qcom_rpm.c 24 KB

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  1. /*
  2. * Copyright (c) 2014, Sony Mobile Communications AB.
  3. * Copyright (c) 2013, The Linux Foundation. All rights reserved.
  4. * Author: Bjorn Andersson <bjorn.andersson@sonymobile.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 and
  8. * only version 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #include <linux/module.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/of_platform.h>
  18. #include <linux/io.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/mfd/qcom_rpm.h>
  21. #include <linux/mfd/syscon.h>
  22. #include <linux/regmap.h>
  23. #include <linux/clk.h>
  24. #include <dt-bindings/mfd/qcom-rpm.h>
  25. struct qcom_rpm_resource {
  26. unsigned target_id;
  27. unsigned status_id;
  28. unsigned select_id;
  29. unsigned size;
  30. };
  31. struct qcom_rpm_data {
  32. u32 version;
  33. const struct qcom_rpm_resource *resource_table;
  34. unsigned int n_resources;
  35. unsigned int req_ctx_off;
  36. unsigned int req_sel_off;
  37. unsigned int ack_ctx_off;
  38. unsigned int ack_sel_off;
  39. unsigned int req_sel_size;
  40. unsigned int ack_sel_size;
  41. };
  42. struct qcom_rpm {
  43. struct device *dev;
  44. struct regmap *ipc_regmap;
  45. unsigned ipc_offset;
  46. unsigned ipc_bit;
  47. struct clk *ramclk;
  48. struct completion ack;
  49. struct mutex lock;
  50. void __iomem *status_regs;
  51. void __iomem *ctrl_regs;
  52. void __iomem *req_regs;
  53. u32 ack_status;
  54. const struct qcom_rpm_data *data;
  55. };
  56. #define RPM_STATUS_REG(rpm, i) ((rpm)->status_regs + (i) * 4)
  57. #define RPM_CTRL_REG(rpm, i) ((rpm)->ctrl_regs + (i) * 4)
  58. #define RPM_REQ_REG(rpm, i) ((rpm)->req_regs + (i) * 4)
  59. #define RPM_REQUEST_TIMEOUT (5 * HZ)
  60. #define RPM_MAX_SEL_SIZE 7
  61. #define RPM_NOTIFICATION BIT(30)
  62. #define RPM_REJECTED BIT(31)
  63. static const struct qcom_rpm_resource apq8064_rpm_resource_table[] = {
  64. [QCOM_RPM_CXO_CLK] = { 25, 9, 5, 1 },
  65. [QCOM_RPM_PXO_CLK] = { 26, 10, 6, 1 },
  66. [QCOM_RPM_APPS_FABRIC_CLK] = { 27, 11, 8, 1 },
  67. [QCOM_RPM_SYS_FABRIC_CLK] = { 28, 12, 9, 1 },
  68. [QCOM_RPM_MM_FABRIC_CLK] = { 29, 13, 10, 1 },
  69. [QCOM_RPM_DAYTONA_FABRIC_CLK] = { 30, 14, 11, 1 },
  70. [QCOM_RPM_SFPB_CLK] = { 31, 15, 12, 1 },
  71. [QCOM_RPM_CFPB_CLK] = { 32, 16, 13, 1 },
  72. [QCOM_RPM_MMFPB_CLK] = { 33, 17, 14, 1 },
  73. [QCOM_RPM_EBI1_CLK] = { 34, 18, 16, 1 },
  74. [QCOM_RPM_APPS_FABRIC_HALT] = { 35, 19, 18, 1 },
  75. [QCOM_RPM_APPS_FABRIC_MODE] = { 37, 20, 19, 1 },
  76. [QCOM_RPM_APPS_FABRIC_IOCTL] = { 40, 21, 20, 1 },
  77. [QCOM_RPM_APPS_FABRIC_ARB] = { 41, 22, 21, 12 },
  78. [QCOM_RPM_SYS_FABRIC_HALT] = { 53, 23, 22, 1 },
  79. [QCOM_RPM_SYS_FABRIC_MODE] = { 55, 24, 23, 1 },
  80. [QCOM_RPM_SYS_FABRIC_IOCTL] = { 58, 25, 24, 1 },
  81. [QCOM_RPM_SYS_FABRIC_ARB] = { 59, 26, 25, 30 },
  82. [QCOM_RPM_MM_FABRIC_HALT] = { 89, 27, 26, 1 },
  83. [QCOM_RPM_MM_FABRIC_MODE] = { 91, 28, 27, 1 },
  84. [QCOM_RPM_MM_FABRIC_IOCTL] = { 94, 29, 28, 1 },
  85. [QCOM_RPM_MM_FABRIC_ARB] = { 95, 30, 29, 21 },
  86. [QCOM_RPM_PM8921_SMPS1] = { 116, 31, 30, 2 },
  87. [QCOM_RPM_PM8921_SMPS2] = { 118, 33, 31, 2 },
  88. [QCOM_RPM_PM8921_SMPS3] = { 120, 35, 32, 2 },
  89. [QCOM_RPM_PM8921_SMPS4] = { 122, 37, 33, 2 },
  90. [QCOM_RPM_PM8921_SMPS5] = { 124, 39, 34, 2 },
  91. [QCOM_RPM_PM8921_SMPS6] = { 126, 41, 35, 2 },
  92. [QCOM_RPM_PM8921_SMPS7] = { 128, 43, 36, 2 },
  93. [QCOM_RPM_PM8921_SMPS8] = { 130, 45, 37, 2 },
  94. [QCOM_RPM_PM8921_LDO1] = { 132, 47, 38, 2 },
  95. [QCOM_RPM_PM8921_LDO2] = { 134, 49, 39, 2 },
  96. [QCOM_RPM_PM8921_LDO3] = { 136, 51, 40, 2 },
  97. [QCOM_RPM_PM8921_LDO4] = { 138, 53, 41, 2 },
  98. [QCOM_RPM_PM8921_LDO5] = { 140, 55, 42, 2 },
  99. [QCOM_RPM_PM8921_LDO6] = { 142, 57, 43, 2 },
  100. [QCOM_RPM_PM8921_LDO7] = { 144, 59, 44, 2 },
  101. [QCOM_RPM_PM8921_LDO8] = { 146, 61, 45, 2 },
  102. [QCOM_RPM_PM8921_LDO9] = { 148, 63, 46, 2 },
  103. [QCOM_RPM_PM8921_LDO10] = { 150, 65, 47, 2 },
  104. [QCOM_RPM_PM8921_LDO11] = { 152, 67, 48, 2 },
  105. [QCOM_RPM_PM8921_LDO12] = { 154, 69, 49, 2 },
  106. [QCOM_RPM_PM8921_LDO13] = { 156, 71, 50, 2 },
  107. [QCOM_RPM_PM8921_LDO14] = { 158, 73, 51, 2 },
  108. [QCOM_RPM_PM8921_LDO15] = { 160, 75, 52, 2 },
  109. [QCOM_RPM_PM8921_LDO16] = { 162, 77, 53, 2 },
  110. [QCOM_RPM_PM8921_LDO17] = { 164, 79, 54, 2 },
  111. [QCOM_RPM_PM8921_LDO18] = { 166, 81, 55, 2 },
  112. [QCOM_RPM_PM8921_LDO19] = { 168, 83, 56, 2 },
  113. [QCOM_RPM_PM8921_LDO20] = { 170, 85, 57, 2 },
  114. [QCOM_RPM_PM8921_LDO21] = { 172, 87, 58, 2 },
  115. [QCOM_RPM_PM8921_LDO22] = { 174, 89, 59, 2 },
  116. [QCOM_RPM_PM8921_LDO23] = { 176, 91, 60, 2 },
  117. [QCOM_RPM_PM8921_LDO24] = { 178, 93, 61, 2 },
  118. [QCOM_RPM_PM8921_LDO25] = { 180, 95, 62, 2 },
  119. [QCOM_RPM_PM8921_LDO26] = { 182, 97, 63, 2 },
  120. [QCOM_RPM_PM8921_LDO27] = { 184, 99, 64, 2 },
  121. [QCOM_RPM_PM8921_LDO28] = { 186, 101, 65, 2 },
  122. [QCOM_RPM_PM8921_LDO29] = { 188, 103, 66, 2 },
  123. [QCOM_RPM_PM8921_CLK1] = { 190, 105, 67, 2 },
  124. [QCOM_RPM_PM8921_CLK2] = { 192, 107, 68, 2 },
  125. [QCOM_RPM_PM8921_LVS1] = { 194, 109, 69, 1 },
  126. [QCOM_RPM_PM8921_LVS2] = { 195, 110, 70, 1 },
  127. [QCOM_RPM_PM8921_LVS3] = { 196, 111, 71, 1 },
  128. [QCOM_RPM_PM8921_LVS4] = { 197, 112, 72, 1 },
  129. [QCOM_RPM_PM8921_LVS5] = { 198, 113, 73, 1 },
  130. [QCOM_RPM_PM8921_LVS6] = { 199, 114, 74, 1 },
  131. [QCOM_RPM_PM8921_LVS7] = { 200, 115, 75, 1 },
  132. [QCOM_RPM_PM8821_SMPS1] = { 201, 116, 76, 2 },
  133. [QCOM_RPM_PM8821_SMPS2] = { 203, 118, 77, 2 },
  134. [QCOM_RPM_PM8821_LDO1] = { 205, 120, 78, 2 },
  135. [QCOM_RPM_PM8921_NCP] = { 207, 122, 80, 2 },
  136. [QCOM_RPM_CXO_BUFFERS] = { 209, 124, 81, 1 },
  137. [QCOM_RPM_USB_OTG_SWITCH] = { 210, 125, 82, 1 },
  138. [QCOM_RPM_HDMI_SWITCH] = { 211, 126, 83, 1 },
  139. [QCOM_RPM_DDR_DMM] = { 212, 127, 84, 2 },
  140. [QCOM_RPM_QDSS_CLK] = { 214, ~0, 7, 1 },
  141. [QCOM_RPM_VDDMIN_GPIO] = { 215, 131, 89, 1 },
  142. };
  143. static const struct qcom_rpm_data apq8064_template = {
  144. .version = 3,
  145. .resource_table = apq8064_rpm_resource_table,
  146. .n_resources = ARRAY_SIZE(apq8064_rpm_resource_table),
  147. .req_ctx_off = 3,
  148. .req_sel_off = 11,
  149. .ack_ctx_off = 15,
  150. .ack_sel_off = 23,
  151. .req_sel_size = 4,
  152. .ack_sel_size = 7,
  153. };
  154. static const struct qcom_rpm_resource msm8660_rpm_resource_table[] = {
  155. [QCOM_RPM_CXO_CLK] = { 32, 12, 5, 1 },
  156. [QCOM_RPM_PXO_CLK] = { 33, 13, 6, 1 },
  157. [QCOM_RPM_PLL_4] = { 34, 14, 7, 1 },
  158. [QCOM_RPM_APPS_FABRIC_CLK] = { 35, 15, 8, 1 },
  159. [QCOM_RPM_SYS_FABRIC_CLK] = { 36, 16, 9, 1 },
  160. [QCOM_RPM_MM_FABRIC_CLK] = { 37, 17, 10, 1 },
  161. [QCOM_RPM_DAYTONA_FABRIC_CLK] = { 38, 18, 11, 1 },
  162. [QCOM_RPM_SFPB_CLK] = { 39, 19, 12, 1 },
  163. [QCOM_RPM_CFPB_CLK] = { 40, 20, 13, 1 },
  164. [QCOM_RPM_MMFPB_CLK] = { 41, 21, 14, 1 },
  165. [QCOM_RPM_SMI_CLK] = { 42, 22, 15, 1 },
  166. [QCOM_RPM_EBI1_CLK] = { 43, 23, 16, 1 },
  167. [QCOM_RPM_APPS_L2_CACHE_CTL] = { 44, 24, 17, 1 },
  168. [QCOM_RPM_APPS_FABRIC_HALT] = { 45, 25, 18, 2 },
  169. [QCOM_RPM_APPS_FABRIC_MODE] = { 47, 26, 19, 3 },
  170. [QCOM_RPM_APPS_FABRIC_ARB] = { 51, 28, 21, 6 },
  171. [QCOM_RPM_SYS_FABRIC_HALT] = { 63, 29, 22, 2 },
  172. [QCOM_RPM_SYS_FABRIC_MODE] = { 65, 30, 23, 3 },
  173. [QCOM_RPM_SYS_FABRIC_ARB] = { 69, 32, 25, 22 },
  174. [QCOM_RPM_MM_FABRIC_HALT] = { 105, 33, 26, 2 },
  175. [QCOM_RPM_MM_FABRIC_MODE] = { 107, 34, 27, 3 },
  176. [QCOM_RPM_MM_FABRIC_ARB] = { 111, 36, 29, 23 },
  177. [QCOM_RPM_PM8901_SMPS0] = { 134, 37, 30, 2 },
  178. [QCOM_RPM_PM8901_SMPS1] = { 136, 39, 31, 2 },
  179. [QCOM_RPM_PM8901_SMPS2] = { 138, 41, 32, 2 },
  180. [QCOM_RPM_PM8901_SMPS3] = { 140, 43, 33, 2 },
  181. [QCOM_RPM_PM8901_SMPS4] = { 142, 45, 34, 2 },
  182. [QCOM_RPM_PM8901_LDO0] = { 144, 47, 35, 2 },
  183. [QCOM_RPM_PM8901_LDO1] = { 146, 49, 36, 2 },
  184. [QCOM_RPM_PM8901_LDO2] = { 148, 51, 37, 2 },
  185. [QCOM_RPM_PM8901_LDO3] = { 150, 53, 38, 2 },
  186. [QCOM_RPM_PM8901_LDO4] = { 152, 55, 39, 2 },
  187. [QCOM_RPM_PM8901_LDO5] = { 154, 57, 40, 2 },
  188. [QCOM_RPM_PM8901_LDO6] = { 156, 59, 41, 2 },
  189. [QCOM_RPM_PM8901_LVS0] = { 158, 61, 42, 1 },
  190. [QCOM_RPM_PM8901_LVS1] = { 159, 62, 43, 1 },
  191. [QCOM_RPM_PM8901_LVS2] = { 160, 63, 44, 1 },
  192. [QCOM_RPM_PM8901_LVS3] = { 161, 64, 45, 1 },
  193. [QCOM_RPM_PM8901_MVS] = { 162, 65, 46, 1 },
  194. [QCOM_RPM_PM8058_SMPS0] = { 163, 66, 47, 2 },
  195. [QCOM_RPM_PM8058_SMPS1] = { 165, 68, 48, 2 },
  196. [QCOM_RPM_PM8058_SMPS2] = { 167, 70, 49, 2 },
  197. [QCOM_RPM_PM8058_SMPS3] = { 169, 72, 50, 2 },
  198. [QCOM_RPM_PM8058_SMPS4] = { 171, 74, 51, 2 },
  199. [QCOM_RPM_PM8058_LDO0] = { 173, 76, 52, 2 },
  200. [QCOM_RPM_PM8058_LDO1] = { 175, 78, 53, 2 },
  201. [QCOM_RPM_PM8058_LDO2] = { 177, 80, 54, 2 },
  202. [QCOM_RPM_PM8058_LDO3] = { 179, 82, 55, 2 },
  203. [QCOM_RPM_PM8058_LDO4] = { 181, 84, 56, 2 },
  204. [QCOM_RPM_PM8058_LDO5] = { 183, 86, 57, 2 },
  205. [QCOM_RPM_PM8058_LDO6] = { 185, 88, 58, 2 },
  206. [QCOM_RPM_PM8058_LDO7] = { 187, 90, 59, 2 },
  207. [QCOM_RPM_PM8058_LDO8] = { 189, 92, 60, 2 },
  208. [QCOM_RPM_PM8058_LDO9] = { 191, 94, 61, 2 },
  209. [QCOM_RPM_PM8058_LDO10] = { 193, 96, 62, 2 },
  210. [QCOM_RPM_PM8058_LDO11] = { 195, 98, 63, 2 },
  211. [QCOM_RPM_PM8058_LDO12] = { 197, 100, 64, 2 },
  212. [QCOM_RPM_PM8058_LDO13] = { 199, 102, 65, 2 },
  213. [QCOM_RPM_PM8058_LDO14] = { 201, 104, 66, 2 },
  214. [QCOM_RPM_PM8058_LDO15] = { 203, 106, 67, 2 },
  215. [QCOM_RPM_PM8058_LDO16] = { 205, 108, 68, 2 },
  216. [QCOM_RPM_PM8058_LDO17] = { 207, 110, 69, 2 },
  217. [QCOM_RPM_PM8058_LDO18] = { 209, 112, 70, 2 },
  218. [QCOM_RPM_PM8058_LDO19] = { 211, 114, 71, 2 },
  219. [QCOM_RPM_PM8058_LDO20] = { 213, 116, 72, 2 },
  220. [QCOM_RPM_PM8058_LDO21] = { 215, 118, 73, 2 },
  221. [QCOM_RPM_PM8058_LDO22] = { 217, 120, 74, 2 },
  222. [QCOM_RPM_PM8058_LDO23] = { 219, 122, 75, 2 },
  223. [QCOM_RPM_PM8058_LDO24] = { 221, 124, 76, 2 },
  224. [QCOM_RPM_PM8058_LDO25] = { 223, 126, 77, 2 },
  225. [QCOM_RPM_PM8058_LVS0] = { 225, 128, 78, 1 },
  226. [QCOM_RPM_PM8058_LVS1] = { 226, 129, 79, 1 },
  227. [QCOM_RPM_PM8058_NCP] = { 227, 130, 80, 2 },
  228. [QCOM_RPM_CXO_BUFFERS] = { 229, 132, 81, 1 },
  229. };
  230. static const struct qcom_rpm_data msm8660_template = {
  231. .version = 2,
  232. .resource_table = msm8660_rpm_resource_table,
  233. .n_resources = ARRAY_SIZE(msm8660_rpm_resource_table),
  234. .req_ctx_off = 3,
  235. .req_sel_off = 11,
  236. .ack_ctx_off = 19,
  237. .ack_sel_off = 27,
  238. .req_sel_size = 7,
  239. .ack_sel_size = 7,
  240. };
  241. static const struct qcom_rpm_resource msm8960_rpm_resource_table[] = {
  242. [QCOM_RPM_CXO_CLK] = { 25, 9, 5, 1 },
  243. [QCOM_RPM_PXO_CLK] = { 26, 10, 6, 1 },
  244. [QCOM_RPM_APPS_FABRIC_CLK] = { 27, 11, 8, 1 },
  245. [QCOM_RPM_SYS_FABRIC_CLK] = { 28, 12, 9, 1 },
  246. [QCOM_RPM_MM_FABRIC_CLK] = { 29, 13, 10, 1 },
  247. [QCOM_RPM_DAYTONA_FABRIC_CLK] = { 30, 14, 11, 1 },
  248. [QCOM_RPM_SFPB_CLK] = { 31, 15, 12, 1 },
  249. [QCOM_RPM_CFPB_CLK] = { 32, 16, 13, 1 },
  250. [QCOM_RPM_MMFPB_CLK] = { 33, 17, 14, 1 },
  251. [QCOM_RPM_EBI1_CLK] = { 34, 18, 16, 1 },
  252. [QCOM_RPM_APPS_FABRIC_HALT] = { 35, 19, 18, 1 },
  253. [QCOM_RPM_APPS_FABRIC_MODE] = { 37, 20, 19, 1 },
  254. [QCOM_RPM_APPS_FABRIC_IOCTL] = { 40, 21, 20, 1 },
  255. [QCOM_RPM_APPS_FABRIC_ARB] = { 41, 22, 21, 12 },
  256. [QCOM_RPM_SYS_FABRIC_HALT] = { 53, 23, 22, 1 },
  257. [QCOM_RPM_SYS_FABRIC_MODE] = { 55, 24, 23, 1 },
  258. [QCOM_RPM_SYS_FABRIC_IOCTL] = { 58, 25, 24, 1 },
  259. [QCOM_RPM_SYS_FABRIC_ARB] = { 59, 26, 25, 29 },
  260. [QCOM_RPM_MM_FABRIC_HALT] = { 88, 27, 26, 1 },
  261. [QCOM_RPM_MM_FABRIC_MODE] = { 90, 28, 27, 1 },
  262. [QCOM_RPM_MM_FABRIC_IOCTL] = { 93, 29, 28, 1 },
  263. [QCOM_RPM_MM_FABRIC_ARB] = { 94, 30, 29, 23 },
  264. [QCOM_RPM_PM8921_SMPS1] = { 117, 31, 30, 2 },
  265. [QCOM_RPM_PM8921_SMPS2] = { 119, 33, 31, 2 },
  266. [QCOM_RPM_PM8921_SMPS3] = { 121, 35, 32, 2 },
  267. [QCOM_RPM_PM8921_SMPS4] = { 123, 37, 33, 2 },
  268. [QCOM_RPM_PM8921_SMPS5] = { 125, 39, 34, 2 },
  269. [QCOM_RPM_PM8921_SMPS6] = { 127, 41, 35, 2 },
  270. [QCOM_RPM_PM8921_SMPS7] = { 129, 43, 36, 2 },
  271. [QCOM_RPM_PM8921_SMPS8] = { 131, 45, 37, 2 },
  272. [QCOM_RPM_PM8921_LDO1] = { 133, 47, 38, 2 },
  273. [QCOM_RPM_PM8921_LDO2] = { 135, 49, 39, 2 },
  274. [QCOM_RPM_PM8921_LDO3] = { 137, 51, 40, 2 },
  275. [QCOM_RPM_PM8921_LDO4] = { 139, 53, 41, 2 },
  276. [QCOM_RPM_PM8921_LDO5] = { 141, 55, 42, 2 },
  277. [QCOM_RPM_PM8921_LDO6] = { 143, 57, 43, 2 },
  278. [QCOM_RPM_PM8921_LDO7] = { 145, 59, 44, 2 },
  279. [QCOM_RPM_PM8921_LDO8] = { 147, 61, 45, 2 },
  280. [QCOM_RPM_PM8921_LDO9] = { 149, 63, 46, 2 },
  281. [QCOM_RPM_PM8921_LDO10] = { 151, 65, 47, 2 },
  282. [QCOM_RPM_PM8921_LDO11] = { 153, 67, 48, 2 },
  283. [QCOM_RPM_PM8921_LDO12] = { 155, 69, 49, 2 },
  284. [QCOM_RPM_PM8921_LDO13] = { 157, 71, 50, 2 },
  285. [QCOM_RPM_PM8921_LDO14] = { 159, 73, 51, 2 },
  286. [QCOM_RPM_PM8921_LDO15] = { 161, 75, 52, 2 },
  287. [QCOM_RPM_PM8921_LDO16] = { 163, 77, 53, 2 },
  288. [QCOM_RPM_PM8921_LDO17] = { 165, 79, 54, 2 },
  289. [QCOM_RPM_PM8921_LDO18] = { 167, 81, 55, 2 },
  290. [QCOM_RPM_PM8921_LDO19] = { 169, 83, 56, 2 },
  291. [QCOM_RPM_PM8921_LDO20] = { 171, 85, 57, 2 },
  292. [QCOM_RPM_PM8921_LDO21] = { 173, 87, 58, 2 },
  293. [QCOM_RPM_PM8921_LDO22] = { 175, 89, 59, 2 },
  294. [QCOM_RPM_PM8921_LDO23] = { 177, 91, 60, 2 },
  295. [QCOM_RPM_PM8921_LDO24] = { 179, 93, 61, 2 },
  296. [QCOM_RPM_PM8921_LDO25] = { 181, 95, 62, 2 },
  297. [QCOM_RPM_PM8921_LDO26] = { 183, 97, 63, 2 },
  298. [QCOM_RPM_PM8921_LDO27] = { 185, 99, 64, 2 },
  299. [QCOM_RPM_PM8921_LDO28] = { 187, 101, 65, 2 },
  300. [QCOM_RPM_PM8921_LDO29] = { 189, 103, 66, 2 },
  301. [QCOM_RPM_PM8921_CLK1] = { 191, 105, 67, 2 },
  302. [QCOM_RPM_PM8921_CLK2] = { 193, 107, 68, 2 },
  303. [QCOM_RPM_PM8921_LVS1] = { 195, 109, 69, 1 },
  304. [QCOM_RPM_PM8921_LVS2] = { 196, 110, 70, 1 },
  305. [QCOM_RPM_PM8921_LVS3] = { 197, 111, 71, 1 },
  306. [QCOM_RPM_PM8921_LVS4] = { 198, 112, 72, 1 },
  307. [QCOM_RPM_PM8921_LVS5] = { 199, 113, 73, 1 },
  308. [QCOM_RPM_PM8921_LVS6] = { 200, 114, 74, 1 },
  309. [QCOM_RPM_PM8921_LVS7] = { 201, 115, 75, 1 },
  310. [QCOM_RPM_PM8921_NCP] = { 202, 116, 80, 2 },
  311. [QCOM_RPM_CXO_BUFFERS] = { 204, 118, 81, 1 },
  312. [QCOM_RPM_USB_OTG_SWITCH] = { 205, 119, 82, 1 },
  313. [QCOM_RPM_HDMI_SWITCH] = { 206, 120, 83, 1 },
  314. [QCOM_RPM_DDR_DMM] = { 207, 121, 84, 2 },
  315. };
  316. static const struct qcom_rpm_data msm8960_template = {
  317. .version = 3,
  318. .resource_table = msm8960_rpm_resource_table,
  319. .n_resources = ARRAY_SIZE(msm8960_rpm_resource_table),
  320. .req_ctx_off = 3,
  321. .req_sel_off = 11,
  322. .ack_ctx_off = 15,
  323. .ack_sel_off = 23,
  324. .req_sel_size = 4,
  325. .ack_sel_size = 7,
  326. };
  327. static const struct qcom_rpm_resource ipq806x_rpm_resource_table[] = {
  328. [QCOM_RPM_CXO_CLK] = { 25, 9, 5, 1 },
  329. [QCOM_RPM_PXO_CLK] = { 26, 10, 6, 1 },
  330. [QCOM_RPM_APPS_FABRIC_CLK] = { 27, 11, 8, 1 },
  331. [QCOM_RPM_SYS_FABRIC_CLK] = { 28, 12, 9, 1 },
  332. [QCOM_RPM_NSS_FABRIC_0_CLK] = { 29, 13, 10, 1 },
  333. [QCOM_RPM_DAYTONA_FABRIC_CLK] = { 30, 14, 11, 1 },
  334. [QCOM_RPM_SFPB_CLK] = { 31, 15, 12, 1 },
  335. [QCOM_RPM_CFPB_CLK] = { 32, 16, 13, 1 },
  336. [QCOM_RPM_NSS_FABRIC_1_CLK] = { 33, 17, 14, 1 },
  337. [QCOM_RPM_EBI1_CLK] = { 34, 18, 16, 1 },
  338. [QCOM_RPM_APPS_FABRIC_HALT] = { 35, 19, 18, 2 },
  339. [QCOM_RPM_APPS_FABRIC_MODE] = { 37, 20, 19, 3 },
  340. [QCOM_RPM_APPS_FABRIC_IOCTL] = { 40, 21, 20, 1 },
  341. [QCOM_RPM_APPS_FABRIC_ARB] = { 41, 22, 21, 12 },
  342. [QCOM_RPM_SYS_FABRIC_HALT] = { 53, 23, 22, 2 },
  343. [QCOM_RPM_SYS_FABRIC_MODE] = { 55, 24, 23, 3 },
  344. [QCOM_RPM_SYS_FABRIC_IOCTL] = { 58, 25, 24, 1 },
  345. [QCOM_RPM_SYS_FABRIC_ARB] = { 59, 26, 25, 30 },
  346. [QCOM_RPM_MM_FABRIC_HALT] = { 89, 27, 26, 2 },
  347. [QCOM_RPM_MM_FABRIC_MODE] = { 91, 28, 27, 3 },
  348. [QCOM_RPM_MM_FABRIC_IOCTL] = { 94, 29, 28, 1 },
  349. [QCOM_RPM_MM_FABRIC_ARB] = { 95, 30, 29, 2 },
  350. [QCOM_RPM_CXO_BUFFERS] = { 209, 33, 31, 1 },
  351. [QCOM_RPM_USB_OTG_SWITCH] = { 210, 34, 32, 1 },
  352. [QCOM_RPM_HDMI_SWITCH] = { 211, 35, 33, 1 },
  353. [QCOM_RPM_DDR_DMM] = { 212, 36, 34, 2 },
  354. [QCOM_RPM_VDDMIN_GPIO] = { 215, 40, 39, 1 },
  355. [QCOM_RPM_SMB208_S1a] = { 216, 41, 90, 2 },
  356. [QCOM_RPM_SMB208_S1b] = { 218, 43, 91, 2 },
  357. [QCOM_RPM_SMB208_S2a] = { 220, 45, 92, 2 },
  358. [QCOM_RPM_SMB208_S2b] = { 222, 47, 93, 2 },
  359. };
  360. static const struct qcom_rpm_data ipq806x_template = {
  361. .version = 3,
  362. .resource_table = ipq806x_rpm_resource_table,
  363. .n_resources = ARRAY_SIZE(ipq806x_rpm_resource_table),
  364. .req_ctx_off = 3,
  365. .req_sel_off = 11,
  366. .ack_ctx_off = 15,
  367. .ack_sel_off = 23,
  368. .req_sel_size = 4,
  369. .ack_sel_size = 7,
  370. };
  371. static const struct qcom_rpm_resource mdm9615_rpm_resource_table[] = {
  372. [QCOM_RPM_CXO_CLK] = { 25, 9, 5, 1 },
  373. [QCOM_RPM_SYS_FABRIC_CLK] = { 26, 10, 9, 1 },
  374. [QCOM_RPM_DAYTONA_FABRIC_CLK] = { 27, 11, 11, 1 },
  375. [QCOM_RPM_SFPB_CLK] = { 28, 12, 12, 1 },
  376. [QCOM_RPM_CFPB_CLK] = { 29, 13, 13, 1 },
  377. [QCOM_RPM_EBI1_CLK] = { 30, 14, 16, 1 },
  378. [QCOM_RPM_APPS_FABRIC_HALT] = { 31, 15, 22, 2 },
  379. [QCOM_RPM_APPS_FABRIC_MODE] = { 33, 16, 23, 3 },
  380. [QCOM_RPM_APPS_FABRIC_IOCTL] = { 36, 17, 24, 1 },
  381. [QCOM_RPM_APPS_FABRIC_ARB] = { 37, 18, 25, 27 },
  382. [QCOM_RPM_PM8018_SMPS1] = { 64, 19, 30, 2 },
  383. [QCOM_RPM_PM8018_SMPS2] = { 66, 21, 31, 2 },
  384. [QCOM_RPM_PM8018_SMPS3] = { 68, 23, 32, 2 },
  385. [QCOM_RPM_PM8018_SMPS4] = { 70, 25, 33, 2 },
  386. [QCOM_RPM_PM8018_SMPS5] = { 72, 27, 34, 2 },
  387. [QCOM_RPM_PM8018_LDO1] = { 74, 29, 35, 2 },
  388. [QCOM_RPM_PM8018_LDO2] = { 76, 31, 36, 2 },
  389. [QCOM_RPM_PM8018_LDO3] = { 78, 33, 37, 2 },
  390. [QCOM_RPM_PM8018_LDO4] = { 80, 35, 38, 2 },
  391. [QCOM_RPM_PM8018_LDO5] = { 82, 37, 39, 2 },
  392. [QCOM_RPM_PM8018_LDO6] = { 84, 39, 40, 2 },
  393. [QCOM_RPM_PM8018_LDO7] = { 86, 41, 41, 2 },
  394. [QCOM_RPM_PM8018_LDO8] = { 88, 43, 42, 2 },
  395. [QCOM_RPM_PM8018_LDO9] = { 90, 45, 43, 2 },
  396. [QCOM_RPM_PM8018_LDO10] = { 92, 47, 44, 2 },
  397. [QCOM_RPM_PM8018_LDO11] = { 94, 49, 45, 2 },
  398. [QCOM_RPM_PM8018_LDO12] = { 96, 51, 46, 2 },
  399. [QCOM_RPM_PM8018_LDO13] = { 98, 53, 47, 2 },
  400. [QCOM_RPM_PM8018_LDO14] = { 100, 55, 48, 2 },
  401. [QCOM_RPM_PM8018_LVS1] = { 102, 57, 49, 1 },
  402. [QCOM_RPM_PM8018_NCP] = { 103, 58, 80, 2 },
  403. [QCOM_RPM_CXO_BUFFERS] = { 105, 60, 81, 1 },
  404. [QCOM_RPM_USB_OTG_SWITCH] = { 106, 61, 82, 1 },
  405. [QCOM_RPM_HDMI_SWITCH] = { 107, 62, 83, 1 },
  406. [QCOM_RPM_VOLTAGE_CORNER] = { 109, 64, 87, 1 },
  407. };
  408. static const struct qcom_rpm_data mdm9615_template = {
  409. .version = 3,
  410. .resource_table = mdm9615_rpm_resource_table,
  411. .n_resources = ARRAY_SIZE(mdm9615_rpm_resource_table),
  412. .req_ctx_off = 3,
  413. .req_sel_off = 11,
  414. .ack_ctx_off = 15,
  415. .ack_sel_off = 23,
  416. .req_sel_size = 4,
  417. .ack_sel_size = 7,
  418. };
  419. static const struct of_device_id qcom_rpm_of_match[] = {
  420. { .compatible = "qcom,rpm-apq8064", .data = &apq8064_template },
  421. { .compatible = "qcom,rpm-msm8660", .data = &msm8660_template },
  422. { .compatible = "qcom,rpm-msm8960", .data = &msm8960_template },
  423. { .compatible = "qcom,rpm-ipq8064", .data = &ipq806x_template },
  424. { .compatible = "qcom,rpm-mdm9615", .data = &mdm9615_template },
  425. { }
  426. };
  427. MODULE_DEVICE_TABLE(of, qcom_rpm_of_match);
  428. int qcom_rpm_write(struct qcom_rpm *rpm,
  429. int state,
  430. int resource,
  431. u32 *buf, size_t count)
  432. {
  433. const struct qcom_rpm_resource *res;
  434. const struct qcom_rpm_data *data = rpm->data;
  435. u32 sel_mask[RPM_MAX_SEL_SIZE] = { 0 };
  436. int left;
  437. int ret = 0;
  438. int i;
  439. if (WARN_ON(resource < 0 || resource >= data->n_resources))
  440. return -EINVAL;
  441. res = &data->resource_table[resource];
  442. if (WARN_ON(res->size != count))
  443. return -EINVAL;
  444. mutex_lock(&rpm->lock);
  445. for (i = 0; i < res->size; i++)
  446. writel_relaxed(buf[i], RPM_REQ_REG(rpm, res->target_id + i));
  447. bitmap_set((unsigned long *)sel_mask, res->select_id, 1);
  448. for (i = 0; i < rpm->data->req_sel_size; i++) {
  449. writel_relaxed(sel_mask[i],
  450. RPM_CTRL_REG(rpm, rpm->data->req_sel_off + i));
  451. }
  452. writel_relaxed(BIT(state), RPM_CTRL_REG(rpm, rpm->data->req_ctx_off));
  453. reinit_completion(&rpm->ack);
  454. regmap_write(rpm->ipc_regmap, rpm->ipc_offset, BIT(rpm->ipc_bit));
  455. left = wait_for_completion_timeout(&rpm->ack, RPM_REQUEST_TIMEOUT);
  456. if (!left)
  457. ret = -ETIMEDOUT;
  458. else if (rpm->ack_status & RPM_REJECTED)
  459. ret = -EIO;
  460. mutex_unlock(&rpm->lock);
  461. return ret;
  462. }
  463. EXPORT_SYMBOL(qcom_rpm_write);
  464. static irqreturn_t qcom_rpm_ack_interrupt(int irq, void *dev)
  465. {
  466. struct qcom_rpm *rpm = dev;
  467. u32 ack;
  468. int i;
  469. ack = readl_relaxed(RPM_CTRL_REG(rpm, rpm->data->ack_ctx_off));
  470. for (i = 0; i < rpm->data->ack_sel_size; i++)
  471. writel_relaxed(0,
  472. RPM_CTRL_REG(rpm, rpm->data->ack_sel_off + i));
  473. writel(0, RPM_CTRL_REG(rpm, rpm->data->ack_ctx_off));
  474. if (ack & RPM_NOTIFICATION) {
  475. dev_warn(rpm->dev, "ignoring notification!\n");
  476. } else {
  477. rpm->ack_status = ack;
  478. complete(&rpm->ack);
  479. }
  480. return IRQ_HANDLED;
  481. }
  482. static irqreturn_t qcom_rpm_err_interrupt(int irq, void *dev)
  483. {
  484. struct qcom_rpm *rpm = dev;
  485. regmap_write(rpm->ipc_regmap, rpm->ipc_offset, BIT(rpm->ipc_bit));
  486. dev_err(rpm->dev, "RPM triggered fatal error\n");
  487. return IRQ_HANDLED;
  488. }
  489. static irqreturn_t qcom_rpm_wakeup_interrupt(int irq, void *dev)
  490. {
  491. return IRQ_HANDLED;
  492. }
  493. static int qcom_rpm_probe(struct platform_device *pdev)
  494. {
  495. const struct of_device_id *match;
  496. struct device_node *syscon_np;
  497. struct resource *res;
  498. struct qcom_rpm *rpm;
  499. u32 fw_version[3];
  500. int irq_wakeup;
  501. int irq_ack;
  502. int irq_err;
  503. int ret;
  504. rpm = devm_kzalloc(&pdev->dev, sizeof(*rpm), GFP_KERNEL);
  505. if (!rpm)
  506. return -ENOMEM;
  507. rpm->dev = &pdev->dev;
  508. mutex_init(&rpm->lock);
  509. init_completion(&rpm->ack);
  510. /* Enable message RAM clock */
  511. rpm->ramclk = devm_clk_get(&pdev->dev, "ram");
  512. if (IS_ERR(rpm->ramclk)) {
  513. ret = PTR_ERR(rpm->ramclk);
  514. if (ret == -EPROBE_DEFER)
  515. return ret;
  516. /*
  517. * Fall through in all other cases, as the clock is
  518. * optional. (Does not exist on all platforms.)
  519. */
  520. rpm->ramclk = NULL;
  521. }
  522. clk_prepare_enable(rpm->ramclk); /* Accepts NULL */
  523. irq_ack = platform_get_irq_byname(pdev, "ack");
  524. if (irq_ack < 0) {
  525. dev_err(&pdev->dev, "required ack interrupt missing\n");
  526. return irq_ack;
  527. }
  528. irq_err = platform_get_irq_byname(pdev, "err");
  529. if (irq_err < 0) {
  530. dev_err(&pdev->dev, "required err interrupt missing\n");
  531. return irq_err;
  532. }
  533. irq_wakeup = platform_get_irq_byname(pdev, "wakeup");
  534. if (irq_wakeup < 0) {
  535. dev_err(&pdev->dev, "required wakeup interrupt missing\n");
  536. return irq_wakeup;
  537. }
  538. match = of_match_device(qcom_rpm_of_match, &pdev->dev);
  539. if (!match)
  540. return -ENODEV;
  541. rpm->data = match->data;
  542. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  543. rpm->status_regs = devm_ioremap_resource(&pdev->dev, res);
  544. if (IS_ERR(rpm->status_regs))
  545. return PTR_ERR(rpm->status_regs);
  546. rpm->ctrl_regs = rpm->status_regs + 0x400;
  547. rpm->req_regs = rpm->status_regs + 0x600;
  548. syscon_np = of_parse_phandle(pdev->dev.of_node, "qcom,ipc", 0);
  549. if (!syscon_np) {
  550. dev_err(&pdev->dev, "no qcom,ipc node\n");
  551. return -ENODEV;
  552. }
  553. rpm->ipc_regmap = syscon_node_to_regmap(syscon_np);
  554. of_node_put(syscon_np);
  555. if (IS_ERR(rpm->ipc_regmap))
  556. return PTR_ERR(rpm->ipc_regmap);
  557. ret = of_property_read_u32_index(pdev->dev.of_node, "qcom,ipc", 1,
  558. &rpm->ipc_offset);
  559. if (ret < 0) {
  560. dev_err(&pdev->dev, "no offset in qcom,ipc\n");
  561. return -EINVAL;
  562. }
  563. ret = of_property_read_u32_index(pdev->dev.of_node, "qcom,ipc", 2,
  564. &rpm->ipc_bit);
  565. if (ret < 0) {
  566. dev_err(&pdev->dev, "no bit in qcom,ipc\n");
  567. return -EINVAL;
  568. }
  569. dev_set_drvdata(&pdev->dev, rpm);
  570. fw_version[0] = readl(RPM_STATUS_REG(rpm, 0));
  571. fw_version[1] = readl(RPM_STATUS_REG(rpm, 1));
  572. fw_version[2] = readl(RPM_STATUS_REG(rpm, 2));
  573. if (fw_version[0] != rpm->data->version) {
  574. dev_err(&pdev->dev,
  575. "RPM version %u.%u.%u incompatible with driver version %u",
  576. fw_version[0],
  577. fw_version[1],
  578. fw_version[2],
  579. rpm->data->version);
  580. return -EFAULT;
  581. }
  582. writel(fw_version[0], RPM_CTRL_REG(rpm, 0));
  583. writel(fw_version[1], RPM_CTRL_REG(rpm, 1));
  584. writel(fw_version[2], RPM_CTRL_REG(rpm, 2));
  585. dev_info(&pdev->dev, "RPM firmware %u.%u.%u\n", fw_version[0],
  586. fw_version[1],
  587. fw_version[2]);
  588. ret = devm_request_irq(&pdev->dev,
  589. irq_ack,
  590. qcom_rpm_ack_interrupt,
  591. IRQF_TRIGGER_RISING,
  592. "qcom_rpm_ack",
  593. rpm);
  594. if (ret) {
  595. dev_err(&pdev->dev, "failed to request ack interrupt\n");
  596. return ret;
  597. }
  598. ret = irq_set_irq_wake(irq_ack, 1);
  599. if (ret)
  600. dev_warn(&pdev->dev, "failed to mark ack irq as wakeup\n");
  601. ret = devm_request_irq(&pdev->dev,
  602. irq_err,
  603. qcom_rpm_err_interrupt,
  604. IRQF_TRIGGER_RISING,
  605. "qcom_rpm_err",
  606. rpm);
  607. if (ret) {
  608. dev_err(&pdev->dev, "failed to request err interrupt\n");
  609. return ret;
  610. }
  611. ret = devm_request_irq(&pdev->dev,
  612. irq_wakeup,
  613. qcom_rpm_wakeup_interrupt,
  614. IRQF_TRIGGER_RISING,
  615. "qcom_rpm_wakeup",
  616. rpm);
  617. if (ret) {
  618. dev_err(&pdev->dev, "failed to request wakeup interrupt\n");
  619. return ret;
  620. }
  621. ret = irq_set_irq_wake(irq_wakeup, 1);
  622. if (ret)
  623. dev_warn(&pdev->dev, "failed to mark wakeup irq as wakeup\n");
  624. return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
  625. }
  626. static int qcom_rpm_remove(struct platform_device *pdev)
  627. {
  628. struct qcom_rpm *rpm = dev_get_drvdata(&pdev->dev);
  629. of_platform_depopulate(&pdev->dev);
  630. clk_disable_unprepare(rpm->ramclk);
  631. return 0;
  632. }
  633. static struct platform_driver qcom_rpm_driver = {
  634. .probe = qcom_rpm_probe,
  635. .remove = qcom_rpm_remove,
  636. .driver = {
  637. .name = "qcom_rpm",
  638. .of_match_table = qcom_rpm_of_match,
  639. },
  640. };
  641. static int __init qcom_rpm_init(void)
  642. {
  643. return platform_driver_register(&qcom_rpm_driver);
  644. }
  645. arch_initcall(qcom_rpm_init);
  646. static void __exit qcom_rpm_exit(void)
  647. {
  648. platform_driver_unregister(&qcom_rpm_driver);
  649. }
  650. module_exit(qcom_rpm_exit)
  651. MODULE_DESCRIPTION("Qualcomm Resource Power Manager driver");
  652. MODULE_LICENSE("GPL v2");
  653. MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>");