max8998-irq.c 6.4 KB

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  1. /*
  2. * Interrupt controller support for MAX8998
  3. *
  4. * Copyright (C) 2010 Samsung Electronics Co.Ltd
  5. * Author: Joonyoung Shim <jy0922.shim@samsung.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the
  9. * Free Software Foundation; either version 2 of the License, or (at your
  10. * option) any later version.
  11. *
  12. */
  13. #include <linux/device.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/irq.h>
  16. #include <linux/irqdomain.h>
  17. #include <linux/mfd/max8998-private.h>
  18. struct max8998_irq_data {
  19. int reg;
  20. int mask;
  21. };
  22. static struct max8998_irq_data max8998_irqs[] = {
  23. [MAX8998_IRQ_DCINF] = {
  24. .reg = 1,
  25. .mask = MAX8998_IRQ_DCINF_MASK,
  26. },
  27. [MAX8998_IRQ_DCINR] = {
  28. .reg = 1,
  29. .mask = MAX8998_IRQ_DCINR_MASK,
  30. },
  31. [MAX8998_IRQ_JIGF] = {
  32. .reg = 1,
  33. .mask = MAX8998_IRQ_JIGF_MASK,
  34. },
  35. [MAX8998_IRQ_JIGR] = {
  36. .reg = 1,
  37. .mask = MAX8998_IRQ_JIGR_MASK,
  38. },
  39. [MAX8998_IRQ_PWRONF] = {
  40. .reg = 1,
  41. .mask = MAX8998_IRQ_PWRONF_MASK,
  42. },
  43. [MAX8998_IRQ_PWRONR] = {
  44. .reg = 1,
  45. .mask = MAX8998_IRQ_PWRONR_MASK,
  46. },
  47. [MAX8998_IRQ_WTSREVNT] = {
  48. .reg = 2,
  49. .mask = MAX8998_IRQ_WTSREVNT_MASK,
  50. },
  51. [MAX8998_IRQ_SMPLEVNT] = {
  52. .reg = 2,
  53. .mask = MAX8998_IRQ_SMPLEVNT_MASK,
  54. },
  55. [MAX8998_IRQ_ALARM1] = {
  56. .reg = 2,
  57. .mask = MAX8998_IRQ_ALARM1_MASK,
  58. },
  59. [MAX8998_IRQ_ALARM0] = {
  60. .reg = 2,
  61. .mask = MAX8998_IRQ_ALARM0_MASK,
  62. },
  63. [MAX8998_IRQ_ONKEY1S] = {
  64. .reg = 3,
  65. .mask = MAX8998_IRQ_ONKEY1S_MASK,
  66. },
  67. [MAX8998_IRQ_TOPOFFR] = {
  68. .reg = 3,
  69. .mask = MAX8998_IRQ_TOPOFFR_MASK,
  70. },
  71. [MAX8998_IRQ_DCINOVPR] = {
  72. .reg = 3,
  73. .mask = MAX8998_IRQ_DCINOVPR_MASK,
  74. },
  75. [MAX8998_IRQ_CHGRSTF] = {
  76. .reg = 3,
  77. .mask = MAX8998_IRQ_CHGRSTF_MASK,
  78. },
  79. [MAX8998_IRQ_DONER] = {
  80. .reg = 3,
  81. .mask = MAX8998_IRQ_DONER_MASK,
  82. },
  83. [MAX8998_IRQ_CHGFAULT] = {
  84. .reg = 3,
  85. .mask = MAX8998_IRQ_CHGFAULT_MASK,
  86. },
  87. [MAX8998_IRQ_LOBAT1] = {
  88. .reg = 4,
  89. .mask = MAX8998_IRQ_LOBAT1_MASK,
  90. },
  91. [MAX8998_IRQ_LOBAT2] = {
  92. .reg = 4,
  93. .mask = MAX8998_IRQ_LOBAT2_MASK,
  94. },
  95. };
  96. static inline struct max8998_irq_data *
  97. irq_to_max8998_irq(struct max8998_dev *max8998, struct irq_data *data)
  98. {
  99. return &max8998_irqs[data->hwirq];
  100. }
  101. static void max8998_irq_lock(struct irq_data *data)
  102. {
  103. struct max8998_dev *max8998 = irq_data_get_irq_chip_data(data);
  104. mutex_lock(&max8998->irqlock);
  105. }
  106. static void max8998_irq_sync_unlock(struct irq_data *data)
  107. {
  108. struct max8998_dev *max8998 = irq_data_get_irq_chip_data(data);
  109. int i;
  110. for (i = 0; i < ARRAY_SIZE(max8998->irq_masks_cur); i++) {
  111. /*
  112. * If there's been a change in the mask write it back
  113. * to the hardware.
  114. */
  115. if (max8998->irq_masks_cur[i] != max8998->irq_masks_cache[i]) {
  116. max8998->irq_masks_cache[i] = max8998->irq_masks_cur[i];
  117. max8998_write_reg(max8998->i2c, MAX8998_REG_IRQM1 + i,
  118. max8998->irq_masks_cur[i]);
  119. }
  120. }
  121. mutex_unlock(&max8998->irqlock);
  122. }
  123. static void max8998_irq_unmask(struct irq_data *data)
  124. {
  125. struct max8998_dev *max8998 = irq_data_get_irq_chip_data(data);
  126. struct max8998_irq_data *irq_data = irq_to_max8998_irq(max8998, data);
  127. max8998->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask;
  128. }
  129. static void max8998_irq_mask(struct irq_data *data)
  130. {
  131. struct max8998_dev *max8998 = irq_data_get_irq_chip_data(data);
  132. struct max8998_irq_data *irq_data = irq_to_max8998_irq(max8998, data);
  133. max8998->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask;
  134. }
  135. static struct irq_chip max8998_irq_chip = {
  136. .name = "max8998",
  137. .irq_bus_lock = max8998_irq_lock,
  138. .irq_bus_sync_unlock = max8998_irq_sync_unlock,
  139. .irq_mask = max8998_irq_mask,
  140. .irq_unmask = max8998_irq_unmask,
  141. };
  142. static irqreturn_t max8998_irq_thread(int irq, void *data)
  143. {
  144. struct max8998_dev *max8998 = data;
  145. u8 irq_reg[MAX8998_NUM_IRQ_REGS];
  146. int ret;
  147. int i;
  148. ret = max8998_bulk_read(max8998->i2c, MAX8998_REG_IRQ1,
  149. MAX8998_NUM_IRQ_REGS, irq_reg);
  150. if (ret < 0) {
  151. dev_err(max8998->dev, "Failed to read interrupt register: %d\n",
  152. ret);
  153. return IRQ_NONE;
  154. }
  155. /* Apply masking */
  156. for (i = 0; i < MAX8998_NUM_IRQ_REGS; i++)
  157. irq_reg[i] &= ~max8998->irq_masks_cur[i];
  158. /* Report */
  159. for (i = 0; i < MAX8998_IRQ_NR; i++) {
  160. if (irq_reg[max8998_irqs[i].reg - 1] & max8998_irqs[i].mask) {
  161. irq = irq_find_mapping(max8998->irq_domain, i);
  162. if (WARN_ON(!irq)) {
  163. disable_irq_nosync(max8998->irq);
  164. return IRQ_NONE;
  165. }
  166. handle_nested_irq(irq);
  167. }
  168. }
  169. return IRQ_HANDLED;
  170. }
  171. int max8998_irq_resume(struct max8998_dev *max8998)
  172. {
  173. if (max8998->irq && max8998->irq_domain)
  174. max8998_irq_thread(max8998->irq, max8998);
  175. return 0;
  176. }
  177. static int max8998_irq_domain_map(struct irq_domain *d, unsigned int irq,
  178. irq_hw_number_t hw)
  179. {
  180. struct max8997_dev *max8998 = d->host_data;
  181. irq_set_chip_data(irq, max8998);
  182. irq_set_chip_and_handler(irq, &max8998_irq_chip, handle_edge_irq);
  183. irq_set_nested_thread(irq, 1);
  184. irq_set_noprobe(irq);
  185. return 0;
  186. }
  187. static const struct irq_domain_ops max8998_irq_domain_ops = {
  188. .map = max8998_irq_domain_map,
  189. };
  190. int max8998_irq_init(struct max8998_dev *max8998)
  191. {
  192. int i;
  193. int ret;
  194. struct irq_domain *domain;
  195. if (!max8998->irq) {
  196. dev_warn(max8998->dev,
  197. "No interrupt specified, no interrupts\n");
  198. return 0;
  199. }
  200. mutex_init(&max8998->irqlock);
  201. /* Mask the individual interrupt sources */
  202. for (i = 0; i < MAX8998_NUM_IRQ_REGS; i++) {
  203. max8998->irq_masks_cur[i] = 0xff;
  204. max8998->irq_masks_cache[i] = 0xff;
  205. max8998_write_reg(max8998->i2c, MAX8998_REG_IRQM1 + i, 0xff);
  206. }
  207. max8998_write_reg(max8998->i2c, MAX8998_REG_STATUSM1, 0xff);
  208. max8998_write_reg(max8998->i2c, MAX8998_REG_STATUSM2, 0xff);
  209. domain = irq_domain_add_simple(NULL, MAX8998_IRQ_NR,
  210. max8998->irq_base, &max8998_irq_domain_ops, max8998);
  211. if (!domain) {
  212. dev_err(max8998->dev, "could not create irq domain\n");
  213. return -ENODEV;
  214. }
  215. max8998->irq_domain = domain;
  216. ret = request_threaded_irq(max8998->irq, NULL, max8998_irq_thread,
  217. IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
  218. "max8998-irq", max8998);
  219. if (ret) {
  220. dev_err(max8998->dev, "Failed to request IRQ %d: %d\n",
  221. max8998->irq, ret);
  222. return ret;
  223. }
  224. if (!max8998->ono)
  225. return 0;
  226. ret = request_threaded_irq(max8998->ono, NULL, max8998_irq_thread,
  227. IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING |
  228. IRQF_ONESHOT, "max8998-ono", max8998);
  229. if (ret)
  230. dev_err(max8998->dev, "Failed to request IRQ %d: %d\n",
  231. max8998->ono, ret);
  232. return 0;
  233. }
  234. void max8998_irq_exit(struct max8998_dev *max8998)
  235. {
  236. if (max8998->ono)
  237. free_irq(max8998->ono, max8998);
  238. if (max8998->irq)
  239. free_irq(max8998->irq, max8998);
  240. }