ab8500-core.c 32 KB

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  1. /*
  2. * Copyright (C) ST-Ericsson SA 2010
  3. *
  4. * License Terms: GNU General Public License v2
  5. * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
  6. * Author: Rabin Vincent <rabin.vincent@stericsson.com>
  7. * Author: Mattias Wallin <mattias.wallin@stericsson.com>
  8. */
  9. #include <linux/kernel.h>
  10. #include <linux/slab.h>
  11. #include <linux/init.h>
  12. #include <linux/irq.h>
  13. #include <linux/irqdomain.h>
  14. #include <linux/delay.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/moduleparam.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/mfd/core.h>
  19. #include <linux/mfd/abx500.h>
  20. #include <linux/mfd/abx500/ab8500.h>
  21. #include <linux/mfd/abx500/ab8500-bm.h>
  22. #include <linux/mfd/dbx500-prcmu.h>
  23. #include <linux/regulator/ab8500.h>
  24. #include <linux/of.h>
  25. #include <linux/of_device.h>
  26. /*
  27. * Interrupt register offsets
  28. * Bank : 0x0E
  29. */
  30. #define AB8500_IT_SOURCE1_REG 0x00
  31. #define AB8500_IT_SOURCE2_REG 0x01
  32. #define AB8500_IT_SOURCE3_REG 0x02
  33. #define AB8500_IT_SOURCE4_REG 0x03
  34. #define AB8500_IT_SOURCE5_REG 0x04
  35. #define AB8500_IT_SOURCE6_REG 0x05
  36. #define AB8500_IT_SOURCE7_REG 0x06
  37. #define AB8500_IT_SOURCE8_REG 0x07
  38. #define AB9540_IT_SOURCE13_REG 0x0C
  39. #define AB8500_IT_SOURCE19_REG 0x12
  40. #define AB8500_IT_SOURCE20_REG 0x13
  41. #define AB8500_IT_SOURCE21_REG 0x14
  42. #define AB8500_IT_SOURCE22_REG 0x15
  43. #define AB8500_IT_SOURCE23_REG 0x16
  44. #define AB8500_IT_SOURCE24_REG 0x17
  45. /*
  46. * latch registers
  47. */
  48. #define AB8500_IT_LATCH1_REG 0x20
  49. #define AB8500_IT_LATCH2_REG 0x21
  50. #define AB8500_IT_LATCH3_REG 0x22
  51. #define AB8500_IT_LATCH4_REG 0x23
  52. #define AB8500_IT_LATCH5_REG 0x24
  53. #define AB8500_IT_LATCH6_REG 0x25
  54. #define AB8500_IT_LATCH7_REG 0x26
  55. #define AB8500_IT_LATCH8_REG 0x27
  56. #define AB8500_IT_LATCH9_REG 0x28
  57. #define AB8500_IT_LATCH10_REG 0x29
  58. #define AB8500_IT_LATCH12_REG 0x2B
  59. #define AB9540_IT_LATCH13_REG 0x2C
  60. #define AB8500_IT_LATCH19_REG 0x32
  61. #define AB8500_IT_LATCH20_REG 0x33
  62. #define AB8500_IT_LATCH21_REG 0x34
  63. #define AB8500_IT_LATCH22_REG 0x35
  64. #define AB8500_IT_LATCH23_REG 0x36
  65. #define AB8500_IT_LATCH24_REG 0x37
  66. /*
  67. * mask registers
  68. */
  69. #define AB8500_IT_MASK1_REG 0x40
  70. #define AB8500_IT_MASK2_REG 0x41
  71. #define AB8500_IT_MASK3_REG 0x42
  72. #define AB8500_IT_MASK4_REG 0x43
  73. #define AB8500_IT_MASK5_REG 0x44
  74. #define AB8500_IT_MASK6_REG 0x45
  75. #define AB8500_IT_MASK7_REG 0x46
  76. #define AB8500_IT_MASK8_REG 0x47
  77. #define AB8500_IT_MASK9_REG 0x48
  78. #define AB8500_IT_MASK10_REG 0x49
  79. #define AB8500_IT_MASK11_REG 0x4A
  80. #define AB8500_IT_MASK12_REG 0x4B
  81. #define AB8500_IT_MASK13_REG 0x4C
  82. #define AB8500_IT_MASK14_REG 0x4D
  83. #define AB8500_IT_MASK15_REG 0x4E
  84. #define AB8500_IT_MASK16_REG 0x4F
  85. #define AB8500_IT_MASK17_REG 0x50
  86. #define AB8500_IT_MASK18_REG 0x51
  87. #define AB8500_IT_MASK19_REG 0x52
  88. #define AB8500_IT_MASK20_REG 0x53
  89. #define AB8500_IT_MASK21_REG 0x54
  90. #define AB8500_IT_MASK22_REG 0x55
  91. #define AB8500_IT_MASK23_REG 0x56
  92. #define AB8500_IT_MASK24_REG 0x57
  93. #define AB8500_IT_MASK25_REG 0x58
  94. /*
  95. * latch hierarchy registers
  96. */
  97. #define AB8500_IT_LATCHHIER1_REG 0x60
  98. #define AB8500_IT_LATCHHIER2_REG 0x61
  99. #define AB8500_IT_LATCHHIER3_REG 0x62
  100. #define AB8540_IT_LATCHHIER4_REG 0x63
  101. #define AB8500_IT_LATCHHIER_NUM 3
  102. #define AB8540_IT_LATCHHIER_NUM 4
  103. #define AB8500_REV_REG 0x80
  104. #define AB8500_IC_NAME_REG 0x82
  105. #define AB8500_SWITCH_OFF_STATUS 0x00
  106. #define AB8500_TURN_ON_STATUS 0x00
  107. #define AB8505_TURN_ON_STATUS_2 0x04
  108. #define AB8500_CH_USBCH_STAT1_REG 0x02
  109. #define VBUS_DET_DBNC100 0x02
  110. #define VBUS_DET_DBNC1 0x01
  111. static DEFINE_SPINLOCK(on_stat_lock);
  112. static u8 turn_on_stat_mask = 0xFF;
  113. static u8 turn_on_stat_set;
  114. static bool no_bm; /* No battery management */
  115. /*
  116. * not really modular, but the easiest way to keep compat with existing
  117. * bootargs behaviour is to continue using module_param here.
  118. */
  119. module_param(no_bm, bool, S_IRUGO);
  120. #define AB9540_MODEM_CTRL2_REG 0x23
  121. #define AB9540_MODEM_CTRL2_SWDBBRSTN_BIT BIT(2)
  122. /*
  123. * Map interrupt numbers to the LATCH and MASK register offsets, Interrupt
  124. * numbers are indexed into this array with (num / 8). The interupts are
  125. * defined in linux/mfd/ab8500.h
  126. *
  127. * This is one off from the register names, i.e. AB8500_IT_MASK1_REG is at
  128. * offset 0.
  129. */
  130. /* AB8500 support */
  131. static const int ab8500_irq_regoffset[AB8500_NUM_IRQ_REGS] = {
  132. 0, 1, 2, 3, 4, 6, 7, 8, 9, 11, 18, 19, 20, 21,
  133. };
  134. /* AB9540 / AB8505 support */
  135. static const int ab9540_irq_regoffset[AB9540_NUM_IRQ_REGS] = {
  136. 0, 1, 2, 3, 4, 6, 7, 8, 9, 11, 18, 19, 20, 21, 12, 13, 24, 5, 22, 23
  137. };
  138. /* AB8540 support */
  139. static const int ab8540_irq_regoffset[AB8540_NUM_IRQ_REGS] = {
  140. 0, 1, 2, 3, 4, -1, -1, -1, -1, 11, 18, 19, 20, 21, 12, 13, 24, 5, 22,
  141. 23, 25, 26, 27, 28, 29, 30, 31,
  142. };
  143. static const char ab8500_version_str[][7] = {
  144. [AB8500_VERSION_AB8500] = "AB8500",
  145. [AB8500_VERSION_AB8505] = "AB8505",
  146. [AB8500_VERSION_AB9540] = "AB9540",
  147. [AB8500_VERSION_AB8540] = "AB8540",
  148. };
  149. static int ab8500_prcmu_write(struct ab8500 *ab8500, u16 addr, u8 data)
  150. {
  151. int ret;
  152. ret = prcmu_abb_write((u8)(addr >> 8), (u8)(addr & 0xFF), &data, 1);
  153. if (ret < 0)
  154. dev_err(ab8500->dev, "prcmu i2c error %d\n", ret);
  155. return ret;
  156. }
  157. static int ab8500_prcmu_write_masked(struct ab8500 *ab8500, u16 addr, u8 mask,
  158. u8 data)
  159. {
  160. int ret;
  161. ret = prcmu_abb_write_masked((u8)(addr >> 8), (u8)(addr & 0xFF), &data,
  162. &mask, 1);
  163. if (ret < 0)
  164. dev_err(ab8500->dev, "prcmu i2c error %d\n", ret);
  165. return ret;
  166. }
  167. static int ab8500_prcmu_read(struct ab8500 *ab8500, u16 addr)
  168. {
  169. int ret;
  170. u8 data;
  171. ret = prcmu_abb_read((u8)(addr >> 8), (u8)(addr & 0xFF), &data, 1);
  172. if (ret < 0) {
  173. dev_err(ab8500->dev, "prcmu i2c error %d\n", ret);
  174. return ret;
  175. }
  176. return (int)data;
  177. }
  178. static int ab8500_get_chip_id(struct device *dev)
  179. {
  180. struct ab8500 *ab8500;
  181. if (!dev)
  182. return -EINVAL;
  183. ab8500 = dev_get_drvdata(dev->parent);
  184. return ab8500 ? (int)ab8500->chip_id : -EINVAL;
  185. }
  186. static int set_register_interruptible(struct ab8500 *ab8500, u8 bank,
  187. u8 reg, u8 data)
  188. {
  189. int ret;
  190. /*
  191. * Put the u8 bank and u8 register together into a an u16.
  192. * The bank on higher 8 bits and register in lower 8 bits.
  193. */
  194. u16 addr = ((u16)bank) << 8 | reg;
  195. dev_vdbg(ab8500->dev, "wr: addr %#x <= %#x\n", addr, data);
  196. mutex_lock(&ab8500->lock);
  197. ret = ab8500->write(ab8500, addr, data);
  198. if (ret < 0)
  199. dev_err(ab8500->dev, "failed to write reg %#x: %d\n",
  200. addr, ret);
  201. mutex_unlock(&ab8500->lock);
  202. return ret;
  203. }
  204. static int ab8500_set_register(struct device *dev, u8 bank,
  205. u8 reg, u8 value)
  206. {
  207. int ret;
  208. struct ab8500 *ab8500 = dev_get_drvdata(dev->parent);
  209. atomic_inc(&ab8500->transfer_ongoing);
  210. ret = set_register_interruptible(ab8500, bank, reg, value);
  211. atomic_dec(&ab8500->transfer_ongoing);
  212. return ret;
  213. }
  214. static int get_register_interruptible(struct ab8500 *ab8500, u8 bank,
  215. u8 reg, u8 *value)
  216. {
  217. int ret;
  218. u16 addr = ((u16)bank) << 8 | reg;
  219. mutex_lock(&ab8500->lock);
  220. ret = ab8500->read(ab8500, addr);
  221. if (ret < 0)
  222. dev_err(ab8500->dev, "failed to read reg %#x: %d\n",
  223. addr, ret);
  224. else
  225. *value = ret;
  226. mutex_unlock(&ab8500->lock);
  227. dev_vdbg(ab8500->dev, "rd: addr %#x => data %#x\n", addr, ret);
  228. return (ret < 0) ? ret : 0;
  229. }
  230. static int ab8500_get_register(struct device *dev, u8 bank,
  231. u8 reg, u8 *value)
  232. {
  233. int ret;
  234. struct ab8500 *ab8500 = dev_get_drvdata(dev->parent);
  235. atomic_inc(&ab8500->transfer_ongoing);
  236. ret = get_register_interruptible(ab8500, bank, reg, value);
  237. atomic_dec(&ab8500->transfer_ongoing);
  238. return ret;
  239. }
  240. static int mask_and_set_register_interruptible(struct ab8500 *ab8500, u8 bank,
  241. u8 reg, u8 bitmask, u8 bitvalues)
  242. {
  243. int ret;
  244. u16 addr = ((u16)bank) << 8 | reg;
  245. mutex_lock(&ab8500->lock);
  246. if (ab8500->write_masked == NULL) {
  247. u8 data;
  248. ret = ab8500->read(ab8500, addr);
  249. if (ret < 0) {
  250. dev_err(ab8500->dev, "failed to read reg %#x: %d\n",
  251. addr, ret);
  252. goto out;
  253. }
  254. data = (u8)ret;
  255. data = (~bitmask & data) | (bitmask & bitvalues);
  256. ret = ab8500->write(ab8500, addr, data);
  257. if (ret < 0)
  258. dev_err(ab8500->dev, "failed to write reg %#x: %d\n",
  259. addr, ret);
  260. dev_vdbg(ab8500->dev, "mask: addr %#x => data %#x\n", addr,
  261. data);
  262. goto out;
  263. }
  264. ret = ab8500->write_masked(ab8500, addr, bitmask, bitvalues);
  265. if (ret < 0)
  266. dev_err(ab8500->dev, "failed to modify reg %#x: %d\n", addr,
  267. ret);
  268. out:
  269. mutex_unlock(&ab8500->lock);
  270. return ret;
  271. }
  272. static int ab8500_mask_and_set_register(struct device *dev,
  273. u8 bank, u8 reg, u8 bitmask, u8 bitvalues)
  274. {
  275. int ret;
  276. struct ab8500 *ab8500 = dev_get_drvdata(dev->parent);
  277. atomic_inc(&ab8500->transfer_ongoing);
  278. ret = mask_and_set_register_interruptible(ab8500, bank, reg,
  279. bitmask, bitvalues);
  280. atomic_dec(&ab8500->transfer_ongoing);
  281. return ret;
  282. }
  283. static struct abx500_ops ab8500_ops = {
  284. .get_chip_id = ab8500_get_chip_id,
  285. .get_register = ab8500_get_register,
  286. .set_register = ab8500_set_register,
  287. .get_register_page = NULL,
  288. .set_register_page = NULL,
  289. .mask_and_set_register = ab8500_mask_and_set_register,
  290. .event_registers_startup_state_get = NULL,
  291. .startup_irq_enabled = NULL,
  292. .dump_all_banks = ab8500_dump_all_banks,
  293. };
  294. static void ab8500_irq_lock(struct irq_data *data)
  295. {
  296. struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data);
  297. mutex_lock(&ab8500->irq_lock);
  298. atomic_inc(&ab8500->transfer_ongoing);
  299. }
  300. static void ab8500_irq_sync_unlock(struct irq_data *data)
  301. {
  302. struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data);
  303. int i;
  304. for (i = 0; i < ab8500->mask_size; i++) {
  305. u8 old = ab8500->oldmask[i];
  306. u8 new = ab8500->mask[i];
  307. int reg;
  308. if (new == old)
  309. continue;
  310. /*
  311. * Interrupt register 12 doesn't exist prior to AB8500 version
  312. * 2.0
  313. */
  314. if (ab8500->irq_reg_offset[i] == 11 &&
  315. is_ab8500_1p1_or_earlier(ab8500))
  316. continue;
  317. if (ab8500->irq_reg_offset[i] < 0)
  318. continue;
  319. ab8500->oldmask[i] = new;
  320. reg = AB8500_IT_MASK1_REG + ab8500->irq_reg_offset[i];
  321. set_register_interruptible(ab8500, AB8500_INTERRUPT, reg, new);
  322. }
  323. atomic_dec(&ab8500->transfer_ongoing);
  324. mutex_unlock(&ab8500->irq_lock);
  325. }
  326. static void ab8500_irq_mask(struct irq_data *data)
  327. {
  328. struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data);
  329. int offset = data->hwirq;
  330. int index = offset / 8;
  331. int mask = 1 << (offset % 8);
  332. ab8500->mask[index] |= mask;
  333. /* The AB8500 GPIOs have two interrupts each (rising & falling). */
  334. if (offset >= AB8500_INT_GPIO6R && offset <= AB8500_INT_GPIO41R)
  335. ab8500->mask[index + 2] |= mask;
  336. if (offset >= AB9540_INT_GPIO50R && offset <= AB9540_INT_GPIO54R)
  337. ab8500->mask[index + 1] |= mask;
  338. if (offset == AB8540_INT_GPIO43R || offset == AB8540_INT_GPIO44R)
  339. /* Here the falling IRQ is one bit lower */
  340. ab8500->mask[index] |= (mask << 1);
  341. }
  342. static void ab8500_irq_unmask(struct irq_data *data)
  343. {
  344. struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data);
  345. unsigned int type = irqd_get_trigger_type(data);
  346. int offset = data->hwirq;
  347. int index = offset / 8;
  348. int mask = 1 << (offset % 8);
  349. if (type & IRQ_TYPE_EDGE_RISING)
  350. ab8500->mask[index] &= ~mask;
  351. /* The AB8500 GPIOs have two interrupts each (rising & falling). */
  352. if (type & IRQ_TYPE_EDGE_FALLING) {
  353. if (offset >= AB8500_INT_GPIO6R && offset <= AB8500_INT_GPIO41R)
  354. ab8500->mask[index + 2] &= ~mask;
  355. else if (offset >= AB9540_INT_GPIO50R &&
  356. offset <= AB9540_INT_GPIO54R)
  357. ab8500->mask[index + 1] &= ~mask;
  358. else if (offset == AB8540_INT_GPIO43R ||
  359. offset == AB8540_INT_GPIO44R)
  360. /* Here the falling IRQ is one bit lower */
  361. ab8500->mask[index] &= ~(mask << 1);
  362. else
  363. ab8500->mask[index] &= ~mask;
  364. } else {
  365. /* Satisfies the case where type is not set. */
  366. ab8500->mask[index] &= ~mask;
  367. }
  368. }
  369. static int ab8500_irq_set_type(struct irq_data *data, unsigned int type)
  370. {
  371. return 0;
  372. }
  373. static struct irq_chip ab8500_irq_chip = {
  374. .name = "ab8500",
  375. .irq_bus_lock = ab8500_irq_lock,
  376. .irq_bus_sync_unlock = ab8500_irq_sync_unlock,
  377. .irq_mask = ab8500_irq_mask,
  378. .irq_disable = ab8500_irq_mask,
  379. .irq_unmask = ab8500_irq_unmask,
  380. .irq_set_type = ab8500_irq_set_type,
  381. };
  382. static void update_latch_offset(u8 *offset, int i)
  383. {
  384. /* Fix inconsistent ITFromLatch25 bit mapping... */
  385. if (unlikely(*offset == 17))
  386. *offset = 24;
  387. /* Fix inconsistent ab8540 bit mapping... */
  388. if (unlikely(*offset == 16))
  389. *offset = 25;
  390. if ((i == 3) && (*offset >= 24))
  391. *offset += 2;
  392. }
  393. static int ab8500_handle_hierarchical_line(struct ab8500 *ab8500,
  394. int latch_offset, u8 latch_val)
  395. {
  396. int int_bit, line, i;
  397. for (i = 0; i < ab8500->mask_size; i++)
  398. if (ab8500->irq_reg_offset[i] == latch_offset)
  399. break;
  400. if (i >= ab8500->mask_size) {
  401. dev_err(ab8500->dev, "Register offset 0x%2x not declared\n",
  402. latch_offset);
  403. return -ENXIO;
  404. }
  405. /* ignore masked out interrupts */
  406. latch_val &= ~ab8500->mask[i];
  407. while (latch_val) {
  408. int_bit = __ffs(latch_val);
  409. line = (i << 3) + int_bit;
  410. latch_val &= ~(1 << int_bit);
  411. /*
  412. * This handles the falling edge hwirqs from the GPIO
  413. * lines. Route them back to the line registered for the
  414. * rising IRQ, as this is merely a flag for the same IRQ
  415. * in linux terms.
  416. */
  417. if (line >= AB8500_INT_GPIO6F && line <= AB8500_INT_GPIO41F)
  418. line -= 16;
  419. if (line >= AB9540_INT_GPIO50F && line <= AB9540_INT_GPIO54F)
  420. line -= 8;
  421. if (line == AB8540_INT_GPIO43F || line == AB8540_INT_GPIO44F)
  422. line += 1;
  423. handle_nested_irq(irq_create_mapping(ab8500->domain, line));
  424. }
  425. return 0;
  426. }
  427. static int ab8500_handle_hierarchical_latch(struct ab8500 *ab8500,
  428. int hier_offset, u8 hier_val)
  429. {
  430. int latch_bit, status;
  431. u8 latch_offset, latch_val;
  432. do {
  433. latch_bit = __ffs(hier_val);
  434. latch_offset = (hier_offset << 3) + latch_bit;
  435. update_latch_offset(&latch_offset, hier_offset);
  436. status = get_register_interruptible(ab8500,
  437. AB8500_INTERRUPT,
  438. AB8500_IT_LATCH1_REG + latch_offset,
  439. &latch_val);
  440. if (status < 0 || latch_val == 0)
  441. goto discard;
  442. status = ab8500_handle_hierarchical_line(ab8500,
  443. latch_offset, latch_val);
  444. if (status < 0)
  445. return status;
  446. discard:
  447. hier_val &= ~(1 << latch_bit);
  448. } while (hier_val);
  449. return 0;
  450. }
  451. static irqreturn_t ab8500_hierarchical_irq(int irq, void *dev)
  452. {
  453. struct ab8500 *ab8500 = dev;
  454. u8 i;
  455. dev_vdbg(ab8500->dev, "interrupt\n");
  456. /* Hierarchical interrupt version */
  457. for (i = 0; i < (ab8500->it_latchhier_num); i++) {
  458. int status;
  459. u8 hier_val;
  460. status = get_register_interruptible(ab8500, AB8500_INTERRUPT,
  461. AB8500_IT_LATCHHIER1_REG + i, &hier_val);
  462. if (status < 0 || hier_val == 0)
  463. continue;
  464. status = ab8500_handle_hierarchical_latch(ab8500, i, hier_val);
  465. if (status < 0)
  466. break;
  467. }
  468. return IRQ_HANDLED;
  469. }
  470. static int ab8500_irq_map(struct irq_domain *d, unsigned int virq,
  471. irq_hw_number_t hwirq)
  472. {
  473. struct ab8500 *ab8500 = d->host_data;
  474. if (!ab8500)
  475. return -EINVAL;
  476. irq_set_chip_data(virq, ab8500);
  477. irq_set_chip_and_handler(virq, &ab8500_irq_chip,
  478. handle_simple_irq);
  479. irq_set_nested_thread(virq, 1);
  480. irq_set_noprobe(virq);
  481. return 0;
  482. }
  483. static const struct irq_domain_ops ab8500_irq_ops = {
  484. .map = ab8500_irq_map,
  485. .xlate = irq_domain_xlate_twocell,
  486. };
  487. static int ab8500_irq_init(struct ab8500 *ab8500, struct device_node *np)
  488. {
  489. int num_irqs;
  490. if (is_ab8540(ab8500))
  491. num_irqs = AB8540_NR_IRQS;
  492. else if (is_ab9540(ab8500))
  493. num_irqs = AB9540_NR_IRQS;
  494. else if (is_ab8505(ab8500))
  495. num_irqs = AB8505_NR_IRQS;
  496. else
  497. num_irqs = AB8500_NR_IRQS;
  498. /* If ->irq_base is zero this will give a linear mapping */
  499. ab8500->domain = irq_domain_add_simple(ab8500->dev->of_node,
  500. num_irqs, 0,
  501. &ab8500_irq_ops, ab8500);
  502. if (!ab8500->domain) {
  503. dev_err(ab8500->dev, "Failed to create irqdomain\n");
  504. return -ENODEV;
  505. }
  506. return 0;
  507. }
  508. int ab8500_suspend(struct ab8500 *ab8500)
  509. {
  510. if (atomic_read(&ab8500->transfer_ongoing))
  511. return -EINVAL;
  512. return 0;
  513. }
  514. static const struct mfd_cell ab8500_bm_devs[] = {
  515. {
  516. .name = "ab8500-charger",
  517. .of_compatible = "stericsson,ab8500-charger",
  518. .platform_data = &ab8500_bm_data,
  519. .pdata_size = sizeof(ab8500_bm_data),
  520. },
  521. {
  522. .name = "ab8500-btemp",
  523. .of_compatible = "stericsson,ab8500-btemp",
  524. .platform_data = &ab8500_bm_data,
  525. .pdata_size = sizeof(ab8500_bm_data),
  526. },
  527. {
  528. .name = "ab8500-fg",
  529. .of_compatible = "stericsson,ab8500-fg",
  530. .platform_data = &ab8500_bm_data,
  531. .pdata_size = sizeof(ab8500_bm_data),
  532. },
  533. {
  534. .name = "ab8500-chargalg",
  535. .of_compatible = "stericsson,ab8500-chargalg",
  536. .platform_data = &ab8500_bm_data,
  537. .pdata_size = sizeof(ab8500_bm_data),
  538. },
  539. };
  540. static const struct mfd_cell ab8500_devs[] = {
  541. #ifdef CONFIG_DEBUG_FS
  542. {
  543. .name = "ab8500-debug",
  544. .of_compatible = "stericsson,ab8500-debug",
  545. },
  546. #endif
  547. {
  548. .name = "ab8500-sysctrl",
  549. .of_compatible = "stericsson,ab8500-sysctrl",
  550. },
  551. {
  552. .name = "ab8500-ext-regulator",
  553. .of_compatible = "stericsson,ab8500-ext-regulator",
  554. },
  555. {
  556. .name = "ab8500-regulator",
  557. .of_compatible = "stericsson,ab8500-regulator",
  558. },
  559. {
  560. .name = "ab8500-clk",
  561. .of_compatible = "stericsson,ab8500-clk",
  562. },
  563. {
  564. .name = "ab8500-gpadc",
  565. .of_compatible = "stericsson,ab8500-gpadc",
  566. },
  567. {
  568. .name = "ab8500-rtc",
  569. .of_compatible = "stericsson,ab8500-rtc",
  570. },
  571. {
  572. .name = "ab8500-acc-det",
  573. .of_compatible = "stericsson,ab8500-acc-det",
  574. },
  575. {
  576. .name = "ab8500-poweron-key",
  577. .of_compatible = "stericsson,ab8500-poweron-key",
  578. },
  579. {
  580. .name = "ab8500-pwm",
  581. .of_compatible = "stericsson,ab8500-pwm",
  582. .id = 1,
  583. },
  584. {
  585. .name = "ab8500-pwm",
  586. .of_compatible = "stericsson,ab8500-pwm",
  587. .id = 2,
  588. },
  589. {
  590. .name = "ab8500-pwm",
  591. .of_compatible = "stericsson,ab8500-pwm",
  592. .id = 3,
  593. },
  594. {
  595. .name = "ab8500-denc",
  596. .of_compatible = "stericsson,ab8500-denc",
  597. },
  598. {
  599. .name = "pinctrl-ab8500",
  600. .of_compatible = "stericsson,ab8500-gpio",
  601. },
  602. {
  603. .name = "abx500-temp",
  604. .of_compatible = "stericsson,abx500-temp",
  605. },
  606. {
  607. .name = "ab8500-usb",
  608. .of_compatible = "stericsson,ab8500-usb",
  609. },
  610. {
  611. .name = "ab8500-codec",
  612. .of_compatible = "stericsson,ab8500-codec",
  613. },
  614. };
  615. static const struct mfd_cell ab9540_devs[] = {
  616. #ifdef CONFIG_DEBUG_FS
  617. {
  618. .name = "ab8500-debug",
  619. },
  620. #endif
  621. {
  622. .name = "ab8500-sysctrl",
  623. },
  624. {
  625. .name = "ab8500-ext-regulator",
  626. },
  627. {
  628. .name = "ab8500-regulator",
  629. },
  630. {
  631. .name = "abx500-clk",
  632. .of_compatible = "stericsson,abx500-clk",
  633. },
  634. {
  635. .name = "ab8500-gpadc",
  636. .of_compatible = "stericsson,ab8500-gpadc",
  637. },
  638. {
  639. .name = "ab8500-rtc",
  640. },
  641. {
  642. .name = "ab8500-acc-det",
  643. },
  644. {
  645. .name = "ab8500-poweron-key",
  646. },
  647. {
  648. .name = "ab8500-pwm",
  649. .id = 1,
  650. },
  651. {
  652. .name = "abx500-temp",
  653. },
  654. {
  655. .name = "pinctrl-ab9540",
  656. .of_compatible = "stericsson,ab9540-gpio",
  657. },
  658. {
  659. .name = "ab9540-usb",
  660. },
  661. {
  662. .name = "ab9540-codec",
  663. },
  664. {
  665. .name = "ab-iddet",
  666. },
  667. };
  668. /* Device list for ab8505 */
  669. static const struct mfd_cell ab8505_devs[] = {
  670. #ifdef CONFIG_DEBUG_FS
  671. {
  672. .name = "ab8500-debug",
  673. },
  674. #endif
  675. {
  676. .name = "ab8500-sysctrl",
  677. },
  678. {
  679. .name = "ab8500-regulator",
  680. },
  681. {
  682. .name = "abx500-clk",
  683. .of_compatible = "stericsson,abx500-clk",
  684. },
  685. {
  686. .name = "ab8500-gpadc",
  687. .of_compatible = "stericsson,ab8500-gpadc",
  688. },
  689. {
  690. .name = "ab8500-rtc",
  691. },
  692. {
  693. .name = "ab8500-acc-det",
  694. },
  695. {
  696. .name = "ab8500-poweron-key",
  697. },
  698. {
  699. .name = "ab8500-pwm",
  700. .id = 1,
  701. },
  702. {
  703. .name = "pinctrl-ab8505",
  704. },
  705. {
  706. .name = "ab8500-usb",
  707. },
  708. {
  709. .name = "ab8500-codec",
  710. },
  711. {
  712. .name = "ab-iddet",
  713. },
  714. };
  715. static const struct mfd_cell ab8540_devs[] = {
  716. #ifdef CONFIG_DEBUG_FS
  717. {
  718. .name = "ab8500-debug",
  719. },
  720. #endif
  721. {
  722. .name = "ab8500-sysctrl",
  723. },
  724. {
  725. .name = "ab8500-ext-regulator",
  726. },
  727. {
  728. .name = "ab8500-regulator",
  729. },
  730. {
  731. .name = "abx500-clk",
  732. .of_compatible = "stericsson,abx500-clk",
  733. },
  734. {
  735. .name = "ab8500-gpadc",
  736. .of_compatible = "stericsson,ab8500-gpadc",
  737. },
  738. {
  739. .name = "ab8500-acc-det",
  740. },
  741. {
  742. .name = "ab8500-poweron-key",
  743. },
  744. {
  745. .name = "ab8500-pwm",
  746. .id = 1,
  747. },
  748. {
  749. .name = "abx500-temp",
  750. },
  751. {
  752. .name = "pinctrl-ab8540",
  753. },
  754. {
  755. .name = "ab8540-usb",
  756. },
  757. {
  758. .name = "ab8540-codec",
  759. },
  760. {
  761. .name = "ab-iddet",
  762. },
  763. };
  764. static const struct mfd_cell ab8540_cut1_devs[] = {
  765. {
  766. .name = "ab8500-rtc",
  767. .of_compatible = "stericsson,ab8500-rtc",
  768. },
  769. };
  770. static const struct mfd_cell ab8540_cut2_devs[] = {
  771. {
  772. .name = "ab8540-rtc",
  773. .of_compatible = "stericsson,ab8540-rtc",
  774. },
  775. };
  776. static ssize_t show_chip_id(struct device *dev,
  777. struct device_attribute *attr, char *buf)
  778. {
  779. struct ab8500 *ab8500;
  780. ab8500 = dev_get_drvdata(dev);
  781. return sprintf(buf, "%#x\n", ab8500 ? ab8500->chip_id : -EINVAL);
  782. }
  783. /*
  784. * ab8500 has switched off due to (SWITCH_OFF_STATUS):
  785. * 0x01 Swoff bit programming
  786. * 0x02 Thermal protection activation
  787. * 0x04 Vbat lower then BattOk falling threshold
  788. * 0x08 Watchdog expired
  789. * 0x10 Non presence of 32kHz clock
  790. * 0x20 Battery level lower than power on reset threshold
  791. * 0x40 Power on key 1 pressed longer than 10 seconds
  792. * 0x80 DB8500 thermal shutdown
  793. */
  794. static ssize_t show_switch_off_status(struct device *dev,
  795. struct device_attribute *attr, char *buf)
  796. {
  797. int ret;
  798. u8 value;
  799. struct ab8500 *ab8500;
  800. ab8500 = dev_get_drvdata(dev);
  801. ret = get_register_interruptible(ab8500, AB8500_RTC,
  802. AB8500_SWITCH_OFF_STATUS, &value);
  803. if (ret < 0)
  804. return ret;
  805. return sprintf(buf, "%#x\n", value);
  806. }
  807. /* use mask and set to override the register turn_on_stat value */
  808. void ab8500_override_turn_on_stat(u8 mask, u8 set)
  809. {
  810. spin_lock(&on_stat_lock);
  811. turn_on_stat_mask = mask;
  812. turn_on_stat_set = set;
  813. spin_unlock(&on_stat_lock);
  814. }
  815. /*
  816. * ab8500 has turned on due to (TURN_ON_STATUS):
  817. * 0x01 PORnVbat
  818. * 0x02 PonKey1dbF
  819. * 0x04 PonKey2dbF
  820. * 0x08 RTCAlarm
  821. * 0x10 MainChDet
  822. * 0x20 VbusDet
  823. * 0x40 UsbIDDetect
  824. * 0x80 Reserved
  825. */
  826. static ssize_t show_turn_on_status(struct device *dev,
  827. struct device_attribute *attr, char *buf)
  828. {
  829. int ret;
  830. u8 value;
  831. struct ab8500 *ab8500;
  832. ab8500 = dev_get_drvdata(dev);
  833. ret = get_register_interruptible(ab8500, AB8500_SYS_CTRL1_BLOCK,
  834. AB8500_TURN_ON_STATUS, &value);
  835. if (ret < 0)
  836. return ret;
  837. /*
  838. * In L9540, turn_on_status register is not updated correctly if
  839. * the device is rebooted with AC/USB charger connected. Due to
  840. * this, the device boots android instead of entering into charge
  841. * only mode. Read the AC/USB status register to detect the charger
  842. * presence and update the turn on status manually.
  843. */
  844. if (is_ab9540(ab8500)) {
  845. spin_lock(&on_stat_lock);
  846. value = (value & turn_on_stat_mask) | turn_on_stat_set;
  847. spin_unlock(&on_stat_lock);
  848. }
  849. return sprintf(buf, "%#x\n", value);
  850. }
  851. static ssize_t show_turn_on_status_2(struct device *dev,
  852. struct device_attribute *attr, char *buf)
  853. {
  854. int ret;
  855. u8 value;
  856. struct ab8500 *ab8500;
  857. ab8500 = dev_get_drvdata(dev);
  858. ret = get_register_interruptible(ab8500, AB8500_SYS_CTRL1_BLOCK,
  859. AB8505_TURN_ON_STATUS_2, &value);
  860. if (ret < 0)
  861. return ret;
  862. return sprintf(buf, "%#x\n", (value & 0x1));
  863. }
  864. static ssize_t show_ab9540_dbbrstn(struct device *dev,
  865. struct device_attribute *attr, char *buf)
  866. {
  867. struct ab8500 *ab8500;
  868. int ret;
  869. u8 value;
  870. ab8500 = dev_get_drvdata(dev);
  871. ret = get_register_interruptible(ab8500, AB8500_REGU_CTRL2,
  872. AB9540_MODEM_CTRL2_REG, &value);
  873. if (ret < 0)
  874. return ret;
  875. return sprintf(buf, "%d\n",
  876. (value & AB9540_MODEM_CTRL2_SWDBBRSTN_BIT) ? 1 : 0);
  877. }
  878. static ssize_t store_ab9540_dbbrstn(struct device *dev,
  879. struct device_attribute *attr, const char *buf, size_t count)
  880. {
  881. struct ab8500 *ab8500;
  882. int ret = count;
  883. int err;
  884. u8 bitvalues;
  885. ab8500 = dev_get_drvdata(dev);
  886. if (count > 0) {
  887. switch (buf[0]) {
  888. case '0':
  889. bitvalues = 0;
  890. break;
  891. case '1':
  892. bitvalues = AB9540_MODEM_CTRL2_SWDBBRSTN_BIT;
  893. break;
  894. default:
  895. goto exit;
  896. }
  897. err = mask_and_set_register_interruptible(ab8500,
  898. AB8500_REGU_CTRL2, AB9540_MODEM_CTRL2_REG,
  899. AB9540_MODEM_CTRL2_SWDBBRSTN_BIT, bitvalues);
  900. if (err)
  901. dev_info(ab8500->dev,
  902. "Failed to set DBBRSTN %c, err %#x\n",
  903. buf[0], err);
  904. }
  905. exit:
  906. return ret;
  907. }
  908. static DEVICE_ATTR(chip_id, S_IRUGO, show_chip_id, NULL);
  909. static DEVICE_ATTR(switch_off_status, S_IRUGO, show_switch_off_status, NULL);
  910. static DEVICE_ATTR(turn_on_status, S_IRUGO, show_turn_on_status, NULL);
  911. static DEVICE_ATTR(turn_on_status_2, S_IRUGO, show_turn_on_status_2, NULL);
  912. static DEVICE_ATTR(dbbrstn, S_IRUGO | S_IWUSR,
  913. show_ab9540_dbbrstn, store_ab9540_dbbrstn);
  914. static struct attribute *ab8500_sysfs_entries[] = {
  915. &dev_attr_chip_id.attr,
  916. &dev_attr_switch_off_status.attr,
  917. &dev_attr_turn_on_status.attr,
  918. NULL,
  919. };
  920. static struct attribute *ab8505_sysfs_entries[] = {
  921. &dev_attr_turn_on_status_2.attr,
  922. NULL,
  923. };
  924. static struct attribute *ab9540_sysfs_entries[] = {
  925. &dev_attr_chip_id.attr,
  926. &dev_attr_switch_off_status.attr,
  927. &dev_attr_turn_on_status.attr,
  928. &dev_attr_dbbrstn.attr,
  929. NULL,
  930. };
  931. static const struct attribute_group ab8500_attr_group = {
  932. .attrs = ab8500_sysfs_entries,
  933. };
  934. static const struct attribute_group ab8505_attr_group = {
  935. .attrs = ab8505_sysfs_entries,
  936. };
  937. static const struct attribute_group ab9540_attr_group = {
  938. .attrs = ab9540_sysfs_entries,
  939. };
  940. static int ab8500_probe(struct platform_device *pdev)
  941. {
  942. static const char * const switch_off_status[] = {
  943. "Swoff bit programming",
  944. "Thermal protection activation",
  945. "Vbat lower then BattOk falling threshold",
  946. "Watchdog expired",
  947. "Non presence of 32kHz clock",
  948. "Battery level lower than power on reset threshold",
  949. "Power on key 1 pressed longer than 10 seconds",
  950. "DB8500 thermal shutdown"};
  951. static const char * const turn_on_status[] = {
  952. "Battery rising (Vbat)",
  953. "Power On Key 1 dbF",
  954. "Power On Key 2 dbF",
  955. "RTC Alarm",
  956. "Main Charger Detect",
  957. "Vbus Detect (USB)",
  958. "USB ID Detect",
  959. "UART Factory Mode Detect"};
  960. const struct platform_device_id *platid = platform_get_device_id(pdev);
  961. enum ab8500_version version = AB8500_VERSION_UNDEFINED;
  962. struct device_node *np = pdev->dev.of_node;
  963. struct ab8500 *ab8500;
  964. struct resource *resource;
  965. int ret;
  966. int i;
  967. u8 value;
  968. ab8500 = devm_kzalloc(&pdev->dev, sizeof(*ab8500), GFP_KERNEL);
  969. if (!ab8500)
  970. return -ENOMEM;
  971. ab8500->dev = &pdev->dev;
  972. resource = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  973. if (!resource) {
  974. dev_err(&pdev->dev, "no IRQ resource\n");
  975. return -ENODEV;
  976. }
  977. ab8500->irq = resource->start;
  978. ab8500->read = ab8500_prcmu_read;
  979. ab8500->write = ab8500_prcmu_write;
  980. ab8500->write_masked = ab8500_prcmu_write_masked;
  981. mutex_init(&ab8500->lock);
  982. mutex_init(&ab8500->irq_lock);
  983. atomic_set(&ab8500->transfer_ongoing, 0);
  984. platform_set_drvdata(pdev, ab8500);
  985. if (platid)
  986. version = platid->driver_data;
  987. if (version != AB8500_VERSION_UNDEFINED)
  988. ab8500->version = version;
  989. else {
  990. ret = get_register_interruptible(ab8500, AB8500_MISC,
  991. AB8500_IC_NAME_REG, &value);
  992. if (ret < 0) {
  993. dev_err(&pdev->dev, "could not probe HW\n");
  994. return ret;
  995. }
  996. ab8500->version = value;
  997. }
  998. ret = get_register_interruptible(ab8500, AB8500_MISC,
  999. AB8500_REV_REG, &value);
  1000. if (ret < 0)
  1001. return ret;
  1002. ab8500->chip_id = value;
  1003. dev_info(ab8500->dev, "detected chip, %s rev. %1x.%1x\n",
  1004. ab8500_version_str[ab8500->version],
  1005. ab8500->chip_id >> 4,
  1006. ab8500->chip_id & 0x0F);
  1007. /* Configure AB8540 */
  1008. if (is_ab8540(ab8500)) {
  1009. ab8500->mask_size = AB8540_NUM_IRQ_REGS;
  1010. ab8500->irq_reg_offset = ab8540_irq_regoffset;
  1011. ab8500->it_latchhier_num = AB8540_IT_LATCHHIER_NUM;
  1012. } /* Configure AB8500 or AB9540 IRQ */
  1013. else if (is_ab9540(ab8500) || is_ab8505(ab8500)) {
  1014. ab8500->mask_size = AB9540_NUM_IRQ_REGS;
  1015. ab8500->irq_reg_offset = ab9540_irq_regoffset;
  1016. ab8500->it_latchhier_num = AB8500_IT_LATCHHIER_NUM;
  1017. } else {
  1018. ab8500->mask_size = AB8500_NUM_IRQ_REGS;
  1019. ab8500->irq_reg_offset = ab8500_irq_regoffset;
  1020. ab8500->it_latchhier_num = AB8500_IT_LATCHHIER_NUM;
  1021. }
  1022. ab8500->mask = devm_kzalloc(&pdev->dev, ab8500->mask_size,
  1023. GFP_KERNEL);
  1024. if (!ab8500->mask)
  1025. return -ENOMEM;
  1026. ab8500->oldmask = devm_kzalloc(&pdev->dev, ab8500->mask_size,
  1027. GFP_KERNEL);
  1028. if (!ab8500->oldmask)
  1029. return -ENOMEM;
  1030. /*
  1031. * ab8500 has switched off due to (SWITCH_OFF_STATUS):
  1032. * 0x01 Swoff bit programming
  1033. * 0x02 Thermal protection activation
  1034. * 0x04 Vbat lower then BattOk falling threshold
  1035. * 0x08 Watchdog expired
  1036. * 0x10 Non presence of 32kHz clock
  1037. * 0x20 Battery level lower than power on reset threshold
  1038. * 0x40 Power on key 1 pressed longer than 10 seconds
  1039. * 0x80 DB8500 thermal shutdown
  1040. */
  1041. ret = get_register_interruptible(ab8500, AB8500_RTC,
  1042. AB8500_SWITCH_OFF_STATUS, &value);
  1043. if (ret < 0)
  1044. return ret;
  1045. dev_info(ab8500->dev, "switch off cause(s) (%#x): ", value);
  1046. if (value) {
  1047. for (i = 0; i < ARRAY_SIZE(switch_off_status); i++) {
  1048. if (value & 1)
  1049. pr_cont(" \"%s\"", switch_off_status[i]);
  1050. value = value >> 1;
  1051. }
  1052. pr_cont("\n");
  1053. } else {
  1054. pr_cont(" None\n");
  1055. }
  1056. ret = get_register_interruptible(ab8500, AB8500_SYS_CTRL1_BLOCK,
  1057. AB8500_TURN_ON_STATUS, &value);
  1058. if (ret < 0)
  1059. return ret;
  1060. dev_info(ab8500->dev, "turn on reason(s) (%#x): ", value);
  1061. if (value) {
  1062. for (i = 0; i < ARRAY_SIZE(turn_on_status); i++) {
  1063. if (value & 1)
  1064. pr_cont("\"%s\" ", turn_on_status[i]);
  1065. value = value >> 1;
  1066. }
  1067. pr_cont("\n");
  1068. } else {
  1069. pr_cont("None\n");
  1070. }
  1071. if (is_ab9540(ab8500)) {
  1072. ret = get_register_interruptible(ab8500, AB8500_CHARGER,
  1073. AB8500_CH_USBCH_STAT1_REG, &value);
  1074. if (ret < 0)
  1075. return ret;
  1076. if ((value & VBUS_DET_DBNC1) && (value & VBUS_DET_DBNC100))
  1077. ab8500_override_turn_on_stat(~AB8500_POW_KEY_1_ON,
  1078. AB8500_VBUS_DET);
  1079. }
  1080. /* Clear and mask all interrupts */
  1081. for (i = 0; i < ab8500->mask_size; i++) {
  1082. /*
  1083. * Interrupt register 12 doesn't exist prior to AB8500 version
  1084. * 2.0
  1085. */
  1086. if (ab8500->irq_reg_offset[i] == 11 &&
  1087. is_ab8500_1p1_or_earlier(ab8500))
  1088. continue;
  1089. if (ab8500->irq_reg_offset[i] < 0)
  1090. continue;
  1091. get_register_interruptible(ab8500, AB8500_INTERRUPT,
  1092. AB8500_IT_LATCH1_REG + ab8500->irq_reg_offset[i],
  1093. &value);
  1094. set_register_interruptible(ab8500, AB8500_INTERRUPT,
  1095. AB8500_IT_MASK1_REG + ab8500->irq_reg_offset[i], 0xff);
  1096. }
  1097. ret = abx500_register_ops(ab8500->dev, &ab8500_ops);
  1098. if (ret)
  1099. return ret;
  1100. for (i = 0; i < ab8500->mask_size; i++)
  1101. ab8500->mask[i] = ab8500->oldmask[i] = 0xff;
  1102. ret = ab8500_irq_init(ab8500, np);
  1103. if (ret)
  1104. return ret;
  1105. ret = devm_request_threaded_irq(&pdev->dev, ab8500->irq, NULL,
  1106. ab8500_hierarchical_irq,
  1107. IRQF_ONESHOT | IRQF_NO_SUSPEND,
  1108. "ab8500", ab8500);
  1109. if (ret)
  1110. return ret;
  1111. if (is_ab9540(ab8500))
  1112. ret = mfd_add_devices(ab8500->dev, 0, ab9540_devs,
  1113. ARRAY_SIZE(ab9540_devs), NULL,
  1114. 0, ab8500->domain);
  1115. else if (is_ab8540(ab8500)) {
  1116. ret = mfd_add_devices(ab8500->dev, 0, ab8540_devs,
  1117. ARRAY_SIZE(ab8540_devs), NULL,
  1118. 0, ab8500->domain);
  1119. if (ret)
  1120. return ret;
  1121. if (is_ab8540_1p2_or_earlier(ab8500))
  1122. ret = mfd_add_devices(ab8500->dev, 0, ab8540_cut1_devs,
  1123. ARRAY_SIZE(ab8540_cut1_devs), NULL,
  1124. 0, ab8500->domain);
  1125. else /* ab8540 >= cut2 */
  1126. ret = mfd_add_devices(ab8500->dev, 0, ab8540_cut2_devs,
  1127. ARRAY_SIZE(ab8540_cut2_devs), NULL,
  1128. 0, ab8500->domain);
  1129. } else if (is_ab8505(ab8500))
  1130. ret = mfd_add_devices(ab8500->dev, 0, ab8505_devs,
  1131. ARRAY_SIZE(ab8505_devs), NULL,
  1132. 0, ab8500->domain);
  1133. else
  1134. ret = mfd_add_devices(ab8500->dev, 0, ab8500_devs,
  1135. ARRAY_SIZE(ab8500_devs), NULL,
  1136. 0, ab8500->domain);
  1137. if (ret)
  1138. return ret;
  1139. if (!no_bm) {
  1140. /* Add battery management devices */
  1141. ret = mfd_add_devices(ab8500->dev, 0, ab8500_bm_devs,
  1142. ARRAY_SIZE(ab8500_bm_devs), NULL,
  1143. 0, ab8500->domain);
  1144. if (ret)
  1145. dev_err(ab8500->dev, "error adding bm devices\n");
  1146. }
  1147. if (((is_ab8505(ab8500) || is_ab9540(ab8500)) &&
  1148. ab8500->chip_id >= AB8500_CUT2P0) || is_ab8540(ab8500))
  1149. ret = sysfs_create_group(&ab8500->dev->kobj,
  1150. &ab9540_attr_group);
  1151. else
  1152. ret = sysfs_create_group(&ab8500->dev->kobj,
  1153. &ab8500_attr_group);
  1154. if ((is_ab8505(ab8500) || is_ab9540(ab8500)) &&
  1155. ab8500->chip_id >= AB8500_CUT2P0)
  1156. ret = sysfs_create_group(&ab8500->dev->kobj,
  1157. &ab8505_attr_group);
  1158. if (ret)
  1159. dev_err(ab8500->dev, "error creating sysfs entries\n");
  1160. return ret;
  1161. }
  1162. static const struct platform_device_id ab8500_id[] = {
  1163. { "ab8500-core", AB8500_VERSION_AB8500 },
  1164. { "ab8505-i2c", AB8500_VERSION_AB8505 },
  1165. { "ab9540-i2c", AB8500_VERSION_AB9540 },
  1166. { "ab8540-i2c", AB8500_VERSION_AB8540 },
  1167. { }
  1168. };
  1169. static struct platform_driver ab8500_core_driver = {
  1170. .driver = {
  1171. .name = "ab8500-core",
  1172. .suppress_bind_attrs = true,
  1173. },
  1174. .probe = ab8500_probe,
  1175. .id_table = ab8500_id,
  1176. };
  1177. static int __init ab8500_core_init(void)
  1178. {
  1179. return platform_driver_register(&ab8500_core_driver);
  1180. }
  1181. core_initcall(ab8500_core_init);