dm1105.c 29 KB

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  1. /*
  2. * dm1105.c - driver for DVB cards based on SDMC DM1105 PCI chip
  3. *
  4. * Copyright (C) 2008 Igor M. Liplianin <liplianin@me.by>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. */
  17. #include <linux/i2c.h>
  18. #include <linux/i2c-algo-bit.h>
  19. #include <linux/init.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/kernel.h>
  22. #include <linux/module.h>
  23. #include <linux/proc_fs.h>
  24. #include <linux/pci.h>
  25. #include <linux/dma-mapping.h>
  26. #include <linux/slab.h>
  27. #include <media/rc-core.h>
  28. #include <media/demux.h>
  29. #include <media/dmxdev.h>
  30. #include <media/dvb_demux.h>
  31. #include <media/dvb_frontend.h>
  32. #include <media/dvb_net.h>
  33. #include <media/dvbdev.h>
  34. #include "dvb-pll.h"
  35. #include "stv0299.h"
  36. #include "stv0288.h"
  37. #include "stb6000.h"
  38. #include "si21xx.h"
  39. #include "cx24116.h"
  40. #include "z0194a.h"
  41. #include "ts2020.h"
  42. #include "ds3000.h"
  43. #define MODULE_NAME "dm1105"
  44. #define UNSET (-1U)
  45. #define DM1105_BOARD_NOAUTO UNSET
  46. #define DM1105_BOARD_UNKNOWN 0
  47. #define DM1105_BOARD_DVBWORLD_2002 1
  48. #define DM1105_BOARD_DVBWORLD_2004 2
  49. #define DM1105_BOARD_AXESS_DM05 3
  50. #define DM1105_BOARD_UNBRANDED_I2C_ON_GPIO 4
  51. /* ----------------------------------------------- */
  52. /*
  53. * PCI ID's
  54. */
  55. #ifndef PCI_VENDOR_ID_TRIGEM
  56. #define PCI_VENDOR_ID_TRIGEM 0x109f
  57. #endif
  58. #ifndef PCI_VENDOR_ID_AXESS
  59. #define PCI_VENDOR_ID_AXESS 0x195d
  60. #endif
  61. #ifndef PCI_DEVICE_ID_DM1105
  62. #define PCI_DEVICE_ID_DM1105 0x036f
  63. #endif
  64. #ifndef PCI_DEVICE_ID_DW2002
  65. #define PCI_DEVICE_ID_DW2002 0x2002
  66. #endif
  67. #ifndef PCI_DEVICE_ID_DW2004
  68. #define PCI_DEVICE_ID_DW2004 0x2004
  69. #endif
  70. #ifndef PCI_DEVICE_ID_DM05
  71. #define PCI_DEVICE_ID_DM05 0x1105
  72. #endif
  73. /* ----------------------------------------------- */
  74. /* sdmc dm1105 registers */
  75. /* TS Control */
  76. #define DM1105_TSCTR 0x00
  77. #define DM1105_DTALENTH 0x04
  78. /* GPIO Interface */
  79. #define DM1105_GPIOVAL 0x08
  80. #define DM1105_GPIOCTR 0x0c
  81. /* PID serial number */
  82. #define DM1105_PIDN 0x10
  83. /* Odd-even secret key select */
  84. #define DM1105_CWSEL 0x14
  85. /* Host Command Interface */
  86. #define DM1105_HOST_CTR 0x18
  87. #define DM1105_HOST_AD 0x1c
  88. /* PCI Interface */
  89. #define DM1105_CR 0x30
  90. #define DM1105_RST 0x34
  91. #define DM1105_STADR 0x38
  92. #define DM1105_RLEN 0x3c
  93. #define DM1105_WRP 0x40
  94. #define DM1105_INTCNT 0x44
  95. #define DM1105_INTMAK 0x48
  96. #define DM1105_INTSTS 0x4c
  97. /* CW Value */
  98. #define DM1105_ODD 0x50
  99. #define DM1105_EVEN 0x58
  100. /* PID Value */
  101. #define DM1105_PID 0x60
  102. /* IR Control */
  103. #define DM1105_IRCTR 0x64
  104. #define DM1105_IRMODE 0x68
  105. #define DM1105_SYSTEMCODE 0x6c
  106. #define DM1105_IRCODE 0x70
  107. /* Unknown Values */
  108. #define DM1105_ENCRYPT 0x74
  109. #define DM1105_VER 0x7c
  110. /* I2C Interface */
  111. #define DM1105_I2CCTR 0x80
  112. #define DM1105_I2CSTS 0x81
  113. #define DM1105_I2CDAT 0x82
  114. #define DM1105_I2C_RA 0x83
  115. /* ----------------------------------------------- */
  116. /* Interrupt Mask Bits */
  117. #define INTMAK_TSIRQM 0x01
  118. #define INTMAK_HIRQM 0x04
  119. #define INTMAK_IRM 0x08
  120. #define INTMAK_ALLMASK (INTMAK_TSIRQM | \
  121. INTMAK_HIRQM | \
  122. INTMAK_IRM)
  123. #define INTMAK_NONEMASK 0x00
  124. /* Interrupt Status Bits */
  125. #define INTSTS_TSIRQ 0x01
  126. #define INTSTS_HIRQ 0x04
  127. #define INTSTS_IR 0x08
  128. /* IR Control Bits */
  129. #define DM1105_IR_EN 0x01
  130. #define DM1105_SYS_CHK 0x02
  131. #define DM1105_REP_FLG 0x08
  132. /* EEPROM addr */
  133. #define IIC_24C01_addr 0xa0
  134. /* Max board count */
  135. #define DM1105_MAX 0x04
  136. #define DRIVER_NAME "dm1105"
  137. #define DM1105_I2C_GPIO_NAME "dm1105-gpio"
  138. #define DM1105_DMA_PACKETS 47
  139. #define DM1105_DMA_PACKET_LENGTH (128*4)
  140. #define DM1105_DMA_BYTES (128 * 4 * DM1105_DMA_PACKETS)
  141. /* */
  142. #define GPIO08 (1 << 8)
  143. #define GPIO13 (1 << 13)
  144. #define GPIO14 (1 << 14)
  145. #define GPIO15 (1 << 15)
  146. #define GPIO16 (1 << 16)
  147. #define GPIO17 (1 << 17)
  148. #define GPIO_ALL 0x03ffff
  149. /* GPIO's for LNB power control */
  150. #define DM1105_LNB_MASK (GPIO_ALL & ~(GPIO14 | GPIO13))
  151. #define DM1105_LNB_OFF GPIO17
  152. #define DM1105_LNB_13V (GPIO16 | GPIO08)
  153. #define DM1105_LNB_18V GPIO08
  154. /* GPIO's for LNB power control for Axess DM05 */
  155. #define DM05_LNB_MASK (GPIO_ALL & ~(GPIO14 | GPIO13))
  156. #define DM05_LNB_OFF GPIO17/* actually 13v */
  157. #define DM05_LNB_13V GPIO17
  158. #define DM05_LNB_18V (GPIO17 | GPIO16)
  159. /* GPIO's for LNB power control for unbranded with I2C on GPIO */
  160. #define UNBR_LNB_MASK (GPIO17 | GPIO16)
  161. #define UNBR_LNB_OFF 0
  162. #define UNBR_LNB_13V GPIO17
  163. #define UNBR_LNB_18V (GPIO17 | GPIO16)
  164. static unsigned int card[] = {[0 ... 3] = UNSET };
  165. module_param_array(card, int, NULL, 0444);
  166. MODULE_PARM_DESC(card, "card type");
  167. static int ir_debug;
  168. module_param(ir_debug, int, 0644);
  169. MODULE_PARM_DESC(ir_debug, "enable debugging information for IR decoding");
  170. static unsigned int dm1105_devcount;
  171. DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  172. struct dm1105_board {
  173. char *name;
  174. struct {
  175. u32 mask, off, v13, v18;
  176. } lnb;
  177. u32 gpio_scl, gpio_sda;
  178. };
  179. struct dm1105_subid {
  180. u16 subvendor;
  181. u16 subdevice;
  182. u32 card;
  183. };
  184. static const struct dm1105_board dm1105_boards[] = {
  185. [DM1105_BOARD_UNKNOWN] = {
  186. .name = "UNKNOWN/GENERIC",
  187. .lnb = {
  188. .mask = DM1105_LNB_MASK,
  189. .off = DM1105_LNB_OFF,
  190. .v13 = DM1105_LNB_13V,
  191. .v18 = DM1105_LNB_18V,
  192. },
  193. },
  194. [DM1105_BOARD_DVBWORLD_2002] = {
  195. .name = "DVBWorld PCI 2002",
  196. .lnb = {
  197. .mask = DM1105_LNB_MASK,
  198. .off = DM1105_LNB_OFF,
  199. .v13 = DM1105_LNB_13V,
  200. .v18 = DM1105_LNB_18V,
  201. },
  202. },
  203. [DM1105_BOARD_DVBWORLD_2004] = {
  204. .name = "DVBWorld PCI 2004",
  205. .lnb = {
  206. .mask = DM1105_LNB_MASK,
  207. .off = DM1105_LNB_OFF,
  208. .v13 = DM1105_LNB_13V,
  209. .v18 = DM1105_LNB_18V,
  210. },
  211. },
  212. [DM1105_BOARD_AXESS_DM05] = {
  213. .name = "Axess/EasyTv DM05",
  214. .lnb = {
  215. .mask = DM05_LNB_MASK,
  216. .off = DM05_LNB_OFF,
  217. .v13 = DM05_LNB_13V,
  218. .v18 = DM05_LNB_18V,
  219. },
  220. },
  221. [DM1105_BOARD_UNBRANDED_I2C_ON_GPIO] = {
  222. .name = "Unbranded DM1105 with i2c on GPIOs",
  223. .lnb = {
  224. .mask = UNBR_LNB_MASK,
  225. .off = UNBR_LNB_OFF,
  226. .v13 = UNBR_LNB_13V,
  227. .v18 = UNBR_LNB_18V,
  228. },
  229. .gpio_scl = GPIO14,
  230. .gpio_sda = GPIO13,
  231. },
  232. };
  233. static const struct dm1105_subid dm1105_subids[] = {
  234. {
  235. .subvendor = 0x0000,
  236. .subdevice = 0x2002,
  237. .card = DM1105_BOARD_DVBWORLD_2002,
  238. }, {
  239. .subvendor = 0x0001,
  240. .subdevice = 0x2002,
  241. .card = DM1105_BOARD_DVBWORLD_2002,
  242. }, {
  243. .subvendor = 0x0000,
  244. .subdevice = 0x2004,
  245. .card = DM1105_BOARD_DVBWORLD_2004,
  246. }, {
  247. .subvendor = 0x0001,
  248. .subdevice = 0x2004,
  249. .card = DM1105_BOARD_DVBWORLD_2004,
  250. }, {
  251. .subvendor = 0x195d,
  252. .subdevice = 0x1105,
  253. .card = DM1105_BOARD_AXESS_DM05,
  254. },
  255. };
  256. static void dm1105_card_list(struct pci_dev *pci)
  257. {
  258. int i;
  259. if (0 == pci->subsystem_vendor &&
  260. 0 == pci->subsystem_device) {
  261. printk(KERN_ERR
  262. "dm1105: Your board has no valid PCI Subsystem ID\n"
  263. "dm1105: and thus can't be autodetected\n"
  264. "dm1105: Please pass card=<n> insmod option to\n"
  265. "dm1105: workaround that. Redirect complaints to\n"
  266. "dm1105: the vendor of the TV card. Best regards,\n"
  267. "dm1105: -- tux\n");
  268. } else {
  269. printk(KERN_ERR
  270. "dm1105: Your board isn't known (yet) to the driver.\n"
  271. "dm1105: You can try to pick one of the existing\n"
  272. "dm1105: card configs via card=<n> insmod option.\n"
  273. "dm1105: Updating to the latest version might help\n"
  274. "dm1105: as well.\n");
  275. }
  276. printk(KERN_ERR "Here is a list of valid choices for the card=<n> insmod option:\n");
  277. for (i = 0; i < ARRAY_SIZE(dm1105_boards); i++)
  278. printk(KERN_ERR "dm1105: card=%d -> %s\n",
  279. i, dm1105_boards[i].name);
  280. }
  281. /* infrared remote control */
  282. struct infrared {
  283. struct rc_dev *dev;
  284. char input_phys[32];
  285. struct work_struct work;
  286. u32 ir_command;
  287. };
  288. struct dm1105_dev {
  289. /* pci */
  290. struct pci_dev *pdev;
  291. u8 __iomem *io_mem;
  292. /* ir */
  293. struct infrared ir;
  294. /* dvb */
  295. struct dmx_frontend hw_frontend;
  296. struct dmx_frontend mem_frontend;
  297. struct dmxdev dmxdev;
  298. struct dvb_adapter dvb_adapter;
  299. struct dvb_demux demux;
  300. struct dvb_frontend *fe;
  301. struct dvb_net dvbnet;
  302. unsigned int full_ts_users;
  303. unsigned int boardnr;
  304. int nr;
  305. /* i2c */
  306. struct i2c_adapter i2c_adap;
  307. struct i2c_adapter i2c_bb_adap;
  308. struct i2c_algo_bit_data i2c_bit;
  309. /* irq */
  310. struct work_struct work;
  311. struct workqueue_struct *wq;
  312. char wqn[16];
  313. /* dma */
  314. dma_addr_t dma_addr;
  315. unsigned char *ts_buf;
  316. u32 wrp;
  317. u32 nextwrp;
  318. u32 buffer_size;
  319. unsigned int PacketErrorCount;
  320. unsigned int dmarst;
  321. spinlock_t lock;
  322. };
  323. #define dm_io_mem(reg) ((unsigned long)(&dev->io_mem[reg]))
  324. #define dm_readb(reg) inb(dm_io_mem(reg))
  325. #define dm_writeb(reg, value) outb((value), (dm_io_mem(reg)))
  326. #define dm_readw(reg) inw(dm_io_mem(reg))
  327. #define dm_writew(reg, value) outw((value), (dm_io_mem(reg)))
  328. #define dm_readl(reg) inl(dm_io_mem(reg))
  329. #define dm_writel(reg, value) outl((value), (dm_io_mem(reg)))
  330. #define dm_andorl(reg, mask, value) \
  331. outl((inl(dm_io_mem(reg)) & ~(mask)) |\
  332. ((value) & (mask)), (dm_io_mem(reg)))
  333. #define dm_setl(reg, bit) dm_andorl((reg), (bit), (bit))
  334. #define dm_clearl(reg, bit) dm_andorl((reg), (bit), 0)
  335. /* The chip has 18 GPIOs. In HOST mode GPIO's used as 15 bit address lines,
  336. so we can use only 3 GPIO's from GPIO15 to GPIO17.
  337. Here I don't check whether HOST is enebled as it is not implemented yet.
  338. */
  339. static void dm1105_gpio_set(struct dm1105_dev *dev, u32 mask)
  340. {
  341. if (mask & 0xfffc0000)
  342. printk(KERN_ERR "%s: Only 18 GPIO's are allowed\n", __func__);
  343. if (mask & 0x0003ffff)
  344. dm_setl(DM1105_GPIOVAL, mask & 0x0003ffff);
  345. }
  346. static void dm1105_gpio_clear(struct dm1105_dev *dev, u32 mask)
  347. {
  348. if (mask & 0xfffc0000)
  349. printk(KERN_ERR "%s: Only 18 GPIO's are allowed\n", __func__);
  350. if (mask & 0x0003ffff)
  351. dm_clearl(DM1105_GPIOVAL, mask & 0x0003ffff);
  352. }
  353. static void dm1105_gpio_andor(struct dm1105_dev *dev, u32 mask, u32 val)
  354. {
  355. if (mask & 0xfffc0000)
  356. printk(KERN_ERR "%s: Only 18 GPIO's are allowed\n", __func__);
  357. if (mask & 0x0003ffff)
  358. dm_andorl(DM1105_GPIOVAL, mask & 0x0003ffff, val);
  359. }
  360. static u32 dm1105_gpio_get(struct dm1105_dev *dev, u32 mask)
  361. {
  362. if (mask & 0xfffc0000)
  363. printk(KERN_ERR "%s: Only 18 GPIO's are allowed\n", __func__);
  364. if (mask & 0x0003ffff)
  365. return dm_readl(DM1105_GPIOVAL) & mask & 0x0003ffff;
  366. return 0;
  367. }
  368. static void dm1105_gpio_enable(struct dm1105_dev *dev, u32 mask, int asoutput)
  369. {
  370. if (mask & 0xfffc0000)
  371. printk(KERN_ERR "%s: Only 18 GPIO's are allowed\n", __func__);
  372. if ((mask & 0x0003ffff) && asoutput)
  373. dm_clearl(DM1105_GPIOCTR, mask & 0x0003ffff);
  374. else if ((mask & 0x0003ffff) && !asoutput)
  375. dm_setl(DM1105_GPIOCTR, mask & 0x0003ffff);
  376. }
  377. static void dm1105_setline(struct dm1105_dev *dev, u32 line, int state)
  378. {
  379. if (state)
  380. dm1105_gpio_enable(dev, line, 0);
  381. else {
  382. dm1105_gpio_enable(dev, line, 1);
  383. dm1105_gpio_clear(dev, line);
  384. }
  385. }
  386. static void dm1105_setsda(void *data, int state)
  387. {
  388. struct dm1105_dev *dev = data;
  389. dm1105_setline(dev, dm1105_boards[dev->boardnr].gpio_sda, state);
  390. }
  391. static void dm1105_setscl(void *data, int state)
  392. {
  393. struct dm1105_dev *dev = data;
  394. dm1105_setline(dev, dm1105_boards[dev->boardnr].gpio_scl, state);
  395. }
  396. static int dm1105_getsda(void *data)
  397. {
  398. struct dm1105_dev *dev = data;
  399. return dm1105_gpio_get(dev, dm1105_boards[dev->boardnr].gpio_sda)
  400. ? 1 : 0;
  401. }
  402. static int dm1105_getscl(void *data)
  403. {
  404. struct dm1105_dev *dev = data;
  405. return dm1105_gpio_get(dev, dm1105_boards[dev->boardnr].gpio_scl)
  406. ? 1 : 0;
  407. }
  408. static int dm1105_i2c_xfer(struct i2c_adapter *i2c_adap,
  409. struct i2c_msg *msgs, int num)
  410. {
  411. struct dm1105_dev *dev ;
  412. int addr, rc, i, j, k, len, byte, data;
  413. u8 status;
  414. dev = i2c_adap->algo_data;
  415. for (i = 0; i < num; i++) {
  416. dm_writeb(DM1105_I2CCTR, 0x00);
  417. if (msgs[i].flags & I2C_M_RD) {
  418. /* read bytes */
  419. addr = msgs[i].addr << 1;
  420. addr |= 1;
  421. dm_writeb(DM1105_I2CDAT, addr);
  422. for (byte = 0; byte < msgs[i].len; byte++)
  423. dm_writeb(DM1105_I2CDAT + byte + 1, 0);
  424. dm_writeb(DM1105_I2CCTR, 0x81 + msgs[i].len);
  425. for (j = 0; j < 55; j++) {
  426. mdelay(10);
  427. status = dm_readb(DM1105_I2CSTS);
  428. if ((status & 0xc0) == 0x40)
  429. break;
  430. }
  431. if (j >= 55)
  432. return -1;
  433. for (byte = 0; byte < msgs[i].len; byte++) {
  434. rc = dm_readb(DM1105_I2CDAT + byte + 1);
  435. if (rc < 0)
  436. goto err;
  437. msgs[i].buf[byte] = rc;
  438. }
  439. } else if ((msgs[i].buf[0] == 0xf7) && (msgs[i].addr == 0x55)) {
  440. /* prepaired for cx24116 firmware */
  441. /* Write in small blocks */
  442. len = msgs[i].len - 1;
  443. k = 1;
  444. do {
  445. dm_writeb(DM1105_I2CDAT, msgs[i].addr << 1);
  446. dm_writeb(DM1105_I2CDAT + 1, 0xf7);
  447. for (byte = 0; byte < (len > 48 ? 48 : len); byte++) {
  448. data = msgs[i].buf[k + byte];
  449. dm_writeb(DM1105_I2CDAT + byte + 2, data);
  450. }
  451. dm_writeb(DM1105_I2CCTR, 0x82 + (len > 48 ? 48 : len));
  452. for (j = 0; j < 25; j++) {
  453. mdelay(10);
  454. status = dm_readb(DM1105_I2CSTS);
  455. if ((status & 0xc0) == 0x40)
  456. break;
  457. }
  458. if (j >= 25)
  459. return -1;
  460. k += 48;
  461. len -= 48;
  462. } while (len > 0);
  463. } else {
  464. /* write bytes */
  465. dm_writeb(DM1105_I2CDAT, msgs[i].addr << 1);
  466. for (byte = 0; byte < msgs[i].len; byte++) {
  467. data = msgs[i].buf[byte];
  468. dm_writeb(DM1105_I2CDAT + byte + 1, data);
  469. }
  470. dm_writeb(DM1105_I2CCTR, 0x81 + msgs[i].len);
  471. for (j = 0; j < 25; j++) {
  472. mdelay(10);
  473. status = dm_readb(DM1105_I2CSTS);
  474. if ((status & 0xc0) == 0x40)
  475. break;
  476. }
  477. if (j >= 25)
  478. return -1;
  479. }
  480. }
  481. return num;
  482. err:
  483. return rc;
  484. }
  485. static u32 functionality(struct i2c_adapter *adap)
  486. {
  487. return I2C_FUNC_I2C;
  488. }
  489. static const struct i2c_algorithm dm1105_algo = {
  490. .master_xfer = dm1105_i2c_xfer,
  491. .functionality = functionality,
  492. };
  493. static inline struct dm1105_dev *feed_to_dm1105_dev(struct dvb_demux_feed *feed)
  494. {
  495. return container_of(feed->demux, struct dm1105_dev, demux);
  496. }
  497. static inline struct dm1105_dev *frontend_to_dm1105_dev(struct dvb_frontend *fe)
  498. {
  499. return container_of(fe->dvb, struct dm1105_dev, dvb_adapter);
  500. }
  501. static int dm1105_set_voltage(struct dvb_frontend *fe,
  502. enum fe_sec_voltage voltage)
  503. {
  504. struct dm1105_dev *dev = frontend_to_dm1105_dev(fe);
  505. dm1105_gpio_enable(dev, dm1105_boards[dev->boardnr].lnb.mask, 1);
  506. if (voltage == SEC_VOLTAGE_18)
  507. dm1105_gpio_andor(dev,
  508. dm1105_boards[dev->boardnr].lnb.mask,
  509. dm1105_boards[dev->boardnr].lnb.v18);
  510. else if (voltage == SEC_VOLTAGE_13)
  511. dm1105_gpio_andor(dev,
  512. dm1105_boards[dev->boardnr].lnb.mask,
  513. dm1105_boards[dev->boardnr].lnb.v13);
  514. else
  515. dm1105_gpio_andor(dev,
  516. dm1105_boards[dev->boardnr].lnb.mask,
  517. dm1105_boards[dev->boardnr].lnb.off);
  518. return 0;
  519. }
  520. static void dm1105_set_dma_addr(struct dm1105_dev *dev)
  521. {
  522. dm_writel(DM1105_STADR, (__force u32)cpu_to_le32(dev->dma_addr));
  523. }
  524. static int dm1105_dma_map(struct dm1105_dev *dev)
  525. {
  526. dev->ts_buf = pci_alloc_consistent(dev->pdev,
  527. 6 * DM1105_DMA_BYTES,
  528. &dev->dma_addr);
  529. return !dev->ts_buf;
  530. }
  531. static void dm1105_dma_unmap(struct dm1105_dev *dev)
  532. {
  533. pci_free_consistent(dev->pdev,
  534. 6 * DM1105_DMA_BYTES,
  535. dev->ts_buf,
  536. dev->dma_addr);
  537. }
  538. static void dm1105_enable_irqs(struct dm1105_dev *dev)
  539. {
  540. dm_writeb(DM1105_INTMAK, INTMAK_ALLMASK);
  541. dm_writeb(DM1105_CR, 1);
  542. }
  543. static void dm1105_disable_irqs(struct dm1105_dev *dev)
  544. {
  545. dm_writeb(DM1105_INTMAK, INTMAK_IRM);
  546. dm_writeb(DM1105_CR, 0);
  547. }
  548. static int dm1105_start_feed(struct dvb_demux_feed *f)
  549. {
  550. struct dm1105_dev *dev = feed_to_dm1105_dev(f);
  551. if (dev->full_ts_users++ == 0)
  552. dm1105_enable_irqs(dev);
  553. return 0;
  554. }
  555. static int dm1105_stop_feed(struct dvb_demux_feed *f)
  556. {
  557. struct dm1105_dev *dev = feed_to_dm1105_dev(f);
  558. if (--dev->full_ts_users == 0)
  559. dm1105_disable_irqs(dev);
  560. return 0;
  561. }
  562. /* ir work handler */
  563. static void dm1105_emit_key(struct work_struct *work)
  564. {
  565. struct infrared *ir = container_of(work, struct infrared, work);
  566. u32 ircom = ir->ir_command;
  567. u8 data;
  568. if (ir_debug)
  569. printk(KERN_INFO "%s: received byte 0x%04x\n", __func__, ircom);
  570. data = (ircom >> 8) & 0x7f;
  571. /* FIXME: UNKNOWN because we don't generate a full NEC scancode (yet?) */
  572. rc_keydown(ir->dev, RC_PROTO_UNKNOWN, data, 0);
  573. }
  574. /* work handler */
  575. static void dm1105_dmx_buffer(struct work_struct *work)
  576. {
  577. struct dm1105_dev *dev = container_of(work, struct dm1105_dev, work);
  578. unsigned int nbpackets;
  579. u32 oldwrp = dev->wrp;
  580. u32 nextwrp = dev->nextwrp;
  581. if (!((dev->ts_buf[oldwrp] == 0x47) &&
  582. (dev->ts_buf[oldwrp + 188] == 0x47) &&
  583. (dev->ts_buf[oldwrp + 188 * 2] == 0x47))) {
  584. dev->PacketErrorCount++;
  585. /* bad packet found */
  586. if ((dev->PacketErrorCount >= 2) &&
  587. (dev->dmarst == 0)) {
  588. dm_writeb(DM1105_RST, 1);
  589. dev->wrp = 0;
  590. dev->PacketErrorCount = 0;
  591. dev->dmarst = 0;
  592. return;
  593. }
  594. }
  595. if (nextwrp < oldwrp) {
  596. memcpy(dev->ts_buf + dev->buffer_size, dev->ts_buf, nextwrp);
  597. nbpackets = ((dev->buffer_size - oldwrp) + nextwrp) / 188;
  598. } else
  599. nbpackets = (nextwrp - oldwrp) / 188;
  600. dev->wrp = nextwrp;
  601. dvb_dmx_swfilter_packets(&dev->demux, &dev->ts_buf[oldwrp], nbpackets);
  602. }
  603. static irqreturn_t dm1105_irq(int irq, void *dev_id)
  604. {
  605. struct dm1105_dev *dev = dev_id;
  606. /* Read-Write INSTS Ack's Interrupt for DM1105 chip 16.03.2008 */
  607. unsigned int intsts = dm_readb(DM1105_INTSTS);
  608. dm_writeb(DM1105_INTSTS, intsts);
  609. switch (intsts) {
  610. case INTSTS_TSIRQ:
  611. case (INTSTS_TSIRQ | INTSTS_IR):
  612. dev->nextwrp = dm_readl(DM1105_WRP) - dm_readl(DM1105_STADR);
  613. queue_work(dev->wq, &dev->work);
  614. break;
  615. case INTSTS_IR:
  616. dev->ir.ir_command = dm_readl(DM1105_IRCODE);
  617. schedule_work(&dev->ir.work);
  618. break;
  619. }
  620. return IRQ_HANDLED;
  621. }
  622. static int dm1105_ir_init(struct dm1105_dev *dm1105)
  623. {
  624. struct rc_dev *dev;
  625. int err = -ENOMEM;
  626. dev = rc_allocate_device(RC_DRIVER_SCANCODE);
  627. if (!dev)
  628. return -ENOMEM;
  629. snprintf(dm1105->ir.input_phys, sizeof(dm1105->ir.input_phys),
  630. "pci-%s/ir0", pci_name(dm1105->pdev));
  631. dev->driver_name = MODULE_NAME;
  632. dev->map_name = RC_MAP_DM1105_NEC;
  633. dev->device_name = "DVB on-card IR receiver";
  634. dev->input_phys = dm1105->ir.input_phys;
  635. dev->input_id.bustype = BUS_PCI;
  636. dev->input_id.version = 1;
  637. if (dm1105->pdev->subsystem_vendor) {
  638. dev->input_id.vendor = dm1105->pdev->subsystem_vendor;
  639. dev->input_id.product = dm1105->pdev->subsystem_device;
  640. } else {
  641. dev->input_id.vendor = dm1105->pdev->vendor;
  642. dev->input_id.product = dm1105->pdev->device;
  643. }
  644. dev->dev.parent = &dm1105->pdev->dev;
  645. INIT_WORK(&dm1105->ir.work, dm1105_emit_key);
  646. err = rc_register_device(dev);
  647. if (err < 0) {
  648. rc_free_device(dev);
  649. return err;
  650. }
  651. dm1105->ir.dev = dev;
  652. return 0;
  653. }
  654. static void dm1105_ir_exit(struct dm1105_dev *dm1105)
  655. {
  656. rc_unregister_device(dm1105->ir.dev);
  657. }
  658. static int dm1105_hw_init(struct dm1105_dev *dev)
  659. {
  660. dm1105_disable_irqs(dev);
  661. dm_writeb(DM1105_HOST_CTR, 0);
  662. /*DATALEN 188,*/
  663. dm_writeb(DM1105_DTALENTH, 188);
  664. /*TS_STRT TS_VALP MSBFIRST TS_MODE ALPAS TSPES*/
  665. dm_writew(DM1105_TSCTR, 0xc10a);
  666. /* map DMA and set address */
  667. dm1105_dma_map(dev);
  668. dm1105_set_dma_addr(dev);
  669. /* big buffer */
  670. dm_writel(DM1105_RLEN, 5 * DM1105_DMA_BYTES);
  671. dm_writeb(DM1105_INTCNT, 47);
  672. /* IR NEC mode enable */
  673. dm_writeb(DM1105_IRCTR, (DM1105_IR_EN | DM1105_SYS_CHK));
  674. dm_writeb(DM1105_IRMODE, 0);
  675. dm_writew(DM1105_SYSTEMCODE, 0);
  676. return 0;
  677. }
  678. static void dm1105_hw_exit(struct dm1105_dev *dev)
  679. {
  680. dm1105_disable_irqs(dev);
  681. /* IR disable */
  682. dm_writeb(DM1105_IRCTR, 0);
  683. dm_writeb(DM1105_INTMAK, INTMAK_NONEMASK);
  684. dm1105_dma_unmap(dev);
  685. }
  686. static const struct stv0299_config sharp_z0194a_config = {
  687. .demod_address = 0x68,
  688. .inittab = sharp_z0194a_inittab,
  689. .mclk = 88000000UL,
  690. .invert = 1,
  691. .skip_reinit = 0,
  692. .lock_output = STV0299_LOCKOUTPUT_1,
  693. .volt13_op0_op1 = STV0299_VOLT13_OP1,
  694. .min_delay_ms = 100,
  695. .set_symbol_rate = sharp_z0194a_set_symbol_rate,
  696. };
  697. static struct stv0288_config earda_config = {
  698. .demod_address = 0x68,
  699. .min_delay_ms = 100,
  700. };
  701. static struct si21xx_config serit_config = {
  702. .demod_address = 0x68,
  703. .min_delay_ms = 100,
  704. };
  705. static struct cx24116_config serit_sp2633_config = {
  706. .demod_address = 0x55,
  707. };
  708. static struct ds3000_config dvbworld_ds3000_config = {
  709. .demod_address = 0x68,
  710. };
  711. static struct ts2020_config dvbworld_ts2020_config = {
  712. .tuner_address = 0x60,
  713. .clk_out_div = 1,
  714. };
  715. static int frontend_init(struct dm1105_dev *dev)
  716. {
  717. int ret;
  718. switch (dev->boardnr) {
  719. case DM1105_BOARD_UNBRANDED_I2C_ON_GPIO:
  720. dm1105_gpio_enable(dev, GPIO15, 1);
  721. dm1105_gpio_clear(dev, GPIO15);
  722. msleep(100);
  723. dm1105_gpio_set(dev, GPIO15);
  724. msleep(200);
  725. dev->fe = dvb_attach(
  726. stv0299_attach, &sharp_z0194a_config,
  727. &dev->i2c_bb_adap);
  728. if (dev->fe) {
  729. dev->fe->ops.set_voltage = dm1105_set_voltage;
  730. dvb_attach(dvb_pll_attach, dev->fe, 0x60,
  731. &dev->i2c_bb_adap, DVB_PLL_OPERA1);
  732. break;
  733. }
  734. dev->fe = dvb_attach(
  735. stv0288_attach, &earda_config,
  736. &dev->i2c_bb_adap);
  737. if (dev->fe) {
  738. dev->fe->ops.set_voltage = dm1105_set_voltage;
  739. dvb_attach(stb6000_attach, dev->fe, 0x61,
  740. &dev->i2c_bb_adap);
  741. break;
  742. }
  743. dev->fe = dvb_attach(
  744. si21xx_attach, &serit_config,
  745. &dev->i2c_bb_adap);
  746. if (dev->fe)
  747. dev->fe->ops.set_voltage = dm1105_set_voltage;
  748. break;
  749. case DM1105_BOARD_DVBWORLD_2004:
  750. dev->fe = dvb_attach(
  751. cx24116_attach, &serit_sp2633_config,
  752. &dev->i2c_adap);
  753. if (dev->fe) {
  754. dev->fe->ops.set_voltage = dm1105_set_voltage;
  755. break;
  756. }
  757. dev->fe = dvb_attach(
  758. ds3000_attach, &dvbworld_ds3000_config,
  759. &dev->i2c_adap);
  760. if (dev->fe) {
  761. dvb_attach(ts2020_attach, dev->fe,
  762. &dvbworld_ts2020_config, &dev->i2c_adap);
  763. dev->fe->ops.set_voltage = dm1105_set_voltage;
  764. }
  765. break;
  766. case DM1105_BOARD_DVBWORLD_2002:
  767. case DM1105_BOARD_AXESS_DM05:
  768. default:
  769. dev->fe = dvb_attach(
  770. stv0299_attach, &sharp_z0194a_config,
  771. &dev->i2c_adap);
  772. if (dev->fe) {
  773. dev->fe->ops.set_voltage = dm1105_set_voltage;
  774. dvb_attach(dvb_pll_attach, dev->fe, 0x60,
  775. &dev->i2c_adap, DVB_PLL_OPERA1);
  776. break;
  777. }
  778. dev->fe = dvb_attach(
  779. stv0288_attach, &earda_config,
  780. &dev->i2c_adap);
  781. if (dev->fe) {
  782. dev->fe->ops.set_voltage = dm1105_set_voltage;
  783. dvb_attach(stb6000_attach, dev->fe, 0x61,
  784. &dev->i2c_adap);
  785. break;
  786. }
  787. dev->fe = dvb_attach(
  788. si21xx_attach, &serit_config,
  789. &dev->i2c_adap);
  790. if (dev->fe)
  791. dev->fe->ops.set_voltage = dm1105_set_voltage;
  792. }
  793. if (!dev->fe) {
  794. dev_err(&dev->pdev->dev, "could not attach frontend\n");
  795. return -ENODEV;
  796. }
  797. ret = dvb_register_frontend(&dev->dvb_adapter, dev->fe);
  798. if (ret < 0) {
  799. if (dev->fe->ops.release)
  800. dev->fe->ops.release(dev->fe);
  801. dev->fe = NULL;
  802. return ret;
  803. }
  804. return 0;
  805. }
  806. static void dm1105_read_mac(struct dm1105_dev *dev, u8 *mac)
  807. {
  808. static u8 command[1] = { 0x28 };
  809. struct i2c_msg msg[] = {
  810. {
  811. .addr = IIC_24C01_addr >> 1,
  812. .flags = 0,
  813. .buf = command,
  814. .len = 1
  815. }, {
  816. .addr = IIC_24C01_addr >> 1,
  817. .flags = I2C_M_RD,
  818. .buf = mac,
  819. .len = 6
  820. },
  821. };
  822. dm1105_i2c_xfer(&dev->i2c_adap, msg , 2);
  823. dev_info(&dev->pdev->dev, "MAC %pM\n", mac);
  824. }
  825. static int dm1105_probe(struct pci_dev *pdev,
  826. const struct pci_device_id *ent)
  827. {
  828. struct dm1105_dev *dev;
  829. struct dvb_adapter *dvb_adapter;
  830. struct dvb_demux *dvbdemux;
  831. struct dmx_demux *dmx;
  832. int ret = -ENOMEM;
  833. int i;
  834. if (dm1105_devcount >= ARRAY_SIZE(card))
  835. return -ENODEV;
  836. dev = kzalloc(sizeof(struct dm1105_dev), GFP_KERNEL);
  837. if (!dev)
  838. return -ENOMEM;
  839. /* board config */
  840. dev->nr = dm1105_devcount;
  841. dev->boardnr = UNSET;
  842. if (card[dev->nr] < ARRAY_SIZE(dm1105_boards))
  843. dev->boardnr = card[dev->nr];
  844. for (i = 0; UNSET == dev->boardnr &&
  845. i < ARRAY_SIZE(dm1105_subids); i++)
  846. if (pdev->subsystem_vendor ==
  847. dm1105_subids[i].subvendor &&
  848. pdev->subsystem_device ==
  849. dm1105_subids[i].subdevice)
  850. dev->boardnr = dm1105_subids[i].card;
  851. if (UNSET == dev->boardnr) {
  852. dev->boardnr = DM1105_BOARD_UNKNOWN;
  853. dm1105_card_list(pdev);
  854. }
  855. dm1105_devcount++;
  856. dev->pdev = pdev;
  857. dev->buffer_size = 5 * DM1105_DMA_BYTES;
  858. dev->PacketErrorCount = 0;
  859. dev->dmarst = 0;
  860. ret = pci_enable_device(pdev);
  861. if (ret < 0)
  862. goto err_kfree;
  863. ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  864. if (ret < 0)
  865. goto err_pci_disable_device;
  866. pci_set_master(pdev);
  867. ret = pci_request_regions(pdev, DRIVER_NAME);
  868. if (ret < 0)
  869. goto err_pci_disable_device;
  870. dev->io_mem = pci_iomap(pdev, 0, pci_resource_len(pdev, 0));
  871. if (!dev->io_mem) {
  872. ret = -EIO;
  873. goto err_pci_release_regions;
  874. }
  875. spin_lock_init(&dev->lock);
  876. pci_set_drvdata(pdev, dev);
  877. ret = dm1105_hw_init(dev);
  878. if (ret < 0)
  879. goto err_pci_iounmap;
  880. /* i2c */
  881. i2c_set_adapdata(&dev->i2c_adap, dev);
  882. strcpy(dev->i2c_adap.name, DRIVER_NAME);
  883. dev->i2c_adap.owner = THIS_MODULE;
  884. dev->i2c_adap.dev.parent = &pdev->dev;
  885. dev->i2c_adap.algo = &dm1105_algo;
  886. dev->i2c_adap.algo_data = dev;
  887. ret = i2c_add_adapter(&dev->i2c_adap);
  888. if (ret < 0)
  889. goto err_dm1105_hw_exit;
  890. i2c_set_adapdata(&dev->i2c_bb_adap, dev);
  891. strcpy(dev->i2c_bb_adap.name, DM1105_I2C_GPIO_NAME);
  892. dev->i2c_bb_adap.owner = THIS_MODULE;
  893. dev->i2c_bb_adap.dev.parent = &pdev->dev;
  894. dev->i2c_bb_adap.algo_data = &dev->i2c_bit;
  895. dev->i2c_bit.data = dev;
  896. dev->i2c_bit.setsda = dm1105_setsda;
  897. dev->i2c_bit.setscl = dm1105_setscl;
  898. dev->i2c_bit.getsda = dm1105_getsda;
  899. dev->i2c_bit.getscl = dm1105_getscl;
  900. dev->i2c_bit.udelay = 10;
  901. dev->i2c_bit.timeout = 10;
  902. /* Raise SCL and SDA */
  903. dm1105_setsda(dev, 1);
  904. dm1105_setscl(dev, 1);
  905. ret = i2c_bit_add_bus(&dev->i2c_bb_adap);
  906. if (ret < 0)
  907. goto err_i2c_del_adapter;
  908. /* dvb */
  909. ret = dvb_register_adapter(&dev->dvb_adapter, DRIVER_NAME,
  910. THIS_MODULE, &pdev->dev, adapter_nr);
  911. if (ret < 0)
  912. goto err_i2c_del_adapters;
  913. dvb_adapter = &dev->dvb_adapter;
  914. dm1105_read_mac(dev, dvb_adapter->proposed_mac);
  915. dvbdemux = &dev->demux;
  916. dvbdemux->filternum = 256;
  917. dvbdemux->feednum = 256;
  918. dvbdemux->start_feed = dm1105_start_feed;
  919. dvbdemux->stop_feed = dm1105_stop_feed;
  920. dvbdemux->dmx.capabilities = (DMX_TS_FILTERING |
  921. DMX_SECTION_FILTERING | DMX_MEMORY_BASED_FILTERING);
  922. ret = dvb_dmx_init(dvbdemux);
  923. if (ret < 0)
  924. goto err_dvb_unregister_adapter;
  925. dmx = &dvbdemux->dmx;
  926. dev->dmxdev.filternum = 256;
  927. dev->dmxdev.demux = dmx;
  928. dev->dmxdev.capabilities = 0;
  929. ret = dvb_dmxdev_init(&dev->dmxdev, dvb_adapter);
  930. if (ret < 0)
  931. goto err_dvb_dmx_release;
  932. dev->hw_frontend.source = DMX_FRONTEND_0;
  933. ret = dmx->add_frontend(dmx, &dev->hw_frontend);
  934. if (ret < 0)
  935. goto err_dvb_dmxdev_release;
  936. dev->mem_frontend.source = DMX_MEMORY_FE;
  937. ret = dmx->add_frontend(dmx, &dev->mem_frontend);
  938. if (ret < 0)
  939. goto err_remove_hw_frontend;
  940. ret = dmx->connect_frontend(dmx, &dev->hw_frontend);
  941. if (ret < 0)
  942. goto err_remove_mem_frontend;
  943. ret = dvb_net_init(dvb_adapter, &dev->dvbnet, dmx);
  944. if (ret < 0)
  945. goto err_disconnect_frontend;
  946. ret = frontend_init(dev);
  947. if (ret < 0)
  948. goto err_dvb_net;
  949. dm1105_ir_init(dev);
  950. INIT_WORK(&dev->work, dm1105_dmx_buffer);
  951. sprintf(dev->wqn, "%s/%d", dvb_adapter->name, dvb_adapter->num);
  952. dev->wq = create_singlethread_workqueue(dev->wqn);
  953. if (!dev->wq) {
  954. ret = -ENOMEM;
  955. goto err_dvb_net;
  956. }
  957. ret = request_irq(pdev->irq, dm1105_irq, IRQF_SHARED,
  958. DRIVER_NAME, dev);
  959. if (ret < 0)
  960. goto err_workqueue;
  961. return 0;
  962. err_workqueue:
  963. destroy_workqueue(dev->wq);
  964. err_dvb_net:
  965. dvb_net_release(&dev->dvbnet);
  966. err_disconnect_frontend:
  967. dmx->disconnect_frontend(dmx);
  968. err_remove_mem_frontend:
  969. dmx->remove_frontend(dmx, &dev->mem_frontend);
  970. err_remove_hw_frontend:
  971. dmx->remove_frontend(dmx, &dev->hw_frontend);
  972. err_dvb_dmxdev_release:
  973. dvb_dmxdev_release(&dev->dmxdev);
  974. err_dvb_dmx_release:
  975. dvb_dmx_release(dvbdemux);
  976. err_dvb_unregister_adapter:
  977. dvb_unregister_adapter(dvb_adapter);
  978. err_i2c_del_adapters:
  979. i2c_del_adapter(&dev->i2c_bb_adap);
  980. err_i2c_del_adapter:
  981. i2c_del_adapter(&dev->i2c_adap);
  982. err_dm1105_hw_exit:
  983. dm1105_hw_exit(dev);
  984. err_pci_iounmap:
  985. pci_iounmap(pdev, dev->io_mem);
  986. err_pci_release_regions:
  987. pci_release_regions(pdev);
  988. err_pci_disable_device:
  989. pci_disable_device(pdev);
  990. err_kfree:
  991. kfree(dev);
  992. return ret;
  993. }
  994. static void dm1105_remove(struct pci_dev *pdev)
  995. {
  996. struct dm1105_dev *dev = pci_get_drvdata(pdev);
  997. struct dvb_adapter *dvb_adapter = &dev->dvb_adapter;
  998. struct dvb_demux *dvbdemux = &dev->demux;
  999. struct dmx_demux *dmx = &dvbdemux->dmx;
  1000. dm1105_ir_exit(dev);
  1001. dmx->close(dmx);
  1002. dvb_net_release(&dev->dvbnet);
  1003. if (dev->fe)
  1004. dvb_unregister_frontend(dev->fe);
  1005. dmx->disconnect_frontend(dmx);
  1006. dmx->remove_frontend(dmx, &dev->mem_frontend);
  1007. dmx->remove_frontend(dmx, &dev->hw_frontend);
  1008. dvb_dmxdev_release(&dev->dmxdev);
  1009. dvb_dmx_release(dvbdemux);
  1010. dvb_unregister_adapter(dvb_adapter);
  1011. i2c_del_adapter(&dev->i2c_adap);
  1012. dm1105_hw_exit(dev);
  1013. free_irq(pdev->irq, dev);
  1014. pci_iounmap(pdev, dev->io_mem);
  1015. pci_release_regions(pdev);
  1016. pci_disable_device(pdev);
  1017. dm1105_devcount--;
  1018. kfree(dev);
  1019. }
  1020. static const struct pci_device_id dm1105_id_table[] = {
  1021. {
  1022. .vendor = PCI_VENDOR_ID_TRIGEM,
  1023. .device = PCI_DEVICE_ID_DM1105,
  1024. .subvendor = PCI_ANY_ID,
  1025. .subdevice = PCI_ANY_ID,
  1026. }, {
  1027. .vendor = PCI_VENDOR_ID_AXESS,
  1028. .device = PCI_DEVICE_ID_DM05,
  1029. .subvendor = PCI_ANY_ID,
  1030. .subdevice = PCI_ANY_ID,
  1031. }, {
  1032. /* empty */
  1033. },
  1034. };
  1035. MODULE_DEVICE_TABLE(pci, dm1105_id_table);
  1036. static struct pci_driver dm1105_driver = {
  1037. .name = DRIVER_NAME,
  1038. .id_table = dm1105_id_table,
  1039. .probe = dm1105_probe,
  1040. .remove = dm1105_remove,
  1041. };
  1042. module_pci_driver(dm1105_driver);
  1043. MODULE_AUTHOR("Igor M. Liplianin <liplianin@me.by>");
  1044. MODULE_DESCRIPTION("SDMC DM1105 DVB driver");
  1045. MODULE_LICENSE("GPL");