cx23418.h 17 KB

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  1. /*
  2. * cx18 header containing common defines.
  3. *
  4. * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. */
  16. #ifndef CX23418_H
  17. #define CX23418_H
  18. #include <media/drv-intf/cx2341x.h>
  19. #define MGR_CMD_MASK 0x40000000
  20. /* The MSB of the command code indicates that this is the completion of a
  21. command */
  22. #define MGR_CMD_MASK_ACK (MGR_CMD_MASK | 0x80000000)
  23. /* Description: This command creates a new instance of a certain task
  24. IN[0] - Task ID. This is one of the XPU_CMD_MASK_YYY where XPU is
  25. the processor on which the task YYY will be created
  26. OUT[0] - Task handle. This handle is passed along with commands to
  27. dispatch to the right instance of the task
  28. ReturnCode - One of the ERR_SYS_... */
  29. #define CX18_CREATE_TASK (MGR_CMD_MASK | 0x0001)
  30. /* Description: This command destroys an instance of a task
  31. IN[0] - Task handle. Hanlde of the task to destroy
  32. ReturnCode - One of the ERR_SYS_... */
  33. #define CX18_DESTROY_TASK (MGR_CMD_MASK | 0x0002)
  34. /* All commands for CPU have the following mask set */
  35. #define CPU_CMD_MASK 0x20000000
  36. #define CPU_CMD_MASK_DEBUG (CPU_CMD_MASK | 0x00000000)
  37. #define CPU_CMD_MASK_ACK (CPU_CMD_MASK | 0x80000000)
  38. #define CPU_CMD_MASK_CAPTURE (CPU_CMD_MASK | 0x00020000)
  39. #define CPU_CMD_MASK_TS (CPU_CMD_MASK | 0x00040000)
  40. #define EPU_CMD_MASK 0x02000000
  41. #define EPU_CMD_MASK_DEBUG (EPU_CMD_MASK | 0x000000)
  42. #define EPU_CMD_MASK_DE (EPU_CMD_MASK | 0x040000)
  43. #define APU_CMD_MASK 0x10000000
  44. #define APU_CMD_MASK_ACK (APU_CMD_MASK | 0x80000000)
  45. #define CX18_APU_ENCODING_METHOD_MPEG (0 << 28)
  46. #define CX18_APU_ENCODING_METHOD_AC3 (1 << 28)
  47. /* Description: Command APU to start audio
  48. IN[0] - audio parameters (same as CX18_CPU_SET_AUDIO_PARAMETERS?)
  49. IN[1] - caller buffer address, or 0
  50. ReturnCode - ??? */
  51. #define CX18_APU_START (APU_CMD_MASK | 0x01)
  52. /* Description: Command APU to stop audio
  53. IN[0] - encoding method to stop
  54. ReturnCode - ??? */
  55. #define CX18_APU_STOP (APU_CMD_MASK | 0x02)
  56. /* Description: Command APU to reset the AI
  57. ReturnCode - ??? */
  58. #define CX18_APU_RESETAI (APU_CMD_MASK | 0x05)
  59. /* Description: This command indicates that a Memory Descriptor List has been
  60. filled with the requested channel type
  61. IN[0] - Task handle. Handle of the task
  62. IN[1] - Offset of the MDL_ACK from the beginning of the local DDR.
  63. IN[2] - Number of CNXT_MDL_ACK structures in the array pointed to by IN[1]
  64. ReturnCode - One of the ERR_DE_... */
  65. #define CX18_EPU_DMA_DONE (EPU_CMD_MASK_DE | 0x0001)
  66. /* Something interesting happened
  67. IN[0] - A value to log
  68. IN[1] - An offset of a string in the MiniMe memory;
  69. 0/zero/NULL means "I have nothing to say" */
  70. #define CX18_EPU_DEBUG (EPU_CMD_MASK_DEBUG | 0x0003)
  71. /* Reads memory/registers (32-bit)
  72. IN[0] - Address
  73. OUT[1] - Value */
  74. #define CX18_CPU_DEBUG_PEEK32 (CPU_CMD_MASK_DEBUG | 0x0003)
  75. /* Description: This command starts streaming with the set channel type
  76. IN[0] - Task handle. Handle of the task to start
  77. ReturnCode - One of the ERR_CAPTURE_... */
  78. #define CX18_CPU_CAPTURE_START (CPU_CMD_MASK_CAPTURE | 0x0002)
  79. /* Description: This command stops streaming with the set channel type
  80. IN[0] - Task handle. Handle of the task to stop
  81. IN[1] - 0 = stop at end of GOP, 1 = stop at end of frame (MPEG only)
  82. ReturnCode - One of the ERR_CAPTURE_... */
  83. #define CX18_CPU_CAPTURE_STOP (CPU_CMD_MASK_CAPTURE | 0x0003)
  84. /* Description: This command pauses streaming with the set channel type
  85. IN[0] - Task handle. Handle of the task to pause
  86. ReturnCode - One of the ERR_CAPTURE_... */
  87. #define CX18_CPU_CAPTURE_PAUSE (CPU_CMD_MASK_CAPTURE | 0x0007)
  88. /* Description: This command resumes streaming with the set channel type
  89. IN[0] - Task handle. Handle of the task to resume
  90. ReturnCode - One of the ERR_CAPTURE_... */
  91. #define CX18_CPU_CAPTURE_RESUME (CPU_CMD_MASK_CAPTURE | 0x0008)
  92. #define CAPTURE_CHANNEL_TYPE_NONE 0
  93. #define CAPTURE_CHANNEL_TYPE_MPEG 1
  94. #define CAPTURE_CHANNEL_TYPE_INDEX 2
  95. #define CAPTURE_CHANNEL_TYPE_YUV 3
  96. #define CAPTURE_CHANNEL_TYPE_PCM 4
  97. #define CAPTURE_CHANNEL_TYPE_VBI 5
  98. #define CAPTURE_CHANNEL_TYPE_SLICED_VBI 6
  99. #define CAPTURE_CHANNEL_TYPE_TS 7
  100. #define CAPTURE_CHANNEL_TYPE_MAX 15
  101. /* Description: This command sets the channel type. This can only be done
  102. when stopped.
  103. IN[0] - Task handle. Handle of the task to start
  104. IN[1] - Channel Type. See Below.
  105. ReturnCode - One of the ERR_CAPTURE_... */
  106. #define CX18_CPU_SET_CHANNEL_TYPE (CPU_CMD_MASK_CAPTURE + 1)
  107. /* Description: Set stream output type
  108. IN[0] - task handle. Handle of the task to start
  109. IN[1] - type
  110. ReturnCode - One of the ERR_CAPTURE_... */
  111. #define CX18_CPU_SET_STREAM_OUTPUT_TYPE (CPU_CMD_MASK_CAPTURE | 0x0012)
  112. /* Description: Set video input resolution and frame rate
  113. IN[0] - task handle
  114. IN[1] - reserved
  115. IN[2] - reserved
  116. IN[3] - reserved
  117. IN[4] - reserved
  118. IN[5] - frame rate, 0 - 29.97f/s, 1 - 25f/s
  119. ReturnCode - One of the ERR_CAPTURE_... */
  120. #define CX18_CPU_SET_VIDEO_IN (CPU_CMD_MASK_CAPTURE | 0x0004)
  121. /* Description: Set video frame rate
  122. IN[0] - task handle. Handle of the task to start
  123. IN[1] - video bit rate mode
  124. IN[2] - video average rate
  125. IN[3] - video peak rate
  126. IN[4] - system mux rate
  127. ReturnCode - One of the ERR_CAPTURE_... */
  128. #define CX18_CPU_SET_VIDEO_RATE (CPU_CMD_MASK_CAPTURE | 0x0005)
  129. /* Description: Set video output resolution
  130. IN[0] - task handle
  131. IN[1] - horizontal size
  132. IN[2] - vertical size
  133. ReturnCode - One of the ERR_CAPTURE_... */
  134. #define CX18_CPU_SET_VIDEO_RESOLUTION (CPU_CMD_MASK_CAPTURE | 0x0006)
  135. /* Description: This command set filter parameters
  136. IN[0] - Task handle. Handle of the task
  137. IN[1] - type, 0 - temporal, 1 - spatial, 2 - median
  138. IN[2] - mode, temporal/spatial: 0 - disable, 1 - static, 2 - dynamic
  139. median: 0 = disable, 1 = horizontal, 2 = vertical,
  140. 3 = horizontal/vertical, 4 = diagonal
  141. IN[3] - strength, temporal 0 - 31, spatial 0 - 15
  142. ReturnCode - One of the ERR_CAPTURE_... */
  143. #define CX18_CPU_SET_FILTER_PARAM (CPU_CMD_MASK_CAPTURE | 0x0009)
  144. /* Description: This command set spatial filter type
  145. IN[0] - Task handle.
  146. IN[1] - luma type: 0 = disable, 1 = 1D horizontal only, 2 = 1D vertical only,
  147. 3 = 2D H/V separable, 4 = 2D symmetric non-separable
  148. IN[2] - chroma type: 0 - disable, 1 = 1D horizontal
  149. ReturnCode - One of the ERR_CAPTURE_... */
  150. #define CX18_CPU_SET_SPATIAL_FILTER_TYPE (CPU_CMD_MASK_CAPTURE | 0x000C)
  151. /* Description: This command set coring levels for median filter
  152. IN[0] - Task handle.
  153. IN[1] - luma_high
  154. IN[2] - luma_low
  155. IN[3] - chroma_high
  156. IN[4] - chroma_low
  157. ReturnCode - One of the ERR_CAPTURE_... */
  158. #define CX18_CPU_SET_MEDIAN_CORING (CPU_CMD_MASK_CAPTURE | 0x000E)
  159. /* Description: This command set the picture type mask for index file
  160. IN[0] - Task handle (ignored by firmware)
  161. IN[1] - 0 = disable index file output
  162. 1 = output I picture
  163. 2 = P picture
  164. 4 = B picture
  165. other = illegal */
  166. #define CX18_CPU_SET_INDEXTABLE (CPU_CMD_MASK_CAPTURE | 0x0010)
  167. /* Description: Set audio parameters
  168. IN[0] - task handle. Handle of the task to start
  169. IN[1] - audio parameter
  170. ReturnCode - One of the ERR_CAPTURE_... */
  171. #define CX18_CPU_SET_AUDIO_PARAMETERS (CPU_CMD_MASK_CAPTURE | 0x0011)
  172. /* Description: Set video mute
  173. IN[0] - task handle. Handle of the task to start
  174. IN[1] - bit31-24: muteYvalue
  175. bit23-16: muteUvalue
  176. bit15-8: muteVvalue
  177. bit0: 1:mute, 0: unmute
  178. ReturnCode - One of the ERR_CAPTURE_... */
  179. #define CX18_CPU_SET_VIDEO_MUTE (CPU_CMD_MASK_CAPTURE | 0x0013)
  180. /* Description: Set audio mute
  181. IN[0] - task handle. Handle of the task to start
  182. IN[1] - mute/unmute
  183. ReturnCode - One of the ERR_CAPTURE_... */
  184. #define CX18_CPU_SET_AUDIO_MUTE (CPU_CMD_MASK_CAPTURE | 0x0014)
  185. /* Description: Set stream output type
  186. IN[0] - task handle. Handle of the task to start
  187. IN[1] - subType
  188. SET_INITIAL_SCR 1
  189. SET_QUALITY_MODE 2
  190. SET_VIM_PROTECT_MODE 3
  191. SET_PTS_CORRECTION 4
  192. SET_USB_FLUSH_MODE 5
  193. SET_MERAQPAR_ENABLE 6
  194. SET_NAV_PACK_INSERTION 7
  195. SET_SCENE_CHANGE_ENABLE 8
  196. IN[2] - parameter 1
  197. IN[3] - parameter 2
  198. ReturnCode - One of the ERR_CAPTURE_... */
  199. #define CX18_CPU_SET_MISC_PARAMETERS (CPU_CMD_MASK_CAPTURE | 0x0015)
  200. /* Description: Set raw VBI parameters
  201. IN[0] - Task handle
  202. IN[1] - No. of input lines per field:
  203. bit[15:0]: field 1,
  204. bit[31:16]: field 2
  205. IN[2] - No. of input bytes per line
  206. IN[3] - No. of output frames per transfer
  207. IN[4] - start code
  208. IN[5] - stop code
  209. ReturnCode */
  210. #define CX18_CPU_SET_RAW_VBI_PARAM (CPU_CMD_MASK_CAPTURE | 0x0016)
  211. /* Description: Set capture line No.
  212. IN[0] - task handle. Handle of the task to start
  213. IN[1] - height1
  214. IN[2] - height2
  215. ReturnCode - One of the ERR_CAPTURE_... */
  216. #define CX18_CPU_SET_CAPTURE_LINE_NO (CPU_CMD_MASK_CAPTURE | 0x0017)
  217. /* Description: Set copyright
  218. IN[0] - task handle. Handle of the task to start
  219. IN[1] - copyright
  220. ReturnCode - One of the ERR_CAPTURE_... */
  221. #define CX18_CPU_SET_COPYRIGHT (CPU_CMD_MASK_CAPTURE | 0x0018)
  222. /* Description: Set audio PID
  223. IN[0] - task handle. Handle of the task to start
  224. IN[1] - PID
  225. ReturnCode - One of the ERR_CAPTURE_... */
  226. #define CX18_CPU_SET_AUDIO_PID (CPU_CMD_MASK_CAPTURE | 0x0019)
  227. /* Description: Set video PID
  228. IN[0] - task handle. Handle of the task to start
  229. IN[1] - PID
  230. ReturnCode - One of the ERR_CAPTURE_... */
  231. #define CX18_CPU_SET_VIDEO_PID (CPU_CMD_MASK_CAPTURE | 0x001A)
  232. /* Description: Set Vertical Crop Line
  233. IN[0] - task handle. Handle of the task to start
  234. IN[1] - Line
  235. ReturnCode - One of the ERR_CAPTURE_... */
  236. #define CX18_CPU_SET_VER_CROP_LINE (CPU_CMD_MASK_CAPTURE | 0x001B)
  237. /* Description: Set COP structure
  238. IN[0] - task handle. Handle of the task to start
  239. IN[1] - M
  240. IN[2] - N
  241. ReturnCode - One of the ERR_CAPTURE_... */
  242. #define CX18_CPU_SET_GOP_STRUCTURE (CPU_CMD_MASK_CAPTURE | 0x001C)
  243. /* Description: Set Scene Change Detection
  244. IN[0] - task handle. Handle of the task to start
  245. IN[1] - scene change
  246. ReturnCode - One of the ERR_CAPTURE_... */
  247. #define CX18_CPU_SET_SCENE_CHANGE_DETECTION (CPU_CMD_MASK_CAPTURE | 0x001D)
  248. /* Description: Set Aspect Ratio
  249. IN[0] - task handle. Handle of the task to start
  250. IN[1] - AspectRatio
  251. ReturnCode - One of the ERR_CAPTURE_... */
  252. #define CX18_CPU_SET_ASPECT_RATIO (CPU_CMD_MASK_CAPTURE | 0x001E)
  253. /* Description: Set Skip Input Frame
  254. IN[0] - task handle. Handle of the task to start
  255. IN[1] - skip input frames
  256. ReturnCode - One of the ERR_CAPTURE_... */
  257. #define CX18_CPU_SET_SKIP_INPUT_FRAME (CPU_CMD_MASK_CAPTURE | 0x001F)
  258. /* Description: Set sliced VBI parameters -
  259. Note This API will only apply to MPEG and Sliced VBI Channels
  260. IN[0] - Task handle
  261. IN[1] - output type, 0 - CC, 1 - Moji, 2 - Teletext
  262. IN[2] - start / stop line
  263. bit[15:0] start line number
  264. bit[31:16] stop line number
  265. IN[3] - number of output frames per interrupt
  266. IN[4] - VBI insertion mode
  267. bit 0: output user data, 1 - enable
  268. bit 1: output private stream, 1 - enable
  269. bit 2: mux option, 0 - in GOP, 1 - in picture
  270. bit[7:0] private stream ID
  271. IN[5] - insertion period while mux option is in picture
  272. ReturnCode - VBI data offset */
  273. #define CX18_CPU_SET_SLICED_VBI_PARAM (CPU_CMD_MASK_CAPTURE | 0x0020)
  274. /* Description: Set the user data place holder
  275. IN[0] - type of data (0 for user)
  276. IN[1] - Stuffing period
  277. IN[2] - ID data size in word (less than 10)
  278. IN[3] - Pointer to ID buffer */
  279. #define CX18_CPU_SET_USERDATA_PLACE_HOLDER (CPU_CMD_MASK_CAPTURE | 0x0021)
  280. /* Description:
  281. In[0] Task Handle
  282. return parameter:
  283. Out[0] Reserved
  284. Out[1] Video PTS bit[32:2] of last output video frame.
  285. Out[2] Video PTS bit[ 1:0] of last output video frame.
  286. Out[3] Hardware Video PTS counter bit[31:0],
  287. these bits get incremented on every 90kHz clock tick.
  288. Out[4] Hardware Video PTS counter bit32,
  289. these bits get incremented on every 90kHz clock tick.
  290. ReturnCode */
  291. #define CX18_CPU_GET_ENC_PTS (CPU_CMD_MASK_CAPTURE | 0x0022)
  292. /* Description: Set VFC parameters
  293. IN[0] - task handle
  294. IN[1] - VFC enable flag, 1 - enable, 0 - disable
  295. */
  296. #define CX18_CPU_SET_VFC_PARAM (CPU_CMD_MASK_CAPTURE | 0x0023)
  297. /* Below is the list of commands related to the data exchange */
  298. #define CPU_CMD_MASK_DE (CPU_CMD_MASK | 0x040000)
  299. /* Description: This command provides the physical base address of the local
  300. DDR as viewed by EPU
  301. IN[0] - Physical offset where EPU has the local DDR mapped
  302. ReturnCode - One of the ERR_DE_... */
  303. #define CPU_CMD_DE_SetBase (CPU_CMD_MASK_DE | 0x0001)
  304. /* Description: This command provides the offsets in the device memory where
  305. the 2 cx18_mdl_ack blocks reside
  306. IN[0] - Task handle. Handle of the task to start
  307. IN[1] - Offset of the first cx18_mdl_ack from the beginning of the
  308. local DDR.
  309. IN[2] - Offset of the second cx18_mdl_ack from the beginning of the
  310. local DDR.
  311. ReturnCode - One of the ERR_DE_... */
  312. #define CX18_CPU_DE_SET_MDL_ACK (CPU_CMD_MASK_DE | 0x0002)
  313. /* Description: This command provides the offset to a Memory Descriptor List
  314. IN[0] - Task handle. Handle of the task to start
  315. IN[1] - Offset of the MDL from the beginning of the local DDR.
  316. IN[2] - Number of cx18_mdl_ent structures in the array pointed to by IN[1]
  317. IN[3] - Buffer ID
  318. IN[4] - Total buffer length
  319. ReturnCode - One of the ERR_DE_... */
  320. #define CX18_CPU_DE_SET_MDL (CPU_CMD_MASK_DE | 0x0005)
  321. /* Description: This command requests return of all current Memory
  322. Descriptor Lists to the driver
  323. IN[0] - Task handle. Handle of the task to start
  324. ReturnCode - One of the ERR_DE_... */
  325. #define CX18_CPU_DE_RELEASE_MDL (CPU_CMD_MASK_DE | 0x0006)
  326. /* Description: This command signals the cpu that the dat buffer has been
  327. consumed and ready for re-use.
  328. IN[0] - Task handle. Handle of the task
  329. IN[1] - Offset of the data block from the beginning of the local DDR.
  330. IN[2] - Number of bytes in the data block
  331. ReturnCode - One of the ERR_DE_... */
  332. /* #define CX18_CPU_DE_RELEASE_BUFFER (CPU_CMD_MASK_DE | 0x0007) */
  333. /* No Error / Success */
  334. #define CNXT_OK 0x000000
  335. /* Received unknown command */
  336. #define CXERR_UNK_CMD 0x000001
  337. /* First parameter in the command is invalid */
  338. #define CXERR_INVALID_PARAM1 0x000002
  339. /* Second parameter in the command is invalid */
  340. #define CXERR_INVALID_PARAM2 0x000003
  341. /* Device interface is not open/found */
  342. #define CXERR_DEV_NOT_FOUND 0x000004
  343. /* Requested function is not implemented/available */
  344. #define CXERR_NOTSUPPORTED 0x000005
  345. /* Invalid pointer is provided */
  346. #define CXERR_BADPTR 0x000006
  347. /* Unable to allocate memory */
  348. #define CXERR_NOMEM 0x000007
  349. /* Object/Link not found */
  350. #define CXERR_LINK 0x000008
  351. /* Device busy, command cannot be executed */
  352. #define CXERR_BUSY 0x000009
  353. /* File/device/handle is not open. */
  354. #define CXERR_NOT_OPEN 0x00000A
  355. /* Value is out of range */
  356. #define CXERR_OUTOFRANGE 0x00000B
  357. /* Buffer overflow */
  358. #define CXERR_OVERFLOW 0x00000C
  359. /* Version mismatch */
  360. #define CXERR_BADVER 0x00000D
  361. /* Operation timed out */
  362. #define CXERR_TIMEOUT 0x00000E
  363. /* Operation aborted */
  364. #define CXERR_ABORT 0x00000F
  365. /* Specified I2C device not found for read/write */
  366. #define CXERR_I2CDEV_NOTFOUND 0x000010
  367. /* Error in I2C data xfer (but I2C device is present) */
  368. #define CXERR_I2CDEV_XFERERR 0x000011
  369. /* Chanel changing component not ready */
  370. #define CXERR_CHANNELNOTREADY 0x000012
  371. /* PPU (Presensation/Decoder) mail box is corrupted */
  372. #define CXERR_PPU_MB_CORRUPT 0x000013
  373. /* CPU (Capture/Encoder) mail box is corrupted */
  374. #define CXERR_CPU_MB_CORRUPT 0x000014
  375. /* APU (Audio) mail box is corrupted */
  376. #define CXERR_APU_MB_CORRUPT 0x000015
  377. /* Unable to open file for reading */
  378. #define CXERR_FILE_OPEN_READ 0x000016
  379. /* Unable to open file for writing */
  380. #define CXERR_FILE_OPEN_WRITE 0x000017
  381. /* Unable to find the I2C section specified */
  382. #define CXERR_I2C_BADSECTION 0x000018
  383. /* Error in I2C data xfer (but I2C device is present) */
  384. #define CXERR_I2CDEV_DATALOW 0x000019
  385. /* Error in I2C data xfer (but I2C device is present) */
  386. #define CXERR_I2CDEV_CLOCKLOW 0x00001A
  387. /* No Interrupt received from HW (for I2C access) */
  388. #define CXERR_NO_HW_I2C_INTR 0x00001B
  389. /* RPU is not ready to accept commands! */
  390. #define CXERR_RPU_NOT_READY 0x00001C
  391. /* RPU is not ready to accept commands! */
  392. #define CXERR_RPU_NO_ACK 0x00001D
  393. /* The are no buffers ready. Try again soon! */
  394. #define CXERR_NODATA_AGAIN 0x00001E
  395. /* The stream is stopping. Function not allowed now! */
  396. #define CXERR_STOPPING_STATUS 0x00001F
  397. /* Trying to access hardware when the power is turned OFF */
  398. #define CXERR_DEVPOWER_OFF 0x000020
  399. #endif /* CX23418_H */