tda18271c2dd.c 29 KB

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  1. /*
  2. * tda18271c2dd: Driver for the TDA18271C2 tuner
  3. *
  4. * Copyright (C) 2010 Digital Devices GmbH
  5. *
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * version 2 only, as published by the Free Software Foundation.
  10. *
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * To obtain the license, point your browser to
  18. * http://www.gnu.org/copyleft/gpl.html
  19. */
  20. #include <linux/kernel.h>
  21. #include <linux/module.h>
  22. #include <linux/moduleparam.h>
  23. #include <linux/init.h>
  24. #include <linux/delay.h>
  25. #include <linux/firmware.h>
  26. #include <linux/i2c.h>
  27. #include <asm/div64.h>
  28. #include <media/dvb_frontend.h>
  29. #include "tda18271c2dd.h"
  30. /* Max transfer size done by I2C transfer functions */
  31. #define MAX_XFER_SIZE 64
  32. struct SStandardParam {
  33. s32 m_IFFrequency;
  34. u32 m_BandWidth;
  35. u8 m_EP3_4_0;
  36. u8 m_EB22;
  37. };
  38. struct SMap {
  39. u32 m_Frequency;
  40. u8 m_Param;
  41. };
  42. struct SMapI {
  43. u32 m_Frequency;
  44. s32 m_Param;
  45. };
  46. struct SMap2 {
  47. u32 m_Frequency;
  48. u8 m_Param1;
  49. u8 m_Param2;
  50. };
  51. struct SRFBandMap {
  52. u32 m_RF_max;
  53. u32 m_RF1_Default;
  54. u32 m_RF2_Default;
  55. u32 m_RF3_Default;
  56. };
  57. enum ERegister {
  58. ID = 0,
  59. TM,
  60. PL,
  61. EP1, EP2, EP3, EP4, EP5,
  62. CPD, CD1, CD2, CD3,
  63. MPD, MD1, MD2, MD3,
  64. EB1, EB2, EB3, EB4, EB5, EB6, EB7, EB8, EB9, EB10,
  65. EB11, EB12, EB13, EB14, EB15, EB16, EB17, EB18, EB19, EB20,
  66. EB21, EB22, EB23,
  67. NUM_REGS
  68. };
  69. struct tda_state {
  70. struct i2c_adapter *i2c;
  71. u8 adr;
  72. u32 m_Frequency;
  73. u32 IF;
  74. u8 m_IFLevelAnalog;
  75. u8 m_IFLevelDigital;
  76. u8 m_IFLevelDVBC;
  77. u8 m_IFLevelDVBT;
  78. u8 m_EP4;
  79. u8 m_EP3_Standby;
  80. bool m_bMaster;
  81. s32 m_SettlingTime;
  82. u8 m_Regs[NUM_REGS];
  83. /* Tracking filter settings for band 0..6 */
  84. u32 m_RF1[7];
  85. s32 m_RF_A1[7];
  86. s32 m_RF_B1[7];
  87. u32 m_RF2[7];
  88. s32 m_RF_A2[7];
  89. s32 m_RF_B2[7];
  90. u32 m_RF3[7];
  91. u8 m_TMValue_RFCal; /* Calibration temperatur */
  92. bool m_bFMInput; /* true to use Pin 8 for FM Radio */
  93. };
  94. static int PowerScan(struct tda_state *state,
  95. u8 RFBand, u32 RF_in,
  96. u32 *pRF_Out, bool *pbcal);
  97. static int i2c_readn(struct i2c_adapter *adapter, u8 adr, u8 *data, int len)
  98. {
  99. struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD,
  100. .buf = data, .len = len} };
  101. return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1;
  102. }
  103. static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len)
  104. {
  105. struct i2c_msg msg = {.addr = adr, .flags = 0,
  106. .buf = data, .len = len};
  107. if (i2c_transfer(adap, &msg, 1) != 1) {
  108. printk(KERN_ERR "tda18271c2dd: i2c write error at addr %i\n", adr);
  109. return -1;
  110. }
  111. return 0;
  112. }
  113. static int WriteRegs(struct tda_state *state,
  114. u8 SubAddr, u8 *Regs, u16 nRegs)
  115. {
  116. u8 data[MAX_XFER_SIZE];
  117. if (1 + nRegs > sizeof(data)) {
  118. printk(KERN_WARNING
  119. "%s: i2c wr: len=%d is too big!\n",
  120. KBUILD_MODNAME, nRegs);
  121. return -EINVAL;
  122. }
  123. data[0] = SubAddr;
  124. memcpy(data + 1, Regs, nRegs);
  125. return i2c_write(state->i2c, state->adr, data, nRegs + 1);
  126. }
  127. static int WriteReg(struct tda_state *state, u8 SubAddr, u8 Reg)
  128. {
  129. u8 msg[2] = {SubAddr, Reg};
  130. return i2c_write(state->i2c, state->adr, msg, 2);
  131. }
  132. static int Read(struct tda_state *state, u8 * Regs)
  133. {
  134. return i2c_readn(state->i2c, state->adr, Regs, 16);
  135. }
  136. static int ReadExtented(struct tda_state *state, u8 * Regs)
  137. {
  138. return i2c_readn(state->i2c, state->adr, Regs, NUM_REGS);
  139. }
  140. static int UpdateRegs(struct tda_state *state, u8 RegFrom, u8 RegTo)
  141. {
  142. return WriteRegs(state, RegFrom,
  143. &state->m_Regs[RegFrom], RegTo-RegFrom+1);
  144. }
  145. static int UpdateReg(struct tda_state *state, u8 Reg)
  146. {
  147. return WriteReg(state, Reg, state->m_Regs[Reg]);
  148. }
  149. #include "tda18271c2dd_maps.h"
  150. static void reset(struct tda_state *state)
  151. {
  152. u32 ulIFLevelAnalog = 0;
  153. u32 ulIFLevelDigital = 2;
  154. u32 ulIFLevelDVBC = 7;
  155. u32 ulIFLevelDVBT = 6;
  156. u32 ulXTOut = 0;
  157. u32 ulStandbyMode = 0x06; /* Send in stdb, but leave osc on */
  158. u32 ulSlave = 0;
  159. u32 ulFMInput = 0;
  160. u32 ulSettlingTime = 100;
  161. state->m_Frequency = 0;
  162. state->m_SettlingTime = 100;
  163. state->m_IFLevelAnalog = (ulIFLevelAnalog & 0x07) << 2;
  164. state->m_IFLevelDigital = (ulIFLevelDigital & 0x07) << 2;
  165. state->m_IFLevelDVBC = (ulIFLevelDVBC & 0x07) << 2;
  166. state->m_IFLevelDVBT = (ulIFLevelDVBT & 0x07) << 2;
  167. state->m_EP4 = 0x20;
  168. if (ulXTOut != 0)
  169. state->m_EP4 |= 0x40;
  170. state->m_EP3_Standby = ((ulStandbyMode & 0x07) << 5) | 0x0F;
  171. state->m_bMaster = (ulSlave == 0);
  172. state->m_SettlingTime = ulSettlingTime;
  173. state->m_bFMInput = (ulFMInput == 2);
  174. }
  175. static bool SearchMap1(struct SMap Map[],
  176. u32 Frequency, u8 *pParam)
  177. {
  178. int i = 0;
  179. while ((Map[i].m_Frequency != 0) && (Frequency > Map[i].m_Frequency))
  180. i += 1;
  181. if (Map[i].m_Frequency == 0)
  182. return false;
  183. *pParam = Map[i].m_Param;
  184. return true;
  185. }
  186. static bool SearchMap2(struct SMapI Map[],
  187. u32 Frequency, s32 *pParam)
  188. {
  189. int i = 0;
  190. while ((Map[i].m_Frequency != 0) &&
  191. (Frequency > Map[i].m_Frequency))
  192. i += 1;
  193. if (Map[i].m_Frequency == 0)
  194. return false;
  195. *pParam = Map[i].m_Param;
  196. return true;
  197. }
  198. static bool SearchMap3(struct SMap2 Map[], u32 Frequency,
  199. u8 *pParam1, u8 *pParam2)
  200. {
  201. int i = 0;
  202. while ((Map[i].m_Frequency != 0) &&
  203. (Frequency > Map[i].m_Frequency))
  204. i += 1;
  205. if (Map[i].m_Frequency == 0)
  206. return false;
  207. *pParam1 = Map[i].m_Param1;
  208. *pParam2 = Map[i].m_Param2;
  209. return true;
  210. }
  211. static bool SearchMap4(struct SRFBandMap Map[],
  212. u32 Frequency, u8 *pRFBand)
  213. {
  214. int i = 0;
  215. while (i < 7 && (Frequency > Map[i].m_RF_max))
  216. i += 1;
  217. if (i == 7)
  218. return false;
  219. *pRFBand = i;
  220. return true;
  221. }
  222. static int ThermometerRead(struct tda_state *state, u8 *pTM_Value)
  223. {
  224. int status = 0;
  225. do {
  226. u8 Regs[16];
  227. state->m_Regs[TM] |= 0x10;
  228. status = UpdateReg(state, TM);
  229. if (status < 0)
  230. break;
  231. status = Read(state, Regs);
  232. if (status < 0)
  233. break;
  234. if (((Regs[TM] & 0x0F) == 0 && (Regs[TM] & 0x20) == 0x20) ||
  235. ((Regs[TM] & 0x0F) == 8 && (Regs[TM] & 0x20) == 0x00)) {
  236. state->m_Regs[TM] ^= 0x20;
  237. status = UpdateReg(state, TM);
  238. if (status < 0)
  239. break;
  240. msleep(10);
  241. status = Read(state, Regs);
  242. if (status < 0)
  243. break;
  244. }
  245. *pTM_Value = (Regs[TM] & 0x20)
  246. ? m_Thermometer_Map_2[Regs[TM] & 0x0F]
  247. : m_Thermometer_Map_1[Regs[TM] & 0x0F] ;
  248. state->m_Regs[TM] &= ~0x10; /* Thermometer off */
  249. status = UpdateReg(state, TM);
  250. if (status < 0)
  251. break;
  252. state->m_Regs[EP4] &= ~0x03; /* CAL_mode = 0 ????????? */
  253. status = UpdateReg(state, EP4);
  254. if (status < 0)
  255. break;
  256. } while (0);
  257. return status;
  258. }
  259. static int StandBy(struct tda_state *state)
  260. {
  261. int status = 0;
  262. do {
  263. state->m_Regs[EB12] &= ~0x20; /* PD_AGC1_Det = 0 */
  264. status = UpdateReg(state, EB12);
  265. if (status < 0)
  266. break;
  267. state->m_Regs[EB18] &= ~0x83; /* AGC1_loop_off = 0, AGC1_Gain = 6 dB */
  268. status = UpdateReg(state, EB18);
  269. if (status < 0)
  270. break;
  271. state->m_Regs[EB21] |= 0x03; /* AGC2_Gain = -6 dB */
  272. state->m_Regs[EP3] = state->m_EP3_Standby;
  273. status = UpdateReg(state, EP3);
  274. if (status < 0)
  275. break;
  276. state->m_Regs[EB23] &= ~0x06; /* ForceLP_Fc2_En = 0, LP_Fc[2] = 0 */
  277. status = UpdateRegs(state, EB21, EB23);
  278. if (status < 0)
  279. break;
  280. } while (0);
  281. return status;
  282. }
  283. static int CalcMainPLL(struct tda_state *state, u32 freq)
  284. {
  285. u8 PostDiv;
  286. u8 Div;
  287. u64 OscFreq;
  288. u32 MainDiv;
  289. if (!SearchMap3(m_Main_PLL_Map, freq, &PostDiv, &Div))
  290. return -EINVAL;
  291. OscFreq = (u64) freq * (u64) Div;
  292. OscFreq *= (u64) 16384;
  293. do_div(OscFreq, (u64)16000000);
  294. MainDiv = OscFreq;
  295. state->m_Regs[MPD] = PostDiv & 0x77;
  296. state->m_Regs[MD1] = ((MainDiv >> 16) & 0x7F);
  297. state->m_Regs[MD2] = ((MainDiv >> 8) & 0xFF);
  298. state->m_Regs[MD3] = (MainDiv & 0xFF);
  299. return UpdateRegs(state, MPD, MD3);
  300. }
  301. static int CalcCalPLL(struct tda_state *state, u32 freq)
  302. {
  303. u8 PostDiv;
  304. u8 Div;
  305. u64 OscFreq;
  306. u32 CalDiv;
  307. if (!SearchMap3(m_Cal_PLL_Map, freq, &PostDiv, &Div))
  308. return -EINVAL;
  309. OscFreq = (u64)freq * (u64)Div;
  310. /* CalDiv = u32( OscFreq * 16384 / 16000000 ); */
  311. OscFreq *= (u64)16384;
  312. do_div(OscFreq, (u64)16000000);
  313. CalDiv = OscFreq;
  314. state->m_Regs[CPD] = PostDiv;
  315. state->m_Regs[CD1] = ((CalDiv >> 16) & 0xFF);
  316. state->m_Regs[CD2] = ((CalDiv >> 8) & 0xFF);
  317. state->m_Regs[CD3] = (CalDiv & 0xFF);
  318. return UpdateRegs(state, CPD, CD3);
  319. }
  320. static int CalibrateRF(struct tda_state *state,
  321. u8 RFBand, u32 freq, s32 *pCprog)
  322. {
  323. int status = 0;
  324. u8 Regs[NUM_REGS];
  325. do {
  326. u8 BP_Filter = 0;
  327. u8 GainTaper = 0;
  328. u8 RFC_K = 0;
  329. u8 RFC_M = 0;
  330. state->m_Regs[EP4] &= ~0x03; /* CAL_mode = 0 */
  331. status = UpdateReg(state, EP4);
  332. if (status < 0)
  333. break;
  334. state->m_Regs[EB18] |= 0x03; /* AGC1_Gain = 3 */
  335. status = UpdateReg(state, EB18);
  336. if (status < 0)
  337. break;
  338. /* Switching off LT (as datasheet says) causes calibration on C1 to fail */
  339. /* (Readout of Cprog is allways 255) */
  340. if (state->m_Regs[ID] != 0x83) /* C1: ID == 83, C2: ID == 84 */
  341. state->m_Regs[EP3] |= 0x40; /* SM_LT = 1 */
  342. if (!(SearchMap1(m_BP_Filter_Map, freq, &BP_Filter) &&
  343. SearchMap1(m_GainTaper_Map, freq, &GainTaper) &&
  344. SearchMap3(m_KM_Map, freq, &RFC_K, &RFC_M)))
  345. return -EINVAL;
  346. state->m_Regs[EP1] = (state->m_Regs[EP1] & ~0x07) | BP_Filter;
  347. state->m_Regs[EP2] = (RFBand << 5) | GainTaper;
  348. state->m_Regs[EB13] = (state->m_Regs[EB13] & ~0x7C) | (RFC_K << 4) | (RFC_M << 2);
  349. status = UpdateRegs(state, EP1, EP3);
  350. if (status < 0)
  351. break;
  352. status = UpdateReg(state, EB13);
  353. if (status < 0)
  354. break;
  355. state->m_Regs[EB4] |= 0x20; /* LO_ForceSrce = 1 */
  356. status = UpdateReg(state, EB4);
  357. if (status < 0)
  358. break;
  359. state->m_Regs[EB7] |= 0x20; /* CAL_ForceSrce = 1 */
  360. status = UpdateReg(state, EB7);
  361. if (status < 0)
  362. break;
  363. state->m_Regs[EB14] = 0; /* RFC_Cprog = 0 */
  364. status = UpdateReg(state, EB14);
  365. if (status < 0)
  366. break;
  367. state->m_Regs[EB20] &= ~0x20; /* ForceLock = 0; */
  368. status = UpdateReg(state, EB20);
  369. if (status < 0)
  370. break;
  371. state->m_Regs[EP4] |= 0x03; /* CAL_Mode = 3 */
  372. status = UpdateRegs(state, EP4, EP5);
  373. if (status < 0)
  374. break;
  375. status = CalcCalPLL(state, freq);
  376. if (status < 0)
  377. break;
  378. status = CalcMainPLL(state, freq + 1000000);
  379. if (status < 0)
  380. break;
  381. msleep(5);
  382. status = UpdateReg(state, EP2);
  383. if (status < 0)
  384. break;
  385. status = UpdateReg(state, EP1);
  386. if (status < 0)
  387. break;
  388. status = UpdateReg(state, EP2);
  389. if (status < 0)
  390. break;
  391. status = UpdateReg(state, EP1);
  392. if (status < 0)
  393. break;
  394. state->m_Regs[EB4] &= ~0x20; /* LO_ForceSrce = 0 */
  395. status = UpdateReg(state, EB4);
  396. if (status < 0)
  397. break;
  398. state->m_Regs[EB7] &= ~0x20; /* CAL_ForceSrce = 0 */
  399. status = UpdateReg(state, EB7);
  400. if (status < 0)
  401. break;
  402. msleep(10);
  403. state->m_Regs[EB20] |= 0x20; /* ForceLock = 1; */
  404. status = UpdateReg(state, EB20);
  405. if (status < 0)
  406. break;
  407. msleep(60);
  408. state->m_Regs[EP4] &= ~0x03; /* CAL_Mode = 0 */
  409. state->m_Regs[EP3] &= ~0x40; /* SM_LT = 0 */
  410. state->m_Regs[EB18] &= ~0x03; /* AGC1_Gain = 0 */
  411. status = UpdateReg(state, EB18);
  412. if (status < 0)
  413. break;
  414. status = UpdateRegs(state, EP3, EP4);
  415. if (status < 0)
  416. break;
  417. status = UpdateReg(state, EP1);
  418. if (status < 0)
  419. break;
  420. status = ReadExtented(state, Regs);
  421. if (status < 0)
  422. break;
  423. *pCprog = Regs[EB14];
  424. } while (0);
  425. return status;
  426. }
  427. static int RFTrackingFiltersInit(struct tda_state *state,
  428. u8 RFBand)
  429. {
  430. int status = 0;
  431. u32 RF1 = m_RF_Band_Map[RFBand].m_RF1_Default;
  432. u32 RF2 = m_RF_Band_Map[RFBand].m_RF2_Default;
  433. u32 RF3 = m_RF_Band_Map[RFBand].m_RF3_Default;
  434. bool bcal = false;
  435. s32 Cprog_cal1 = 0;
  436. s32 Cprog_table1 = 0;
  437. s32 Cprog_cal2 = 0;
  438. s32 Cprog_table2 = 0;
  439. s32 Cprog_cal3 = 0;
  440. s32 Cprog_table3 = 0;
  441. state->m_RF_A1[RFBand] = 0;
  442. state->m_RF_B1[RFBand] = 0;
  443. state->m_RF_A2[RFBand] = 0;
  444. state->m_RF_B2[RFBand] = 0;
  445. do {
  446. status = PowerScan(state, RFBand, RF1, &RF1, &bcal);
  447. if (status < 0)
  448. break;
  449. if (bcal) {
  450. status = CalibrateRF(state, RFBand, RF1, &Cprog_cal1);
  451. if (status < 0)
  452. break;
  453. }
  454. SearchMap2(m_RF_Cal_Map, RF1, &Cprog_table1);
  455. if (!bcal)
  456. Cprog_cal1 = Cprog_table1;
  457. state->m_RF_B1[RFBand] = Cprog_cal1 - Cprog_table1;
  458. /* state->m_RF_A1[RF_Band] = ???? */
  459. if (RF2 == 0)
  460. break;
  461. status = PowerScan(state, RFBand, RF2, &RF2, &bcal);
  462. if (status < 0)
  463. break;
  464. if (bcal) {
  465. status = CalibrateRF(state, RFBand, RF2, &Cprog_cal2);
  466. if (status < 0)
  467. break;
  468. }
  469. SearchMap2(m_RF_Cal_Map, RF2, &Cprog_table2);
  470. if (!bcal)
  471. Cprog_cal2 = Cprog_table2;
  472. state->m_RF_A1[RFBand] =
  473. (Cprog_cal2 - Cprog_table2 - Cprog_cal1 + Cprog_table1) /
  474. ((s32)(RF2) - (s32)(RF1));
  475. if (RF3 == 0)
  476. break;
  477. status = PowerScan(state, RFBand, RF3, &RF3, &bcal);
  478. if (status < 0)
  479. break;
  480. if (bcal) {
  481. status = CalibrateRF(state, RFBand, RF3, &Cprog_cal3);
  482. if (status < 0)
  483. break;
  484. }
  485. SearchMap2(m_RF_Cal_Map, RF3, &Cprog_table3);
  486. if (!bcal)
  487. Cprog_cal3 = Cprog_table3;
  488. state->m_RF_A2[RFBand] = (Cprog_cal3 - Cprog_table3 - Cprog_cal2 + Cprog_table2) / ((s32)(RF3) - (s32)(RF2));
  489. state->m_RF_B2[RFBand] = Cprog_cal2 - Cprog_table2;
  490. } while (0);
  491. state->m_RF1[RFBand] = RF1;
  492. state->m_RF2[RFBand] = RF2;
  493. state->m_RF3[RFBand] = RF3;
  494. #if 0
  495. printk(KERN_ERR "tda18271c2dd: %s %d RF1 = %d A1 = %d B1 = %d RF2 = %d A2 = %d B2 = %d RF3 = %d\n", __func__,
  496. RFBand, RF1, state->m_RF_A1[RFBand], state->m_RF_B1[RFBand], RF2,
  497. state->m_RF_A2[RFBand], state->m_RF_B2[RFBand], RF3);
  498. #endif
  499. return status;
  500. }
  501. static int PowerScan(struct tda_state *state,
  502. u8 RFBand, u32 RF_in, u32 *pRF_Out, bool *pbcal)
  503. {
  504. int status = 0;
  505. do {
  506. u8 Gain_Taper = 0;
  507. s32 RFC_Cprog = 0;
  508. u8 CID_Target = 0;
  509. u8 CountLimit = 0;
  510. u32 freq_MainPLL;
  511. u8 Regs[NUM_REGS];
  512. u8 CID_Gain;
  513. s32 Count = 0;
  514. int sign = 1;
  515. bool wait = false;
  516. if (!(SearchMap2(m_RF_Cal_Map, RF_in, &RFC_Cprog) &&
  517. SearchMap1(m_GainTaper_Map, RF_in, &Gain_Taper) &&
  518. SearchMap3(m_CID_Target_Map, RF_in, &CID_Target, &CountLimit))) {
  519. printk(KERN_ERR "tda18271c2dd: %s Search map failed\n", __func__);
  520. return -EINVAL;
  521. }
  522. state->m_Regs[EP2] = (RFBand << 5) | Gain_Taper;
  523. state->m_Regs[EB14] = (RFC_Cprog);
  524. status = UpdateReg(state, EP2);
  525. if (status < 0)
  526. break;
  527. status = UpdateReg(state, EB14);
  528. if (status < 0)
  529. break;
  530. freq_MainPLL = RF_in + 1000000;
  531. status = CalcMainPLL(state, freq_MainPLL);
  532. if (status < 0)
  533. break;
  534. msleep(5);
  535. state->m_Regs[EP4] = (state->m_Regs[EP4] & ~0x03) | 1; /* CAL_mode = 1 */
  536. status = UpdateReg(state, EP4);
  537. if (status < 0)
  538. break;
  539. status = UpdateReg(state, EP2); /* Launch power measurement */
  540. if (status < 0)
  541. break;
  542. status = ReadExtented(state, Regs);
  543. if (status < 0)
  544. break;
  545. CID_Gain = Regs[EB10] & 0x3F;
  546. state->m_Regs[ID] = Regs[ID]; /* Chip version, (needed for C1 workarround in CalibrateRF) */
  547. *pRF_Out = RF_in;
  548. while (CID_Gain < CID_Target) {
  549. freq_MainPLL = RF_in + sign * Count + 1000000;
  550. status = CalcMainPLL(state, freq_MainPLL);
  551. if (status < 0)
  552. break;
  553. msleep(wait ? 5 : 1);
  554. wait = false;
  555. status = UpdateReg(state, EP2); /* Launch power measurement */
  556. if (status < 0)
  557. break;
  558. status = ReadExtented(state, Regs);
  559. if (status < 0)
  560. break;
  561. CID_Gain = Regs[EB10] & 0x3F;
  562. Count += 200000;
  563. if (Count < CountLimit * 100000)
  564. continue;
  565. if (sign < 0)
  566. break;
  567. sign = -sign;
  568. Count = 200000;
  569. wait = true;
  570. }
  571. if (status < 0)
  572. break;
  573. if (CID_Gain >= CID_Target) {
  574. *pbcal = true;
  575. *pRF_Out = freq_MainPLL - 1000000;
  576. } else
  577. *pbcal = false;
  578. } while (0);
  579. return status;
  580. }
  581. static int PowerScanInit(struct tda_state *state)
  582. {
  583. int status = 0;
  584. do {
  585. state->m_Regs[EP3] = (state->m_Regs[EP3] & ~0x1F) | 0x12;
  586. state->m_Regs[EP4] = (state->m_Regs[EP4] & ~0x1F); /* If level = 0, Cal mode = 0 */
  587. status = UpdateRegs(state, EP3, EP4);
  588. if (status < 0)
  589. break;
  590. state->m_Regs[EB18] = (state->m_Regs[EB18] & ~0x03); /* AGC 1 Gain = 0 */
  591. status = UpdateReg(state, EB18);
  592. if (status < 0)
  593. break;
  594. state->m_Regs[EB21] = (state->m_Regs[EB21] & ~0x03); /* AGC 2 Gain = 0 (Datasheet = 3) */
  595. state->m_Regs[EB23] = (state->m_Regs[EB23] | 0x06); /* ForceLP_Fc2_En = 1, LPFc[2] = 1 */
  596. status = UpdateRegs(state, EB21, EB23);
  597. if (status < 0)
  598. break;
  599. } while (0);
  600. return status;
  601. }
  602. static int CalcRFFilterCurve(struct tda_state *state)
  603. {
  604. int status = 0;
  605. do {
  606. msleep(200); /* Temperature stabilisation */
  607. status = PowerScanInit(state);
  608. if (status < 0)
  609. break;
  610. status = RFTrackingFiltersInit(state, 0);
  611. if (status < 0)
  612. break;
  613. status = RFTrackingFiltersInit(state, 1);
  614. if (status < 0)
  615. break;
  616. status = RFTrackingFiltersInit(state, 2);
  617. if (status < 0)
  618. break;
  619. status = RFTrackingFiltersInit(state, 3);
  620. if (status < 0)
  621. break;
  622. status = RFTrackingFiltersInit(state, 4);
  623. if (status < 0)
  624. break;
  625. status = RFTrackingFiltersInit(state, 5);
  626. if (status < 0)
  627. break;
  628. status = RFTrackingFiltersInit(state, 6);
  629. if (status < 0)
  630. break;
  631. status = ThermometerRead(state, &state->m_TMValue_RFCal); /* also switches off Cal mode !!! */
  632. if (status < 0)
  633. break;
  634. } while (0);
  635. return status;
  636. }
  637. static int FixedContentsI2CUpdate(struct tda_state *state)
  638. {
  639. static u8 InitRegs[] = {
  640. 0x08, 0x80, 0xC6,
  641. 0xDF, 0x16, 0x60, 0x80,
  642. 0x80, 0x00, 0x00, 0x00,
  643. 0x00, 0x00, 0x00, 0x00,
  644. 0xFC, 0x01, 0x84, 0x41,
  645. 0x01, 0x84, 0x40, 0x07,
  646. 0x00, 0x00, 0x96, 0x3F,
  647. 0xC1, 0x00, 0x8F, 0x00,
  648. 0x00, 0x8C, 0x00, 0x20,
  649. 0xB3, 0x48, 0xB0,
  650. };
  651. int status = 0;
  652. memcpy(&state->m_Regs[TM], InitRegs, EB23 - TM + 1);
  653. do {
  654. status = UpdateRegs(state, TM, EB23);
  655. if (status < 0)
  656. break;
  657. /* AGC1 gain setup */
  658. state->m_Regs[EB17] = 0x00;
  659. status = UpdateReg(state, EB17);
  660. if (status < 0)
  661. break;
  662. state->m_Regs[EB17] = 0x03;
  663. status = UpdateReg(state, EB17);
  664. if (status < 0)
  665. break;
  666. state->m_Regs[EB17] = 0x43;
  667. status = UpdateReg(state, EB17);
  668. if (status < 0)
  669. break;
  670. state->m_Regs[EB17] = 0x4C;
  671. status = UpdateReg(state, EB17);
  672. if (status < 0)
  673. break;
  674. /* IRC Cal Low band */
  675. state->m_Regs[EP3] = 0x1F;
  676. state->m_Regs[EP4] = 0x66;
  677. state->m_Regs[EP5] = 0x81;
  678. state->m_Regs[CPD] = 0xCC;
  679. state->m_Regs[CD1] = 0x6C;
  680. state->m_Regs[CD2] = 0x00;
  681. state->m_Regs[CD3] = 0x00;
  682. state->m_Regs[MPD] = 0xC5;
  683. state->m_Regs[MD1] = 0x77;
  684. state->m_Regs[MD2] = 0x08;
  685. state->m_Regs[MD3] = 0x00;
  686. status = UpdateRegs(state, EP2, MD3); /* diff between sw and datasheet (ep3-md3) */
  687. if (status < 0)
  688. break;
  689. #if 0
  690. state->m_Regs[EB4] = 0x61; /* missing in sw */
  691. status = UpdateReg(state, EB4);
  692. if (status < 0)
  693. break;
  694. msleep(1);
  695. state->m_Regs[EB4] = 0x41;
  696. status = UpdateReg(state, EB4);
  697. if (status < 0)
  698. break;
  699. #endif
  700. msleep(5);
  701. status = UpdateReg(state, EP1);
  702. if (status < 0)
  703. break;
  704. msleep(5);
  705. state->m_Regs[EP5] = 0x85;
  706. state->m_Regs[CPD] = 0xCB;
  707. state->m_Regs[CD1] = 0x66;
  708. state->m_Regs[CD2] = 0x70;
  709. status = UpdateRegs(state, EP3, CD3);
  710. if (status < 0)
  711. break;
  712. msleep(5);
  713. status = UpdateReg(state, EP2);
  714. if (status < 0)
  715. break;
  716. msleep(30);
  717. /* IRC Cal mid band */
  718. state->m_Regs[EP5] = 0x82;
  719. state->m_Regs[CPD] = 0xA8;
  720. state->m_Regs[CD2] = 0x00;
  721. state->m_Regs[MPD] = 0xA1; /* Datasheet = 0xA9 */
  722. state->m_Regs[MD1] = 0x73;
  723. state->m_Regs[MD2] = 0x1A;
  724. status = UpdateRegs(state, EP3, MD3);
  725. if (status < 0)
  726. break;
  727. msleep(5);
  728. status = UpdateReg(state, EP1);
  729. if (status < 0)
  730. break;
  731. msleep(5);
  732. state->m_Regs[EP5] = 0x86;
  733. state->m_Regs[CPD] = 0xA8;
  734. state->m_Regs[CD1] = 0x66;
  735. state->m_Regs[CD2] = 0xA0;
  736. status = UpdateRegs(state, EP3, CD3);
  737. if (status < 0)
  738. break;
  739. msleep(5);
  740. status = UpdateReg(state, EP2);
  741. if (status < 0)
  742. break;
  743. msleep(30);
  744. /* IRC Cal high band */
  745. state->m_Regs[EP5] = 0x83;
  746. state->m_Regs[CPD] = 0x98;
  747. state->m_Regs[CD1] = 0x65;
  748. state->m_Regs[CD2] = 0x00;
  749. state->m_Regs[MPD] = 0x91; /* Datasheet = 0x91 */
  750. state->m_Regs[MD1] = 0x71;
  751. state->m_Regs[MD2] = 0xCD;
  752. status = UpdateRegs(state, EP3, MD3);
  753. if (status < 0)
  754. break;
  755. msleep(5);
  756. status = UpdateReg(state, EP1);
  757. if (status < 0)
  758. break;
  759. msleep(5);
  760. state->m_Regs[EP5] = 0x87;
  761. state->m_Regs[CD1] = 0x65;
  762. state->m_Regs[CD2] = 0x50;
  763. status = UpdateRegs(state, EP3, CD3);
  764. if (status < 0)
  765. break;
  766. msleep(5);
  767. status = UpdateReg(state, EP2);
  768. if (status < 0)
  769. break;
  770. msleep(30);
  771. /* Back to normal */
  772. state->m_Regs[EP4] = 0x64;
  773. status = UpdateReg(state, EP4);
  774. if (status < 0)
  775. break;
  776. status = UpdateReg(state, EP1);
  777. if (status < 0)
  778. break;
  779. } while (0);
  780. return status;
  781. }
  782. static int InitCal(struct tda_state *state)
  783. {
  784. int status = 0;
  785. do {
  786. status = FixedContentsI2CUpdate(state);
  787. if (status < 0)
  788. break;
  789. status = CalcRFFilterCurve(state);
  790. if (status < 0)
  791. break;
  792. status = StandBy(state);
  793. if (status < 0)
  794. break;
  795. /* m_bInitDone = true; */
  796. } while (0);
  797. return status;
  798. };
  799. static int RFTrackingFiltersCorrection(struct tda_state *state,
  800. u32 Frequency)
  801. {
  802. int status = 0;
  803. s32 Cprog_table;
  804. u8 RFBand;
  805. u8 dCoverdT;
  806. if (!SearchMap2(m_RF_Cal_Map, Frequency, &Cprog_table) ||
  807. !SearchMap4(m_RF_Band_Map, Frequency, &RFBand) ||
  808. !SearchMap1(m_RF_Cal_DC_Over_DT_Map, Frequency, &dCoverdT))
  809. return -EINVAL;
  810. do {
  811. u8 TMValue_Current;
  812. u32 RF1 = state->m_RF1[RFBand];
  813. u32 RF2 = state->m_RF1[RFBand];
  814. u32 RF3 = state->m_RF1[RFBand];
  815. s32 RF_A1 = state->m_RF_A1[RFBand];
  816. s32 RF_B1 = state->m_RF_B1[RFBand];
  817. s32 RF_A2 = state->m_RF_A2[RFBand];
  818. s32 RF_B2 = state->m_RF_B2[RFBand];
  819. s32 Capprox = 0;
  820. int TComp;
  821. state->m_Regs[EP3] &= ~0xE0; /* Power up */
  822. status = UpdateReg(state, EP3);
  823. if (status < 0)
  824. break;
  825. status = ThermometerRead(state, &TMValue_Current);
  826. if (status < 0)
  827. break;
  828. if (RF3 == 0 || Frequency < RF2)
  829. Capprox = RF_A1 * ((s32)(Frequency) - (s32)(RF1)) + RF_B1 + Cprog_table;
  830. else
  831. Capprox = RF_A2 * ((s32)(Frequency) - (s32)(RF2)) + RF_B2 + Cprog_table;
  832. TComp = (int)(dCoverdT) * ((int)(TMValue_Current) - (int)(state->m_TMValue_RFCal))/1000;
  833. Capprox += TComp;
  834. if (Capprox < 0)
  835. Capprox = 0;
  836. else if (Capprox > 255)
  837. Capprox = 255;
  838. /* TODO Temperature compensation. There is defenitely a scale factor */
  839. /* missing in the datasheet, so leave it out for now. */
  840. state->m_Regs[EB14] = Capprox;
  841. status = UpdateReg(state, EB14);
  842. if (status < 0)
  843. break;
  844. } while (0);
  845. return status;
  846. }
  847. static int ChannelConfiguration(struct tda_state *state,
  848. u32 Frequency, int Standard)
  849. {
  850. s32 IntermediateFrequency = m_StandardTable[Standard].m_IFFrequency;
  851. int status = 0;
  852. u8 BP_Filter = 0;
  853. u8 RF_Band = 0;
  854. u8 GainTaper = 0;
  855. u8 IR_Meas = 0;
  856. state->IF = IntermediateFrequency;
  857. /* printk("tda18271c2dd: %s Freq = %d Standard = %d IF = %d\n", __func__, Frequency, Standard, IntermediateFrequency); */
  858. /* get values from tables */
  859. if (!(SearchMap1(m_BP_Filter_Map, Frequency, &BP_Filter) &&
  860. SearchMap1(m_GainTaper_Map, Frequency, &GainTaper) &&
  861. SearchMap1(m_IR_Meas_Map, Frequency, &IR_Meas) &&
  862. SearchMap4(m_RF_Band_Map, Frequency, &RF_Band))) {
  863. printk(KERN_ERR "tda18271c2dd: %s SearchMap failed\n", __func__);
  864. return -EINVAL;
  865. }
  866. do {
  867. state->m_Regs[EP3] = (state->m_Regs[EP3] & ~0x1F) | m_StandardTable[Standard].m_EP3_4_0;
  868. state->m_Regs[EP3] &= ~0x04; /* switch RFAGC to high speed mode */
  869. /* m_EP4 default for XToutOn, CAL_Mode (0) */
  870. state->m_Regs[EP4] = state->m_EP4 | ((Standard > HF_AnalogMax) ? state->m_IFLevelDigital : state->m_IFLevelAnalog);
  871. /* state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDigital; */
  872. if (Standard <= HF_AnalogMax)
  873. state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelAnalog;
  874. else if (Standard <= HF_ATSC)
  875. state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDVBT;
  876. else if (Standard <= HF_DVBC)
  877. state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDVBC;
  878. else
  879. state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDigital;
  880. if ((Standard == HF_FM_Radio) && state->m_bFMInput)
  881. state->m_Regs[EP4] |= 0x80;
  882. state->m_Regs[MPD] &= ~0x80;
  883. if (Standard > HF_AnalogMax)
  884. state->m_Regs[MPD] |= 0x80; /* Add IF_notch for digital */
  885. state->m_Regs[EB22] = m_StandardTable[Standard].m_EB22;
  886. /* Note: This is missing from flowchart in TDA18271 specification ( 1.5 MHz cutoff for FM ) */
  887. if (Standard == HF_FM_Radio)
  888. state->m_Regs[EB23] |= 0x06; /* ForceLP_Fc2_En = 1, LPFc[2] = 1 */
  889. else
  890. state->m_Regs[EB23] &= ~0x06; /* ForceLP_Fc2_En = 0, LPFc[2] = 0 */
  891. status = UpdateRegs(state, EB22, EB23);
  892. if (status < 0)
  893. break;
  894. state->m_Regs[EP1] = (state->m_Regs[EP1] & ~0x07) | 0x40 | BP_Filter; /* Dis_Power_level = 1, Filter */
  895. state->m_Regs[EP5] = (state->m_Regs[EP5] & ~0x07) | IR_Meas;
  896. state->m_Regs[EP2] = (RF_Band << 5) | GainTaper;
  897. state->m_Regs[EB1] = (state->m_Regs[EB1] & ~0x07) |
  898. (state->m_bMaster ? 0x04 : 0x00); /* CALVCO_FortLOn = MS */
  899. /* AGC1_always_master = 0 */
  900. /* AGC_firstn = 0 */
  901. status = UpdateReg(state, EB1);
  902. if (status < 0)
  903. break;
  904. if (state->m_bMaster) {
  905. status = CalcMainPLL(state, Frequency + IntermediateFrequency);
  906. if (status < 0)
  907. break;
  908. status = UpdateRegs(state, TM, EP5);
  909. if (status < 0)
  910. break;
  911. state->m_Regs[EB4] |= 0x20; /* LO_forceSrce = 1 */
  912. status = UpdateReg(state, EB4);
  913. if (status < 0)
  914. break;
  915. msleep(1);
  916. state->m_Regs[EB4] &= ~0x20; /* LO_forceSrce = 0 */
  917. status = UpdateReg(state, EB4);
  918. if (status < 0)
  919. break;
  920. } else {
  921. u8 PostDiv = 0;
  922. u8 Div;
  923. status = CalcCalPLL(state, Frequency + IntermediateFrequency);
  924. if (status < 0)
  925. break;
  926. SearchMap3(m_Cal_PLL_Map, Frequency + IntermediateFrequency, &PostDiv, &Div);
  927. state->m_Regs[MPD] = (state->m_Regs[MPD] & ~0x7F) | (PostDiv & 0x77);
  928. status = UpdateReg(state, MPD);
  929. if (status < 0)
  930. break;
  931. status = UpdateRegs(state, TM, EP5);
  932. if (status < 0)
  933. break;
  934. state->m_Regs[EB7] |= 0x20; /* CAL_forceSrce = 1 */
  935. status = UpdateReg(state, EB7);
  936. if (status < 0)
  937. break;
  938. msleep(1);
  939. state->m_Regs[EB7] &= ~0x20; /* CAL_forceSrce = 0 */
  940. status = UpdateReg(state, EB7);
  941. if (status < 0)
  942. break;
  943. }
  944. msleep(20);
  945. if (Standard != HF_FM_Radio)
  946. state->m_Regs[EP3] |= 0x04; /* RFAGC to normal mode */
  947. status = UpdateReg(state, EP3);
  948. if (status < 0)
  949. break;
  950. } while (0);
  951. return status;
  952. }
  953. static int sleep(struct dvb_frontend *fe)
  954. {
  955. struct tda_state *state = fe->tuner_priv;
  956. StandBy(state);
  957. return 0;
  958. }
  959. static int init(struct dvb_frontend *fe)
  960. {
  961. return 0;
  962. }
  963. static void release(struct dvb_frontend *fe)
  964. {
  965. kfree(fe->tuner_priv);
  966. fe->tuner_priv = NULL;
  967. }
  968. static int set_params(struct dvb_frontend *fe)
  969. {
  970. struct tda_state *state = fe->tuner_priv;
  971. int status = 0;
  972. int Standard;
  973. u32 bw = fe->dtv_property_cache.bandwidth_hz;
  974. u32 delsys = fe->dtv_property_cache.delivery_system;
  975. state->m_Frequency = fe->dtv_property_cache.frequency;
  976. switch (delsys) {
  977. case SYS_DVBT:
  978. case SYS_DVBT2:
  979. switch (bw) {
  980. case 6000000:
  981. Standard = HF_DVBT_6MHZ;
  982. break;
  983. case 7000000:
  984. Standard = HF_DVBT_7MHZ;
  985. break;
  986. case 8000000:
  987. Standard = HF_DVBT_8MHZ;
  988. break;
  989. default:
  990. return -EINVAL;
  991. }
  992. break;
  993. case SYS_DVBC_ANNEX_A:
  994. case SYS_DVBC_ANNEX_C:
  995. if (bw <= 6000000)
  996. Standard = HF_DVBC_6MHZ;
  997. else if (bw <= 7000000)
  998. Standard = HF_DVBC_7MHZ;
  999. else
  1000. Standard = HF_DVBC_8MHZ;
  1001. break;
  1002. default:
  1003. return -EINVAL;
  1004. }
  1005. do {
  1006. status = RFTrackingFiltersCorrection(state, state->m_Frequency);
  1007. if (status < 0)
  1008. break;
  1009. status = ChannelConfiguration(state, state->m_Frequency,
  1010. Standard);
  1011. if (status < 0)
  1012. break;
  1013. msleep(state->m_SettlingTime); /* Allow AGC's to settle down */
  1014. } while (0);
  1015. return status;
  1016. }
  1017. #if 0
  1018. static int GetSignalStrength(s32 *pSignalStrength, u32 RFAgc, u32 IFAgc)
  1019. {
  1020. if (IFAgc < 500) {
  1021. /* Scale this from 0 to 50000 */
  1022. *pSignalStrength = IFAgc * 100;
  1023. } else {
  1024. /* Scale range 500-1500 to 50000-80000 */
  1025. *pSignalStrength = 50000 + (IFAgc - 500) * 30;
  1026. }
  1027. return 0;
  1028. }
  1029. #endif
  1030. static int get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
  1031. {
  1032. struct tda_state *state = fe->tuner_priv;
  1033. *frequency = state->IF;
  1034. return 0;
  1035. }
  1036. static int get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
  1037. {
  1038. /* struct tda_state *state = fe->tuner_priv; */
  1039. /* *bandwidth = priv->bandwidth; */
  1040. return 0;
  1041. }
  1042. static const struct dvb_tuner_ops tuner_ops = {
  1043. .info = {
  1044. .name = "NXP TDA18271C2D",
  1045. .frequency_min_hz = 47125 * kHz,
  1046. .frequency_max_hz = 865 * MHz,
  1047. .frequency_step_hz = 62500
  1048. },
  1049. .init = init,
  1050. .sleep = sleep,
  1051. .set_params = set_params,
  1052. .release = release,
  1053. .get_if_frequency = get_if_frequency,
  1054. .get_bandwidth = get_bandwidth,
  1055. };
  1056. struct dvb_frontend *tda18271c2dd_attach(struct dvb_frontend *fe,
  1057. struct i2c_adapter *i2c, u8 adr)
  1058. {
  1059. struct tda_state *state;
  1060. state = kzalloc(sizeof(struct tda_state), GFP_KERNEL);
  1061. if (!state)
  1062. return NULL;
  1063. fe->tuner_priv = state;
  1064. state->adr = adr;
  1065. state->i2c = i2c;
  1066. memcpy(&fe->ops.tuner_ops, &tuner_ops, sizeof(struct dvb_tuner_ops));
  1067. reset(state);
  1068. InitCal(state);
  1069. return fe;
  1070. }
  1071. EXPORT_SYMBOL_GPL(tda18271c2dd_attach);
  1072. MODULE_DESCRIPTION("TDA18271C2 driver");
  1073. MODULE_AUTHOR("DD");
  1074. MODULE_LICENSE("GPL");