cxd2099.c 14 KB

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  1. /*
  2. * cxd2099.c: Driver for the Sony CXD2099AR Common Interface Controller
  3. *
  4. * Copyright (C) 2010-2013 Digital Devices GmbH
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * version 2 only, as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #include <linux/slab.h>
  16. #include <linux/kernel.h>
  17. #include <linux/module.h>
  18. #include <linux/i2c.h>
  19. #include <linux/regmap.h>
  20. #include <linux/wait.h>
  21. #include <linux/delay.h>
  22. #include <linux/mutex.h>
  23. #include <linux/io.h>
  24. #include "cxd2099.h"
  25. static int buffermode;
  26. module_param(buffermode, int, 0444);
  27. MODULE_PARM_DESC(buffermode, "Enable CXD2099AR buffer mode (default: disabled)");
  28. static int read_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount);
  29. struct cxd {
  30. struct dvb_ca_en50221 en;
  31. struct cxd2099_cfg cfg;
  32. struct i2c_client *client;
  33. struct regmap *regmap;
  34. u8 regs[0x23];
  35. u8 lastaddress;
  36. u8 clk_reg_f;
  37. u8 clk_reg_b;
  38. int mode;
  39. int ready;
  40. int dr;
  41. int write_busy;
  42. int slot_stat;
  43. u8 amem[1024];
  44. int amem_read;
  45. int cammode;
  46. struct mutex lock; /* device access lock */
  47. u8 rbuf[1028];
  48. u8 wbuf[1028];
  49. };
  50. static int read_block(struct cxd *ci, u8 adr, u8 *data, u16 n)
  51. {
  52. int status = 0;
  53. if (ci->lastaddress != adr)
  54. status = regmap_write(ci->regmap, 0, adr);
  55. if (!status) {
  56. ci->lastaddress = adr;
  57. while (n) {
  58. int len = n;
  59. if (ci->cfg.max_i2c && len > ci->cfg.max_i2c)
  60. len = ci->cfg.max_i2c;
  61. status = regmap_raw_read(ci->regmap, 1, data, len);
  62. if (status)
  63. return status;
  64. data += len;
  65. n -= len;
  66. }
  67. }
  68. return status;
  69. }
  70. static int read_reg(struct cxd *ci, u8 reg, u8 *val)
  71. {
  72. return read_block(ci, reg, val, 1);
  73. }
  74. static int read_pccard(struct cxd *ci, u16 address, u8 *data, u8 n)
  75. {
  76. int status;
  77. u8 addr[2] = {address & 0xff, address >> 8};
  78. status = regmap_raw_write(ci->regmap, 2, addr, 2);
  79. if (!status)
  80. status = regmap_raw_read(ci->regmap, 3, data, n);
  81. return status;
  82. }
  83. static int write_pccard(struct cxd *ci, u16 address, u8 *data, u8 n)
  84. {
  85. int status;
  86. u8 addr[2] = {address & 0xff, address >> 8};
  87. status = regmap_raw_write(ci->regmap, 2, addr, 2);
  88. if (!status) {
  89. u8 buf[256];
  90. memcpy(buf, data, n);
  91. status = regmap_raw_write(ci->regmap, 3, buf, n);
  92. }
  93. return status;
  94. }
  95. static int read_io(struct cxd *ci, u16 address, unsigned int *val)
  96. {
  97. int status;
  98. u8 addr[2] = {address & 0xff, address >> 8};
  99. status = regmap_raw_write(ci->regmap, 2, addr, 2);
  100. if (!status)
  101. status = regmap_read(ci->regmap, 3, val);
  102. return status;
  103. }
  104. static int write_io(struct cxd *ci, u16 address, u8 val)
  105. {
  106. int status;
  107. u8 addr[2] = {address & 0xff, address >> 8};
  108. status = regmap_raw_write(ci->regmap, 2, addr, 2);
  109. if (!status)
  110. status = regmap_write(ci->regmap, 3, val);
  111. return status;
  112. }
  113. static int write_regm(struct cxd *ci, u8 reg, u8 val, u8 mask)
  114. {
  115. int status = 0;
  116. unsigned int regval;
  117. if (ci->lastaddress != reg)
  118. status = regmap_write(ci->regmap, 0, reg);
  119. if (!status && reg >= 6 && reg <= 8 && mask != 0xff) {
  120. status = regmap_read(ci->regmap, 1, &regval);
  121. ci->regs[reg] = regval;
  122. }
  123. ci->lastaddress = reg;
  124. ci->regs[reg] = (ci->regs[reg] & (~mask)) | val;
  125. if (!status)
  126. status = regmap_write(ci->regmap, 1, ci->regs[reg]);
  127. if (reg == 0x20)
  128. ci->regs[reg] &= 0x7f;
  129. return status;
  130. }
  131. static int write_reg(struct cxd *ci, u8 reg, u8 val)
  132. {
  133. return write_regm(ci, reg, val, 0xff);
  134. }
  135. static int write_block(struct cxd *ci, u8 adr, u8 *data, u16 n)
  136. {
  137. int status = 0;
  138. u8 *buf = ci->wbuf;
  139. if (ci->lastaddress != adr)
  140. status = regmap_write(ci->regmap, 0, adr);
  141. if (status)
  142. return status;
  143. ci->lastaddress = adr;
  144. while (n) {
  145. int len = n;
  146. if (ci->cfg.max_i2c && (len + 1 > ci->cfg.max_i2c))
  147. len = ci->cfg.max_i2c - 1;
  148. memcpy(buf, data, len);
  149. status = regmap_raw_write(ci->regmap, 1, buf, len);
  150. if (status)
  151. return status;
  152. n -= len;
  153. data += len;
  154. }
  155. return status;
  156. }
  157. static void set_mode(struct cxd *ci, int mode)
  158. {
  159. if (mode == ci->mode)
  160. return;
  161. switch (mode) {
  162. case 0x00: /* IO mem */
  163. write_regm(ci, 0x06, 0x00, 0x07);
  164. break;
  165. case 0x01: /* ATT mem */
  166. write_regm(ci, 0x06, 0x02, 0x07);
  167. break;
  168. default:
  169. break;
  170. }
  171. ci->mode = mode;
  172. }
  173. static void cam_mode(struct cxd *ci, int mode)
  174. {
  175. u8 dummy;
  176. if (mode == ci->cammode)
  177. return;
  178. switch (mode) {
  179. case 0x00:
  180. write_regm(ci, 0x20, 0x80, 0x80);
  181. break;
  182. case 0x01:
  183. if (!ci->en.read_data)
  184. return;
  185. ci->write_busy = 0;
  186. dev_info(&ci->client->dev, "enable cam buffer mode\n");
  187. write_reg(ci, 0x0d, 0x00);
  188. write_reg(ci, 0x0e, 0x01);
  189. write_regm(ci, 0x08, 0x40, 0x40);
  190. read_reg(ci, 0x12, &dummy);
  191. write_regm(ci, 0x08, 0x80, 0x80);
  192. break;
  193. default:
  194. break;
  195. }
  196. ci->cammode = mode;
  197. }
  198. static int init(struct cxd *ci)
  199. {
  200. int status;
  201. mutex_lock(&ci->lock);
  202. ci->mode = -1;
  203. do {
  204. status = write_reg(ci, 0x00, 0x00);
  205. if (status < 0)
  206. break;
  207. status = write_reg(ci, 0x01, 0x00);
  208. if (status < 0)
  209. break;
  210. status = write_reg(ci, 0x02, 0x10);
  211. if (status < 0)
  212. break;
  213. status = write_reg(ci, 0x03, 0x00);
  214. if (status < 0)
  215. break;
  216. status = write_reg(ci, 0x05, 0xFF);
  217. if (status < 0)
  218. break;
  219. status = write_reg(ci, 0x06, 0x1F);
  220. if (status < 0)
  221. break;
  222. status = write_reg(ci, 0x07, 0x1F);
  223. if (status < 0)
  224. break;
  225. status = write_reg(ci, 0x08, 0x28);
  226. if (status < 0)
  227. break;
  228. status = write_reg(ci, 0x14, 0x20);
  229. if (status < 0)
  230. break;
  231. /* TOSTRT = 8, Mode B (gated clock), falling Edge,
  232. * Serial, POL=HIGH, MSB
  233. */
  234. status = write_reg(ci, 0x0A, 0xA7);
  235. if (status < 0)
  236. break;
  237. status = write_reg(ci, 0x0B, 0x33);
  238. if (status < 0)
  239. break;
  240. status = write_reg(ci, 0x0C, 0x33);
  241. if (status < 0)
  242. break;
  243. status = write_regm(ci, 0x14, 0x00, 0x0F);
  244. if (status < 0)
  245. break;
  246. status = write_reg(ci, 0x15, ci->clk_reg_b);
  247. if (status < 0)
  248. break;
  249. status = write_regm(ci, 0x16, 0x00, 0x0F);
  250. if (status < 0)
  251. break;
  252. status = write_reg(ci, 0x17, ci->clk_reg_f);
  253. if (status < 0)
  254. break;
  255. if (ci->cfg.clock_mode == 2) {
  256. /* bitrate*2^13/ 72000 */
  257. u32 reg = ((ci->cfg.bitrate << 13) + 71999) / 72000;
  258. if (ci->cfg.polarity) {
  259. status = write_reg(ci, 0x09, 0x6f);
  260. if (status < 0)
  261. break;
  262. } else {
  263. status = write_reg(ci, 0x09, 0x6d);
  264. if (status < 0)
  265. break;
  266. }
  267. status = write_reg(ci, 0x20, 0x08);
  268. if (status < 0)
  269. break;
  270. status = write_reg(ci, 0x21, (reg >> 8) & 0xff);
  271. if (status < 0)
  272. break;
  273. status = write_reg(ci, 0x22, reg & 0xff);
  274. if (status < 0)
  275. break;
  276. } else if (ci->cfg.clock_mode == 1) {
  277. if (ci->cfg.polarity) {
  278. status = write_reg(ci, 0x09, 0x6f); /* D */
  279. if (status < 0)
  280. break;
  281. } else {
  282. status = write_reg(ci, 0x09, 0x6d);
  283. if (status < 0)
  284. break;
  285. }
  286. status = write_reg(ci, 0x20, 0x68);
  287. if (status < 0)
  288. break;
  289. status = write_reg(ci, 0x21, 0x00);
  290. if (status < 0)
  291. break;
  292. status = write_reg(ci, 0x22, 0x02);
  293. if (status < 0)
  294. break;
  295. } else {
  296. if (ci->cfg.polarity) {
  297. status = write_reg(ci, 0x09, 0x4f); /* C */
  298. if (status < 0)
  299. break;
  300. } else {
  301. status = write_reg(ci, 0x09, 0x4d);
  302. if (status < 0)
  303. break;
  304. }
  305. status = write_reg(ci, 0x20, 0x28);
  306. if (status < 0)
  307. break;
  308. status = write_reg(ci, 0x21, 0x00);
  309. if (status < 0)
  310. break;
  311. status = write_reg(ci, 0x22, 0x07);
  312. if (status < 0)
  313. break;
  314. }
  315. status = write_regm(ci, 0x20, 0x80, 0x80);
  316. if (status < 0)
  317. break;
  318. status = write_regm(ci, 0x03, 0x02, 0x02);
  319. if (status < 0)
  320. break;
  321. status = write_reg(ci, 0x01, 0x04);
  322. if (status < 0)
  323. break;
  324. status = write_reg(ci, 0x00, 0x31);
  325. if (status < 0)
  326. break;
  327. /* Put TS in bypass */
  328. status = write_regm(ci, 0x09, 0x08, 0x08);
  329. if (status < 0)
  330. break;
  331. ci->cammode = -1;
  332. cam_mode(ci, 0);
  333. } while (0);
  334. mutex_unlock(&ci->lock);
  335. return 0;
  336. }
  337. static int read_attribute_mem(struct dvb_ca_en50221 *ca,
  338. int slot, int address)
  339. {
  340. struct cxd *ci = ca->data;
  341. u8 val;
  342. mutex_lock(&ci->lock);
  343. set_mode(ci, 1);
  344. read_pccard(ci, address, &val, 1);
  345. mutex_unlock(&ci->lock);
  346. return val;
  347. }
  348. static int write_attribute_mem(struct dvb_ca_en50221 *ca, int slot,
  349. int address, u8 value)
  350. {
  351. struct cxd *ci = ca->data;
  352. mutex_lock(&ci->lock);
  353. set_mode(ci, 1);
  354. write_pccard(ci, address, &value, 1);
  355. mutex_unlock(&ci->lock);
  356. return 0;
  357. }
  358. static int read_cam_control(struct dvb_ca_en50221 *ca,
  359. int slot, u8 address)
  360. {
  361. struct cxd *ci = ca->data;
  362. unsigned int val;
  363. mutex_lock(&ci->lock);
  364. set_mode(ci, 0);
  365. read_io(ci, address, &val);
  366. mutex_unlock(&ci->lock);
  367. return val;
  368. }
  369. static int write_cam_control(struct dvb_ca_en50221 *ca, int slot,
  370. u8 address, u8 value)
  371. {
  372. struct cxd *ci = ca->data;
  373. mutex_lock(&ci->lock);
  374. set_mode(ci, 0);
  375. write_io(ci, address, value);
  376. mutex_unlock(&ci->lock);
  377. return 0;
  378. }
  379. static int slot_reset(struct dvb_ca_en50221 *ca, int slot)
  380. {
  381. struct cxd *ci = ca->data;
  382. if (ci->cammode)
  383. read_data(ca, slot, ci->rbuf, 0);
  384. mutex_lock(&ci->lock);
  385. cam_mode(ci, 0);
  386. write_reg(ci, 0x00, 0x21);
  387. write_reg(ci, 0x06, 0x1F);
  388. write_reg(ci, 0x00, 0x31);
  389. write_regm(ci, 0x20, 0x80, 0x80);
  390. write_reg(ci, 0x03, 0x02);
  391. ci->ready = 0;
  392. ci->mode = -1;
  393. {
  394. int i;
  395. for (i = 0; i < 100; i++) {
  396. usleep_range(10000, 11000);
  397. if (ci->ready)
  398. break;
  399. }
  400. }
  401. mutex_unlock(&ci->lock);
  402. return 0;
  403. }
  404. static int slot_shutdown(struct dvb_ca_en50221 *ca, int slot)
  405. {
  406. struct cxd *ci = ca->data;
  407. dev_dbg(&ci->client->dev, "%s\n", __func__);
  408. if (ci->cammode)
  409. read_data(ca, slot, ci->rbuf, 0);
  410. mutex_lock(&ci->lock);
  411. write_reg(ci, 0x00, 0x21);
  412. write_reg(ci, 0x06, 0x1F);
  413. msleep(300);
  414. write_regm(ci, 0x09, 0x08, 0x08);
  415. write_regm(ci, 0x20, 0x80, 0x80); /* Reset CAM Mode */
  416. write_regm(ci, 0x06, 0x07, 0x07); /* Clear IO Mode */
  417. ci->mode = -1;
  418. ci->write_busy = 0;
  419. mutex_unlock(&ci->lock);
  420. return 0;
  421. }
  422. static int slot_ts_enable(struct dvb_ca_en50221 *ca, int slot)
  423. {
  424. struct cxd *ci = ca->data;
  425. mutex_lock(&ci->lock);
  426. write_regm(ci, 0x09, 0x00, 0x08);
  427. set_mode(ci, 0);
  428. cam_mode(ci, 1);
  429. mutex_unlock(&ci->lock);
  430. return 0;
  431. }
  432. static int campoll(struct cxd *ci)
  433. {
  434. u8 istat;
  435. read_reg(ci, 0x04, &istat);
  436. if (!istat)
  437. return 0;
  438. write_reg(ci, 0x05, istat);
  439. if (istat & 0x40)
  440. ci->dr = 1;
  441. if (istat & 0x20)
  442. ci->write_busy = 0;
  443. if (istat & 2) {
  444. u8 slotstat;
  445. read_reg(ci, 0x01, &slotstat);
  446. if (!(2 & slotstat)) {
  447. if (!ci->slot_stat) {
  448. ci->slot_stat |=
  449. DVB_CA_EN50221_POLL_CAM_PRESENT;
  450. write_regm(ci, 0x03, 0x08, 0x08);
  451. }
  452. } else {
  453. if (ci->slot_stat) {
  454. ci->slot_stat = 0;
  455. write_regm(ci, 0x03, 0x00, 0x08);
  456. dev_info(&ci->client->dev, "NO CAM\n");
  457. ci->ready = 0;
  458. }
  459. }
  460. if ((istat & 8) &&
  461. ci->slot_stat == DVB_CA_EN50221_POLL_CAM_PRESENT) {
  462. ci->ready = 1;
  463. ci->slot_stat |= DVB_CA_EN50221_POLL_CAM_READY;
  464. }
  465. }
  466. return 0;
  467. }
  468. static int poll_slot_status(struct dvb_ca_en50221 *ca, int slot, int open)
  469. {
  470. struct cxd *ci = ca->data;
  471. u8 slotstat;
  472. mutex_lock(&ci->lock);
  473. campoll(ci);
  474. read_reg(ci, 0x01, &slotstat);
  475. mutex_unlock(&ci->lock);
  476. return ci->slot_stat;
  477. }
  478. static int read_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount)
  479. {
  480. struct cxd *ci = ca->data;
  481. u8 msb, lsb;
  482. u16 len;
  483. mutex_lock(&ci->lock);
  484. campoll(ci);
  485. mutex_unlock(&ci->lock);
  486. if (!ci->dr)
  487. return 0;
  488. mutex_lock(&ci->lock);
  489. read_reg(ci, 0x0f, &msb);
  490. read_reg(ci, 0x10, &lsb);
  491. len = ((u16)msb << 8) | lsb;
  492. if (len > ecount || len < 2) {
  493. /* read it anyway or cxd may hang */
  494. read_block(ci, 0x12, ci->rbuf, len);
  495. mutex_unlock(&ci->lock);
  496. return -EIO;
  497. }
  498. read_block(ci, 0x12, ebuf, len);
  499. ci->dr = 0;
  500. mutex_unlock(&ci->lock);
  501. return len;
  502. }
  503. static int write_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount)
  504. {
  505. struct cxd *ci = ca->data;
  506. if (ci->write_busy)
  507. return -EAGAIN;
  508. mutex_lock(&ci->lock);
  509. write_reg(ci, 0x0d, ecount >> 8);
  510. write_reg(ci, 0x0e, ecount & 0xff);
  511. write_block(ci, 0x11, ebuf, ecount);
  512. ci->write_busy = 1;
  513. mutex_unlock(&ci->lock);
  514. return ecount;
  515. }
  516. static struct dvb_ca_en50221 en_templ = {
  517. .read_attribute_mem = read_attribute_mem,
  518. .write_attribute_mem = write_attribute_mem,
  519. .read_cam_control = read_cam_control,
  520. .write_cam_control = write_cam_control,
  521. .slot_reset = slot_reset,
  522. .slot_shutdown = slot_shutdown,
  523. .slot_ts_enable = slot_ts_enable,
  524. .poll_slot_status = poll_slot_status,
  525. .read_data = read_data,
  526. .write_data = write_data,
  527. };
  528. static int cxd2099_probe(struct i2c_client *client,
  529. const struct i2c_device_id *id)
  530. {
  531. struct cxd *ci;
  532. struct cxd2099_cfg *cfg = client->dev.platform_data;
  533. static const struct regmap_config rm_cfg = {
  534. .reg_bits = 8,
  535. .val_bits = 8,
  536. };
  537. unsigned int val;
  538. int ret;
  539. ci = kzalloc(sizeof(*ci), GFP_KERNEL);
  540. if (!ci) {
  541. ret = -ENOMEM;
  542. goto err;
  543. }
  544. ci->client = client;
  545. memcpy(&ci->cfg, cfg, sizeof(ci->cfg));
  546. ci->regmap = regmap_init_i2c(client, &rm_cfg);
  547. if (IS_ERR(ci->regmap)) {
  548. ret = PTR_ERR(ci->regmap);
  549. goto err_kfree;
  550. }
  551. ret = regmap_read(ci->regmap, 0x00, &val);
  552. if (ret < 0) {
  553. dev_info(&client->dev, "No CXD2099AR detected at 0x%02x\n",
  554. client->addr);
  555. goto err_rmexit;
  556. }
  557. mutex_init(&ci->lock);
  558. ci->lastaddress = 0xff;
  559. ci->clk_reg_b = 0x4a;
  560. ci->clk_reg_f = 0x1b;
  561. ci->en = en_templ;
  562. ci->en.data = ci;
  563. init(ci);
  564. dev_info(&client->dev, "Attached CXD2099AR at 0x%02x\n", client->addr);
  565. *cfg->en = &ci->en;
  566. if (!buffermode) {
  567. ci->en.read_data = NULL;
  568. ci->en.write_data = NULL;
  569. } else {
  570. dev_info(&client->dev, "Using CXD2099AR buffer mode");
  571. }
  572. i2c_set_clientdata(client, ci);
  573. return 0;
  574. err_rmexit:
  575. regmap_exit(ci->regmap);
  576. err_kfree:
  577. kfree(ci);
  578. err:
  579. return ret;
  580. }
  581. static int cxd2099_remove(struct i2c_client *client)
  582. {
  583. struct cxd *ci = i2c_get_clientdata(client);
  584. regmap_exit(ci->regmap);
  585. kfree(ci);
  586. return 0;
  587. }
  588. static const struct i2c_device_id cxd2099_id[] = {
  589. {"cxd2099", 0},
  590. {}
  591. };
  592. MODULE_DEVICE_TABLE(i2c, cxd2099_id);
  593. static struct i2c_driver cxd2099_driver = {
  594. .driver = {
  595. .name = "cxd2099",
  596. },
  597. .probe = cxd2099_probe,
  598. .remove = cxd2099_remove,
  599. .id_table = cxd2099_id,
  600. };
  601. module_i2c_driver(cxd2099_driver);
  602. MODULE_DESCRIPTION("Sony CXD2099AR Common Interface controller driver");
  603. MODULE_AUTHOR("Ralph Metzler");
  604. MODULE_LICENSE("GPL");