imx6ul_tsc.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Freescale i.MX6UL touchscreen controller driver
  4. //
  5. // Copyright (C) 2015 Freescale Semiconductor, Inc.
  6. #include <linux/errno.h>
  7. #include <linux/kernel.h>
  8. #include <linux/module.h>
  9. #include <linux/gpio/consumer.h>
  10. #include <linux/input.h>
  11. #include <linux/slab.h>
  12. #include <linux/completion.h>
  13. #include <linux/delay.h>
  14. #include <linux/of.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/clk.h>
  18. #include <linux/io.h>
  19. #include <linux/log2.h>
  20. /* ADC configuration registers field define */
  21. #define ADC_AIEN (0x1 << 7)
  22. #define ADC_CONV_DISABLE 0x1F
  23. #define ADC_AVGE (0x1 << 5)
  24. #define ADC_CAL (0x1 << 7)
  25. #define ADC_CALF 0x2
  26. #define ADC_12BIT_MODE (0x2 << 2)
  27. #define ADC_CONV_MODE_MASK (0x3 << 2)
  28. #define ADC_IPG_CLK 0x00
  29. #define ADC_INPUT_CLK_MASK 0x3
  30. #define ADC_CLK_DIV_8 (0x03 << 5)
  31. #define ADC_CLK_DIV_MASK (0x3 << 5)
  32. #define ADC_SHORT_SAMPLE_MODE (0x0 << 4)
  33. #define ADC_SAMPLE_MODE_MASK (0x1 << 4)
  34. #define ADC_HARDWARE_TRIGGER (0x1 << 13)
  35. #define ADC_AVGS_SHIFT 14
  36. #define ADC_AVGS_MASK (0x3 << 14)
  37. #define SELECT_CHANNEL_4 0x04
  38. #define SELECT_CHANNEL_1 0x01
  39. #define DISABLE_CONVERSION_INT (0x0 << 7)
  40. /* ADC registers */
  41. #define REG_ADC_HC0 0x00
  42. #define REG_ADC_HC1 0x04
  43. #define REG_ADC_HC2 0x08
  44. #define REG_ADC_HC3 0x0C
  45. #define REG_ADC_HC4 0x10
  46. #define REG_ADC_HS 0x14
  47. #define REG_ADC_R0 0x18
  48. #define REG_ADC_CFG 0x2C
  49. #define REG_ADC_GC 0x30
  50. #define REG_ADC_GS 0x34
  51. #define ADC_TIMEOUT msecs_to_jiffies(100)
  52. /* TSC registers */
  53. #define REG_TSC_BASIC_SETING 0x00
  54. #define REG_TSC_PRE_CHARGE_TIME 0x10
  55. #define REG_TSC_FLOW_CONTROL 0x20
  56. #define REG_TSC_MEASURE_VALUE 0x30
  57. #define REG_TSC_INT_EN 0x40
  58. #define REG_TSC_INT_SIG_EN 0x50
  59. #define REG_TSC_INT_STATUS 0x60
  60. #define REG_TSC_DEBUG_MODE 0x70
  61. #define REG_TSC_DEBUG_MODE2 0x80
  62. /* TSC configuration registers field define */
  63. #define DETECT_4_WIRE_MODE (0x0 << 4)
  64. #define AUTO_MEASURE 0x1
  65. #define MEASURE_SIGNAL 0x1
  66. #define DETECT_SIGNAL (0x1 << 4)
  67. #define VALID_SIGNAL (0x1 << 8)
  68. #define MEASURE_INT_EN 0x1
  69. #define MEASURE_SIG_EN 0x1
  70. #define VALID_SIG_EN (0x1 << 8)
  71. #define DE_GLITCH_2 (0x2 << 29)
  72. #define START_SENSE (0x1 << 12)
  73. #define TSC_DISABLE (0x1 << 16)
  74. #define DETECT_MODE 0x2
  75. struct imx6ul_tsc {
  76. struct device *dev;
  77. struct input_dev *input;
  78. void __iomem *tsc_regs;
  79. void __iomem *adc_regs;
  80. struct clk *tsc_clk;
  81. struct clk *adc_clk;
  82. struct gpio_desc *xnur_gpio;
  83. u32 measure_delay_time;
  84. u32 pre_charge_time;
  85. bool average_enable;
  86. u32 average_select;
  87. struct completion completion;
  88. };
  89. /*
  90. * TSC module need ADC to get the measure value. So
  91. * before config TSC, we should initialize ADC module.
  92. */
  93. static int imx6ul_adc_init(struct imx6ul_tsc *tsc)
  94. {
  95. u32 adc_hc = 0;
  96. u32 adc_gc;
  97. u32 adc_gs;
  98. u32 adc_cfg;
  99. unsigned long timeout;
  100. reinit_completion(&tsc->completion);
  101. adc_cfg = readl(tsc->adc_regs + REG_ADC_CFG);
  102. adc_cfg &= ~(ADC_CONV_MODE_MASK | ADC_INPUT_CLK_MASK);
  103. adc_cfg |= ADC_12BIT_MODE | ADC_IPG_CLK;
  104. adc_cfg &= ~(ADC_CLK_DIV_MASK | ADC_SAMPLE_MODE_MASK);
  105. adc_cfg |= ADC_CLK_DIV_8 | ADC_SHORT_SAMPLE_MODE;
  106. if (tsc->average_enable) {
  107. adc_cfg &= ~ADC_AVGS_MASK;
  108. adc_cfg |= (tsc->average_select) << ADC_AVGS_SHIFT;
  109. }
  110. adc_cfg &= ~ADC_HARDWARE_TRIGGER;
  111. writel(adc_cfg, tsc->adc_regs + REG_ADC_CFG);
  112. /* enable calibration interrupt */
  113. adc_hc |= ADC_AIEN;
  114. adc_hc |= ADC_CONV_DISABLE;
  115. writel(adc_hc, tsc->adc_regs + REG_ADC_HC0);
  116. /* start ADC calibration */
  117. adc_gc = readl(tsc->adc_regs + REG_ADC_GC);
  118. adc_gc |= ADC_CAL;
  119. if (tsc->average_enable)
  120. adc_gc |= ADC_AVGE;
  121. writel(adc_gc, tsc->adc_regs + REG_ADC_GC);
  122. timeout = wait_for_completion_timeout
  123. (&tsc->completion, ADC_TIMEOUT);
  124. if (timeout == 0) {
  125. dev_err(tsc->dev, "Timeout for adc calibration\n");
  126. return -ETIMEDOUT;
  127. }
  128. adc_gs = readl(tsc->adc_regs + REG_ADC_GS);
  129. if (adc_gs & ADC_CALF) {
  130. dev_err(tsc->dev, "ADC calibration failed\n");
  131. return -EINVAL;
  132. }
  133. /* TSC need the ADC work in hardware trigger */
  134. adc_cfg = readl(tsc->adc_regs + REG_ADC_CFG);
  135. adc_cfg |= ADC_HARDWARE_TRIGGER;
  136. writel(adc_cfg, tsc->adc_regs + REG_ADC_CFG);
  137. return 0;
  138. }
  139. /*
  140. * This is a TSC workaround. Currently TSC misconnect two
  141. * ADC channels, this function remap channel configure for
  142. * hardware trigger.
  143. */
  144. static void imx6ul_tsc_channel_config(struct imx6ul_tsc *tsc)
  145. {
  146. u32 adc_hc0, adc_hc1, adc_hc2, adc_hc3, adc_hc4;
  147. adc_hc0 = DISABLE_CONVERSION_INT;
  148. writel(adc_hc0, tsc->adc_regs + REG_ADC_HC0);
  149. adc_hc1 = DISABLE_CONVERSION_INT | SELECT_CHANNEL_4;
  150. writel(adc_hc1, tsc->adc_regs + REG_ADC_HC1);
  151. adc_hc2 = DISABLE_CONVERSION_INT;
  152. writel(adc_hc2, tsc->adc_regs + REG_ADC_HC2);
  153. adc_hc3 = DISABLE_CONVERSION_INT | SELECT_CHANNEL_1;
  154. writel(adc_hc3, tsc->adc_regs + REG_ADC_HC3);
  155. adc_hc4 = DISABLE_CONVERSION_INT;
  156. writel(adc_hc4, tsc->adc_regs + REG_ADC_HC4);
  157. }
  158. /*
  159. * TSC setting, confige the pre-charge time and measure delay time.
  160. * different touch screen may need different pre-charge time and
  161. * measure delay time.
  162. */
  163. static void imx6ul_tsc_set(struct imx6ul_tsc *tsc)
  164. {
  165. u32 basic_setting = 0;
  166. u32 start;
  167. basic_setting |= tsc->measure_delay_time << 8;
  168. basic_setting |= DETECT_4_WIRE_MODE | AUTO_MEASURE;
  169. writel(basic_setting, tsc->tsc_regs + REG_TSC_BASIC_SETING);
  170. writel(DE_GLITCH_2, tsc->tsc_regs + REG_TSC_DEBUG_MODE2);
  171. writel(tsc->pre_charge_time, tsc->tsc_regs + REG_TSC_PRE_CHARGE_TIME);
  172. writel(MEASURE_INT_EN, tsc->tsc_regs + REG_TSC_INT_EN);
  173. writel(MEASURE_SIG_EN | VALID_SIG_EN,
  174. tsc->tsc_regs + REG_TSC_INT_SIG_EN);
  175. /* start sense detection */
  176. start = readl(tsc->tsc_regs + REG_TSC_FLOW_CONTROL);
  177. start |= START_SENSE;
  178. start &= ~TSC_DISABLE;
  179. writel(start, tsc->tsc_regs + REG_TSC_FLOW_CONTROL);
  180. }
  181. static int imx6ul_tsc_init(struct imx6ul_tsc *tsc)
  182. {
  183. int err;
  184. err = imx6ul_adc_init(tsc);
  185. if (err)
  186. return err;
  187. imx6ul_tsc_channel_config(tsc);
  188. imx6ul_tsc_set(tsc);
  189. return 0;
  190. }
  191. static void imx6ul_tsc_disable(struct imx6ul_tsc *tsc)
  192. {
  193. u32 tsc_flow;
  194. u32 adc_cfg;
  195. /* TSC controller enters to idle status */
  196. tsc_flow = readl(tsc->tsc_regs + REG_TSC_FLOW_CONTROL);
  197. tsc_flow |= TSC_DISABLE;
  198. writel(tsc_flow, tsc->tsc_regs + REG_TSC_FLOW_CONTROL);
  199. /* ADC controller enters to stop mode */
  200. adc_cfg = readl(tsc->adc_regs + REG_ADC_HC0);
  201. adc_cfg |= ADC_CONV_DISABLE;
  202. writel(adc_cfg, tsc->adc_regs + REG_ADC_HC0);
  203. }
  204. /* Delay some time (max 2ms), wait the pre-charge done. */
  205. static bool tsc_wait_detect_mode(struct imx6ul_tsc *tsc)
  206. {
  207. unsigned long timeout = jiffies + msecs_to_jiffies(2);
  208. u32 state_machine;
  209. u32 debug_mode2;
  210. do {
  211. if (time_after(jiffies, timeout))
  212. return false;
  213. usleep_range(200, 400);
  214. debug_mode2 = readl(tsc->tsc_regs + REG_TSC_DEBUG_MODE2);
  215. state_machine = (debug_mode2 >> 20) & 0x7;
  216. } while (state_machine != DETECT_MODE);
  217. usleep_range(200, 400);
  218. return true;
  219. }
  220. static irqreturn_t tsc_irq_fn(int irq, void *dev_id)
  221. {
  222. struct imx6ul_tsc *tsc = dev_id;
  223. u32 status;
  224. u32 value;
  225. u32 x, y;
  226. u32 start;
  227. status = readl(tsc->tsc_regs + REG_TSC_INT_STATUS);
  228. /* write 1 to clear the bit measure-signal */
  229. writel(MEASURE_SIGNAL | DETECT_SIGNAL,
  230. tsc->tsc_regs + REG_TSC_INT_STATUS);
  231. /* It's a HW self-clean bit. Set this bit and start sense detection */
  232. start = readl(tsc->tsc_regs + REG_TSC_FLOW_CONTROL);
  233. start |= START_SENSE;
  234. writel(start, tsc->tsc_regs + REG_TSC_FLOW_CONTROL);
  235. if (status & MEASURE_SIGNAL) {
  236. value = readl(tsc->tsc_regs + REG_TSC_MEASURE_VALUE);
  237. x = (value >> 16) & 0x0fff;
  238. y = value & 0x0fff;
  239. /*
  240. * In detect mode, we can get the xnur gpio value,
  241. * otherwise assume contact is stiull active.
  242. */
  243. if (!tsc_wait_detect_mode(tsc) ||
  244. gpiod_get_value_cansleep(tsc->xnur_gpio)) {
  245. input_report_key(tsc->input, BTN_TOUCH, 1);
  246. input_report_abs(tsc->input, ABS_X, x);
  247. input_report_abs(tsc->input, ABS_Y, y);
  248. } else {
  249. input_report_key(tsc->input, BTN_TOUCH, 0);
  250. }
  251. input_sync(tsc->input);
  252. }
  253. return IRQ_HANDLED;
  254. }
  255. static irqreturn_t adc_irq_fn(int irq, void *dev_id)
  256. {
  257. struct imx6ul_tsc *tsc = dev_id;
  258. u32 coco;
  259. u32 value;
  260. coco = readl(tsc->adc_regs + REG_ADC_HS);
  261. if (coco & 0x01) {
  262. value = readl(tsc->adc_regs + REG_ADC_R0);
  263. complete(&tsc->completion);
  264. }
  265. return IRQ_HANDLED;
  266. }
  267. static int imx6ul_tsc_open(struct input_dev *input_dev)
  268. {
  269. struct imx6ul_tsc *tsc = input_get_drvdata(input_dev);
  270. int err;
  271. err = clk_prepare_enable(tsc->adc_clk);
  272. if (err) {
  273. dev_err(tsc->dev,
  274. "Could not prepare or enable the adc clock: %d\n",
  275. err);
  276. return err;
  277. }
  278. err = clk_prepare_enable(tsc->tsc_clk);
  279. if (err) {
  280. dev_err(tsc->dev,
  281. "Could not prepare or enable the tsc clock: %d\n",
  282. err);
  283. goto disable_adc_clk;
  284. }
  285. err = imx6ul_tsc_init(tsc);
  286. if (err)
  287. goto disable_tsc_clk;
  288. return 0;
  289. disable_tsc_clk:
  290. clk_disable_unprepare(tsc->tsc_clk);
  291. disable_adc_clk:
  292. clk_disable_unprepare(tsc->adc_clk);
  293. return err;
  294. }
  295. static void imx6ul_tsc_close(struct input_dev *input_dev)
  296. {
  297. struct imx6ul_tsc *tsc = input_get_drvdata(input_dev);
  298. imx6ul_tsc_disable(tsc);
  299. clk_disable_unprepare(tsc->tsc_clk);
  300. clk_disable_unprepare(tsc->adc_clk);
  301. }
  302. static int imx6ul_tsc_probe(struct platform_device *pdev)
  303. {
  304. struct device_node *np = pdev->dev.of_node;
  305. struct imx6ul_tsc *tsc;
  306. struct input_dev *input_dev;
  307. struct resource *tsc_mem;
  308. struct resource *adc_mem;
  309. int err;
  310. int tsc_irq;
  311. int adc_irq;
  312. u32 average_samples;
  313. tsc = devm_kzalloc(&pdev->dev, sizeof(*tsc), GFP_KERNEL);
  314. if (!tsc)
  315. return -ENOMEM;
  316. input_dev = devm_input_allocate_device(&pdev->dev);
  317. if (!input_dev)
  318. return -ENOMEM;
  319. input_dev->name = "iMX6UL Touchscreen Controller";
  320. input_dev->id.bustype = BUS_HOST;
  321. input_dev->open = imx6ul_tsc_open;
  322. input_dev->close = imx6ul_tsc_close;
  323. input_set_capability(input_dev, EV_KEY, BTN_TOUCH);
  324. input_set_abs_params(input_dev, ABS_X, 0, 0xFFF, 0, 0);
  325. input_set_abs_params(input_dev, ABS_Y, 0, 0xFFF, 0, 0);
  326. input_set_drvdata(input_dev, tsc);
  327. tsc->dev = &pdev->dev;
  328. tsc->input = input_dev;
  329. init_completion(&tsc->completion);
  330. tsc->xnur_gpio = devm_gpiod_get(&pdev->dev, "xnur", GPIOD_IN);
  331. if (IS_ERR(tsc->xnur_gpio)) {
  332. err = PTR_ERR(tsc->xnur_gpio);
  333. dev_err(&pdev->dev,
  334. "failed to request GPIO tsc_X- (xnur): %d\n", err);
  335. return err;
  336. }
  337. tsc_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  338. tsc->tsc_regs = devm_ioremap_resource(&pdev->dev, tsc_mem);
  339. if (IS_ERR(tsc->tsc_regs)) {
  340. err = PTR_ERR(tsc->tsc_regs);
  341. dev_err(&pdev->dev, "failed to remap tsc memory: %d\n", err);
  342. return err;
  343. }
  344. adc_mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  345. tsc->adc_regs = devm_ioremap_resource(&pdev->dev, adc_mem);
  346. if (IS_ERR(tsc->adc_regs)) {
  347. err = PTR_ERR(tsc->adc_regs);
  348. dev_err(&pdev->dev, "failed to remap adc memory: %d\n", err);
  349. return err;
  350. }
  351. tsc->tsc_clk = devm_clk_get(&pdev->dev, "tsc");
  352. if (IS_ERR(tsc->tsc_clk)) {
  353. err = PTR_ERR(tsc->tsc_clk);
  354. dev_err(&pdev->dev, "failed getting tsc clock: %d\n", err);
  355. return err;
  356. }
  357. tsc->adc_clk = devm_clk_get(&pdev->dev, "adc");
  358. if (IS_ERR(tsc->adc_clk)) {
  359. err = PTR_ERR(tsc->adc_clk);
  360. dev_err(&pdev->dev, "failed getting adc clock: %d\n", err);
  361. return err;
  362. }
  363. tsc_irq = platform_get_irq(pdev, 0);
  364. if (tsc_irq < 0) {
  365. dev_err(&pdev->dev, "no tsc irq resource?\n");
  366. return tsc_irq;
  367. }
  368. adc_irq = platform_get_irq(pdev, 1);
  369. if (adc_irq < 0) {
  370. dev_err(&pdev->dev, "no adc irq resource?\n");
  371. return adc_irq;
  372. }
  373. err = devm_request_threaded_irq(tsc->dev, tsc_irq,
  374. NULL, tsc_irq_fn, IRQF_ONESHOT,
  375. dev_name(&pdev->dev), tsc);
  376. if (err) {
  377. dev_err(&pdev->dev,
  378. "failed requesting tsc irq %d: %d\n",
  379. tsc_irq, err);
  380. return err;
  381. }
  382. err = devm_request_irq(tsc->dev, adc_irq, adc_irq_fn, 0,
  383. dev_name(&pdev->dev), tsc);
  384. if (err) {
  385. dev_err(&pdev->dev,
  386. "failed requesting adc irq %d: %d\n",
  387. adc_irq, err);
  388. return err;
  389. }
  390. err = of_property_read_u32(np, "measure-delay-time",
  391. &tsc->measure_delay_time);
  392. if (err)
  393. tsc->measure_delay_time = 0xffff;
  394. err = of_property_read_u32(np, "pre-charge-time",
  395. &tsc->pre_charge_time);
  396. if (err)
  397. tsc->pre_charge_time = 0xfff;
  398. err = of_property_read_u32(np, "touchscreen-average-samples",
  399. &average_samples);
  400. if (err)
  401. average_samples = 1;
  402. switch (average_samples) {
  403. case 1:
  404. tsc->average_enable = false;
  405. tsc->average_select = 0; /* value unused; initialize anyway */
  406. break;
  407. case 4:
  408. case 8:
  409. case 16:
  410. case 32:
  411. tsc->average_enable = true;
  412. tsc->average_select = ilog2(average_samples) - 2;
  413. break;
  414. default:
  415. dev_err(&pdev->dev,
  416. "touchscreen-average-samples (%u) must be 1, 4, 8, 16 or 32\n",
  417. average_samples);
  418. return -EINVAL;
  419. }
  420. err = input_register_device(tsc->input);
  421. if (err) {
  422. dev_err(&pdev->dev,
  423. "failed to register input device: %d\n", err);
  424. return err;
  425. }
  426. platform_set_drvdata(pdev, tsc);
  427. return 0;
  428. }
  429. static int __maybe_unused imx6ul_tsc_suspend(struct device *dev)
  430. {
  431. struct platform_device *pdev = to_platform_device(dev);
  432. struct imx6ul_tsc *tsc = platform_get_drvdata(pdev);
  433. struct input_dev *input_dev = tsc->input;
  434. mutex_lock(&input_dev->mutex);
  435. if (input_dev->users) {
  436. imx6ul_tsc_disable(tsc);
  437. clk_disable_unprepare(tsc->tsc_clk);
  438. clk_disable_unprepare(tsc->adc_clk);
  439. }
  440. mutex_unlock(&input_dev->mutex);
  441. return 0;
  442. }
  443. static int __maybe_unused imx6ul_tsc_resume(struct device *dev)
  444. {
  445. struct platform_device *pdev = to_platform_device(dev);
  446. struct imx6ul_tsc *tsc = platform_get_drvdata(pdev);
  447. struct input_dev *input_dev = tsc->input;
  448. int retval = 0;
  449. mutex_lock(&input_dev->mutex);
  450. if (input_dev->users) {
  451. retval = clk_prepare_enable(tsc->adc_clk);
  452. if (retval)
  453. goto out;
  454. retval = clk_prepare_enable(tsc->tsc_clk);
  455. if (retval) {
  456. clk_disable_unprepare(tsc->adc_clk);
  457. goto out;
  458. }
  459. retval = imx6ul_tsc_init(tsc);
  460. }
  461. out:
  462. mutex_unlock(&input_dev->mutex);
  463. return retval;
  464. }
  465. static SIMPLE_DEV_PM_OPS(imx6ul_tsc_pm_ops,
  466. imx6ul_tsc_suspend, imx6ul_tsc_resume);
  467. static const struct of_device_id imx6ul_tsc_match[] = {
  468. { .compatible = "fsl,imx6ul-tsc", },
  469. { /* sentinel */ }
  470. };
  471. MODULE_DEVICE_TABLE(of, imx6ul_tsc_match);
  472. static struct platform_driver imx6ul_tsc_driver = {
  473. .driver = {
  474. .name = "imx6ul-tsc",
  475. .of_match_table = imx6ul_tsc_match,
  476. .pm = &imx6ul_tsc_pm_ops,
  477. },
  478. .probe = imx6ul_tsc_probe,
  479. };
  480. module_platform_driver(imx6ul_tsc_driver);
  481. MODULE_AUTHOR("Haibo Chen <haibo.chen@freescale.com>");
  482. MODULE_DESCRIPTION("Freescale i.MX6UL Touchscreen controller driver");
  483. MODULE_LICENSE("GPL v2");