main.c 93 KB

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  1. /*
  2. * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
  3. * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenIB.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. */
  33. #include <linux/module.h>
  34. #include <linux/init.h>
  35. #include <linux/slab.h>
  36. #include <linux/errno.h>
  37. #include <linux/netdevice.h>
  38. #include <linux/inetdevice.h>
  39. #include <linux/rtnetlink.h>
  40. #include <linux/if_vlan.h>
  41. #include <linux/sched/mm.h>
  42. #include <linux/sched/task.h>
  43. #include <net/ipv6.h>
  44. #include <net/addrconf.h>
  45. #include <net/devlink.h>
  46. #include <rdma/ib_smi.h>
  47. #include <rdma/ib_user_verbs.h>
  48. #include <rdma/ib_addr.h>
  49. #include <rdma/ib_cache.h>
  50. #include <net/bonding.h>
  51. #include <linux/mlx4/driver.h>
  52. #include <linux/mlx4/cmd.h>
  53. #include <linux/mlx4/qp.h>
  54. #include "mlx4_ib.h"
  55. #include <rdma/mlx4-abi.h>
  56. #define DRV_NAME MLX4_IB_DRV_NAME
  57. #define DRV_VERSION "4.0-0"
  58. #define MLX4_IB_FLOW_MAX_PRIO 0xFFF
  59. #define MLX4_IB_FLOW_QPN_MASK 0xFFFFFF
  60. #define MLX4_IB_CARD_REV_A0 0xA0
  61. MODULE_AUTHOR("Roland Dreier");
  62. MODULE_DESCRIPTION("Mellanox ConnectX HCA InfiniBand driver");
  63. MODULE_LICENSE("Dual BSD/GPL");
  64. int mlx4_ib_sm_guid_assign = 0;
  65. module_param_named(sm_guid_assign, mlx4_ib_sm_guid_assign, int, 0444);
  66. MODULE_PARM_DESC(sm_guid_assign, "Enable SM alias_GUID assignment if sm_guid_assign > 0 (Default: 0)");
  67. static const char mlx4_ib_version[] =
  68. DRV_NAME ": Mellanox ConnectX InfiniBand driver v"
  69. DRV_VERSION "\n";
  70. static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init);
  71. static enum rdma_link_layer mlx4_ib_port_link_layer(struct ib_device *device,
  72. u8 port_num);
  73. static struct workqueue_struct *wq;
  74. static void init_query_mad(struct ib_smp *mad)
  75. {
  76. mad->base_version = 1;
  77. mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
  78. mad->class_version = 1;
  79. mad->method = IB_MGMT_METHOD_GET;
  80. }
  81. static int check_flow_steering_support(struct mlx4_dev *dev)
  82. {
  83. int eth_num_ports = 0;
  84. int ib_num_ports = 0;
  85. int dmfs = dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED;
  86. if (dmfs) {
  87. int i;
  88. mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH)
  89. eth_num_ports++;
  90. mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
  91. ib_num_ports++;
  92. dmfs &= (!ib_num_ports ||
  93. (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB)) &&
  94. (!eth_num_ports ||
  95. (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN));
  96. if (ib_num_ports && mlx4_is_mfunc(dev)) {
  97. pr_warn("Device managed flow steering is unavailable for IB port in multifunction env.\n");
  98. dmfs = 0;
  99. }
  100. }
  101. return dmfs;
  102. }
  103. static int num_ib_ports(struct mlx4_dev *dev)
  104. {
  105. int ib_ports = 0;
  106. int i;
  107. mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
  108. ib_ports++;
  109. return ib_ports;
  110. }
  111. static struct net_device *mlx4_ib_get_netdev(struct ib_device *device, u8 port_num)
  112. {
  113. struct mlx4_ib_dev *ibdev = to_mdev(device);
  114. struct net_device *dev;
  115. rcu_read_lock();
  116. dev = mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port_num);
  117. if (dev) {
  118. if (mlx4_is_bonded(ibdev->dev)) {
  119. struct net_device *upper = NULL;
  120. upper = netdev_master_upper_dev_get_rcu(dev);
  121. if (upper) {
  122. struct net_device *active;
  123. active = bond_option_active_slave_get_rcu(netdev_priv(upper));
  124. if (active)
  125. dev = active;
  126. }
  127. }
  128. }
  129. if (dev)
  130. dev_hold(dev);
  131. rcu_read_unlock();
  132. return dev;
  133. }
  134. static int mlx4_ib_update_gids_v1(struct gid_entry *gids,
  135. struct mlx4_ib_dev *ibdev,
  136. u8 port_num)
  137. {
  138. struct mlx4_cmd_mailbox *mailbox;
  139. int err;
  140. struct mlx4_dev *dev = ibdev->dev;
  141. int i;
  142. union ib_gid *gid_tbl;
  143. mailbox = mlx4_alloc_cmd_mailbox(dev);
  144. if (IS_ERR(mailbox))
  145. return -ENOMEM;
  146. gid_tbl = mailbox->buf;
  147. for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i)
  148. memcpy(&gid_tbl[i], &gids[i].gid, sizeof(union ib_gid));
  149. err = mlx4_cmd(dev, mailbox->dma,
  150. MLX4_SET_PORT_GID_TABLE << 8 | port_num,
  151. 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
  152. MLX4_CMD_WRAPPED);
  153. if (mlx4_is_bonded(dev))
  154. err += mlx4_cmd(dev, mailbox->dma,
  155. MLX4_SET_PORT_GID_TABLE << 8 | 2,
  156. 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
  157. MLX4_CMD_WRAPPED);
  158. mlx4_free_cmd_mailbox(dev, mailbox);
  159. return err;
  160. }
  161. static int mlx4_ib_update_gids_v1_v2(struct gid_entry *gids,
  162. struct mlx4_ib_dev *ibdev,
  163. u8 port_num)
  164. {
  165. struct mlx4_cmd_mailbox *mailbox;
  166. int err;
  167. struct mlx4_dev *dev = ibdev->dev;
  168. int i;
  169. struct {
  170. union ib_gid gid;
  171. __be32 rsrvd1[2];
  172. __be16 rsrvd2;
  173. u8 type;
  174. u8 version;
  175. __be32 rsrvd3;
  176. } *gid_tbl;
  177. mailbox = mlx4_alloc_cmd_mailbox(dev);
  178. if (IS_ERR(mailbox))
  179. return -ENOMEM;
  180. gid_tbl = mailbox->buf;
  181. for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) {
  182. memcpy(&gid_tbl[i].gid, &gids[i].gid, sizeof(union ib_gid));
  183. if (gids[i].gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) {
  184. gid_tbl[i].version = 2;
  185. if (!ipv6_addr_v4mapped((struct in6_addr *)&gids[i].gid))
  186. gid_tbl[i].type = 1;
  187. }
  188. }
  189. err = mlx4_cmd(dev, mailbox->dma,
  190. MLX4_SET_PORT_ROCE_ADDR << 8 | port_num,
  191. 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
  192. MLX4_CMD_WRAPPED);
  193. if (mlx4_is_bonded(dev))
  194. err += mlx4_cmd(dev, mailbox->dma,
  195. MLX4_SET_PORT_ROCE_ADDR << 8 | 2,
  196. 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
  197. MLX4_CMD_WRAPPED);
  198. mlx4_free_cmd_mailbox(dev, mailbox);
  199. return err;
  200. }
  201. static int mlx4_ib_update_gids(struct gid_entry *gids,
  202. struct mlx4_ib_dev *ibdev,
  203. u8 port_num)
  204. {
  205. if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2)
  206. return mlx4_ib_update_gids_v1_v2(gids, ibdev, port_num);
  207. return mlx4_ib_update_gids_v1(gids, ibdev, port_num);
  208. }
  209. static void free_gid_entry(struct gid_entry *entry)
  210. {
  211. memset(&entry->gid, 0, sizeof(entry->gid));
  212. kfree(entry->ctx);
  213. entry->ctx = NULL;
  214. }
  215. static int mlx4_ib_add_gid(const struct ib_gid_attr *attr, void **context)
  216. {
  217. struct mlx4_ib_dev *ibdev = to_mdev(attr->device);
  218. struct mlx4_ib_iboe *iboe = &ibdev->iboe;
  219. struct mlx4_port_gid_table *port_gid_table;
  220. int free = -1, found = -1;
  221. int ret = 0;
  222. int hw_update = 0;
  223. int i;
  224. struct gid_entry *gids = NULL;
  225. if (!rdma_cap_roce_gid_table(attr->device, attr->port_num))
  226. return -EINVAL;
  227. if (attr->port_num > MLX4_MAX_PORTS)
  228. return -EINVAL;
  229. if (!context)
  230. return -EINVAL;
  231. port_gid_table = &iboe->gids[attr->port_num - 1];
  232. spin_lock_bh(&iboe->lock);
  233. for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) {
  234. if (!memcmp(&port_gid_table->gids[i].gid,
  235. &attr->gid, sizeof(attr->gid)) &&
  236. port_gid_table->gids[i].gid_type == attr->gid_type) {
  237. found = i;
  238. break;
  239. }
  240. if (free < 0 && rdma_is_zero_gid(&port_gid_table->gids[i].gid))
  241. free = i; /* HW has space */
  242. }
  243. if (found < 0) {
  244. if (free < 0) {
  245. ret = -ENOSPC;
  246. } else {
  247. port_gid_table->gids[free].ctx = kmalloc(sizeof(*port_gid_table->gids[free].ctx), GFP_ATOMIC);
  248. if (!port_gid_table->gids[free].ctx) {
  249. ret = -ENOMEM;
  250. } else {
  251. *context = port_gid_table->gids[free].ctx;
  252. memcpy(&port_gid_table->gids[free].gid,
  253. &attr->gid, sizeof(attr->gid));
  254. port_gid_table->gids[free].gid_type = attr->gid_type;
  255. port_gid_table->gids[free].ctx->real_index = free;
  256. port_gid_table->gids[free].ctx->refcount = 1;
  257. hw_update = 1;
  258. }
  259. }
  260. } else {
  261. struct gid_cache_context *ctx = port_gid_table->gids[found].ctx;
  262. *context = ctx;
  263. ctx->refcount++;
  264. }
  265. if (!ret && hw_update) {
  266. gids = kmalloc_array(MLX4_MAX_PORT_GIDS, sizeof(*gids),
  267. GFP_ATOMIC);
  268. if (!gids) {
  269. ret = -ENOMEM;
  270. *context = NULL;
  271. free_gid_entry(&port_gid_table->gids[free]);
  272. } else {
  273. for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) {
  274. memcpy(&gids[i].gid, &port_gid_table->gids[i].gid, sizeof(union ib_gid));
  275. gids[i].gid_type = port_gid_table->gids[i].gid_type;
  276. }
  277. }
  278. }
  279. spin_unlock_bh(&iboe->lock);
  280. if (!ret && hw_update) {
  281. ret = mlx4_ib_update_gids(gids, ibdev, attr->port_num);
  282. if (ret) {
  283. spin_lock_bh(&iboe->lock);
  284. *context = NULL;
  285. free_gid_entry(&port_gid_table->gids[free]);
  286. spin_unlock_bh(&iboe->lock);
  287. }
  288. kfree(gids);
  289. }
  290. return ret;
  291. }
  292. static int mlx4_ib_del_gid(const struct ib_gid_attr *attr, void **context)
  293. {
  294. struct gid_cache_context *ctx = *context;
  295. struct mlx4_ib_dev *ibdev = to_mdev(attr->device);
  296. struct mlx4_ib_iboe *iboe = &ibdev->iboe;
  297. struct mlx4_port_gid_table *port_gid_table;
  298. int ret = 0;
  299. int hw_update = 0;
  300. struct gid_entry *gids = NULL;
  301. if (!rdma_cap_roce_gid_table(attr->device, attr->port_num))
  302. return -EINVAL;
  303. if (attr->port_num > MLX4_MAX_PORTS)
  304. return -EINVAL;
  305. port_gid_table = &iboe->gids[attr->port_num - 1];
  306. spin_lock_bh(&iboe->lock);
  307. if (ctx) {
  308. ctx->refcount--;
  309. if (!ctx->refcount) {
  310. unsigned int real_index = ctx->real_index;
  311. free_gid_entry(&port_gid_table->gids[real_index]);
  312. hw_update = 1;
  313. }
  314. }
  315. if (!ret && hw_update) {
  316. int i;
  317. gids = kmalloc_array(MLX4_MAX_PORT_GIDS, sizeof(*gids),
  318. GFP_ATOMIC);
  319. if (!gids) {
  320. ret = -ENOMEM;
  321. } else {
  322. for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) {
  323. memcpy(&gids[i].gid,
  324. &port_gid_table->gids[i].gid,
  325. sizeof(union ib_gid));
  326. gids[i].gid_type =
  327. port_gid_table->gids[i].gid_type;
  328. }
  329. }
  330. }
  331. spin_unlock_bh(&iboe->lock);
  332. if (!ret && hw_update) {
  333. ret = mlx4_ib_update_gids(gids, ibdev, attr->port_num);
  334. kfree(gids);
  335. }
  336. return ret;
  337. }
  338. int mlx4_ib_gid_index_to_real_index(struct mlx4_ib_dev *ibdev,
  339. const struct ib_gid_attr *attr)
  340. {
  341. struct mlx4_ib_iboe *iboe = &ibdev->iboe;
  342. struct gid_cache_context *ctx = NULL;
  343. struct mlx4_port_gid_table *port_gid_table;
  344. int real_index = -EINVAL;
  345. int i;
  346. unsigned long flags;
  347. u8 port_num = attr->port_num;
  348. if (port_num > MLX4_MAX_PORTS)
  349. return -EINVAL;
  350. if (mlx4_is_bonded(ibdev->dev))
  351. port_num = 1;
  352. if (!rdma_cap_roce_gid_table(&ibdev->ib_dev, port_num))
  353. return attr->index;
  354. spin_lock_irqsave(&iboe->lock, flags);
  355. port_gid_table = &iboe->gids[port_num - 1];
  356. for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i)
  357. if (!memcmp(&port_gid_table->gids[i].gid,
  358. &attr->gid, sizeof(attr->gid)) &&
  359. attr->gid_type == port_gid_table->gids[i].gid_type) {
  360. ctx = port_gid_table->gids[i].ctx;
  361. break;
  362. }
  363. if (ctx)
  364. real_index = ctx->real_index;
  365. spin_unlock_irqrestore(&iboe->lock, flags);
  366. return real_index;
  367. }
  368. #define field_avail(type, fld, sz) (offsetof(type, fld) + \
  369. sizeof(((type *)0)->fld) <= (sz))
  370. static int mlx4_ib_query_device(struct ib_device *ibdev,
  371. struct ib_device_attr *props,
  372. struct ib_udata *uhw)
  373. {
  374. struct mlx4_ib_dev *dev = to_mdev(ibdev);
  375. struct ib_smp *in_mad = NULL;
  376. struct ib_smp *out_mad = NULL;
  377. int err;
  378. int have_ib_ports;
  379. struct mlx4_uverbs_ex_query_device cmd;
  380. struct mlx4_uverbs_ex_query_device_resp resp = {.comp_mask = 0};
  381. struct mlx4_clock_params clock_params;
  382. if (uhw->inlen) {
  383. if (uhw->inlen < sizeof(cmd))
  384. return -EINVAL;
  385. err = ib_copy_from_udata(&cmd, uhw, sizeof(cmd));
  386. if (err)
  387. return err;
  388. if (cmd.comp_mask)
  389. return -EINVAL;
  390. if (cmd.reserved)
  391. return -EINVAL;
  392. }
  393. resp.response_length = offsetof(typeof(resp), response_length) +
  394. sizeof(resp.response_length);
  395. in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
  396. out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
  397. err = -ENOMEM;
  398. if (!in_mad || !out_mad)
  399. goto out;
  400. init_query_mad(in_mad);
  401. in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
  402. err = mlx4_MAD_IFC(to_mdev(ibdev), MLX4_MAD_IFC_IGNORE_KEYS,
  403. 1, NULL, NULL, in_mad, out_mad);
  404. if (err)
  405. goto out;
  406. memset(props, 0, sizeof *props);
  407. have_ib_ports = num_ib_ports(dev->dev);
  408. props->fw_ver = dev->dev->caps.fw_ver;
  409. props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
  410. IB_DEVICE_PORT_ACTIVE_EVENT |
  411. IB_DEVICE_SYS_IMAGE_GUID |
  412. IB_DEVICE_RC_RNR_NAK_GEN |
  413. IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
  414. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR)
  415. props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
  416. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR)
  417. props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
  418. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_APM && have_ib_ports)
  419. props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
  420. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UD_AV_PORT)
  421. props->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
  422. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
  423. props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
  424. if (dev->dev->caps.max_gso_sz &&
  425. (dev->dev->rev_id != MLX4_IB_CARD_REV_A0) &&
  426. (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BLH))
  427. props->device_cap_flags |= IB_DEVICE_UD_TSO;
  428. if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_RESERVED_LKEY)
  429. props->device_cap_flags |= IB_DEVICE_LOCAL_DMA_LKEY;
  430. if ((dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_LOCAL_INV) &&
  431. (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_REMOTE_INV) &&
  432. (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_FAST_REG_WR))
  433. props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
  434. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)
  435. props->device_cap_flags |= IB_DEVICE_XRC;
  436. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW)
  437. props->device_cap_flags |= IB_DEVICE_MEM_WINDOW;
  438. if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) {
  439. if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_WIN_TYPE_2B)
  440. props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2B;
  441. else
  442. props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2A;
  443. }
  444. if (dev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED)
  445. props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
  446. props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
  447. props->vendor_id = be32_to_cpup((__be32 *) (out_mad->data + 36)) &
  448. 0xffffff;
  449. props->vendor_part_id = dev->dev->persist->pdev->device;
  450. props->hw_ver = be32_to_cpup((__be32 *) (out_mad->data + 32));
  451. memcpy(&props->sys_image_guid, out_mad->data + 4, 8);
  452. props->max_mr_size = ~0ull;
  453. props->page_size_cap = dev->dev->caps.page_size_cap;
  454. props->max_qp = dev->dev->quotas.qp;
  455. props->max_qp_wr = dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE;
  456. props->max_send_sge =
  457. min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg);
  458. props->max_recv_sge =
  459. min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg);
  460. props->max_sge_rd = MLX4_MAX_SGE_RD;
  461. props->max_cq = dev->dev->quotas.cq;
  462. props->max_cqe = dev->dev->caps.max_cqes;
  463. props->max_mr = dev->dev->quotas.mpt;
  464. props->max_pd = dev->dev->caps.num_pds - dev->dev->caps.reserved_pds;
  465. props->max_qp_rd_atom = dev->dev->caps.max_qp_dest_rdma;
  466. props->max_qp_init_rd_atom = dev->dev->caps.max_qp_init_rdma;
  467. props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
  468. props->max_srq = dev->dev->quotas.srq;
  469. props->max_srq_wr = dev->dev->caps.max_srq_wqes - 1;
  470. props->max_srq_sge = dev->dev->caps.max_srq_sge;
  471. props->max_fast_reg_page_list_len = MLX4_MAX_FAST_REG_PAGES;
  472. props->local_ca_ack_delay = dev->dev->caps.local_ca_ack_delay;
  473. props->atomic_cap = dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_ATOMIC ?
  474. IB_ATOMIC_HCA : IB_ATOMIC_NONE;
  475. props->masked_atomic_cap = props->atomic_cap;
  476. props->max_pkeys = dev->dev->caps.pkey_table_len[1];
  477. props->max_mcast_grp = dev->dev->caps.num_mgms + dev->dev->caps.num_amgms;
  478. props->max_mcast_qp_attach = dev->dev->caps.num_qp_per_mgm;
  479. props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
  480. props->max_mcast_grp;
  481. props->max_map_per_fmr = dev->dev->caps.max_fmr_maps;
  482. props->hca_core_clock = dev->dev->caps.hca_core_clock * 1000UL;
  483. props->timestamp_mask = 0xFFFFFFFFFFFFULL;
  484. props->max_ah = INT_MAX;
  485. if (mlx4_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET ||
  486. mlx4_ib_port_link_layer(ibdev, 2) == IB_LINK_LAYER_ETHERNET) {
  487. if (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS) {
  488. props->rss_caps.max_rwq_indirection_tables =
  489. props->max_qp;
  490. props->rss_caps.max_rwq_indirection_table_size =
  491. dev->dev->caps.max_rss_tbl_sz;
  492. props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
  493. props->max_wq_type_rq = props->max_qp;
  494. }
  495. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)
  496. props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
  497. }
  498. props->cq_caps.max_cq_moderation_count = MLX4_MAX_CQ_COUNT;
  499. props->cq_caps.max_cq_moderation_period = MLX4_MAX_CQ_PERIOD;
  500. if (!mlx4_is_slave(dev->dev))
  501. err = mlx4_get_internal_clock_params(dev->dev, &clock_params);
  502. if (uhw->outlen >= resp.response_length + sizeof(resp.hca_core_clock_offset)) {
  503. resp.response_length += sizeof(resp.hca_core_clock_offset);
  504. if (!err && !mlx4_is_slave(dev->dev)) {
  505. resp.comp_mask |= MLX4_IB_QUERY_DEV_RESP_MASK_CORE_CLOCK_OFFSET;
  506. resp.hca_core_clock_offset = clock_params.offset % PAGE_SIZE;
  507. }
  508. }
  509. if (uhw->outlen >= resp.response_length +
  510. sizeof(resp.max_inl_recv_sz)) {
  511. resp.response_length += sizeof(resp.max_inl_recv_sz);
  512. resp.max_inl_recv_sz = dev->dev->caps.max_rq_sg *
  513. sizeof(struct mlx4_wqe_data_seg);
  514. }
  515. if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
  516. if (props->rss_caps.supported_qpts) {
  517. resp.rss_caps.rx_hash_function =
  518. MLX4_IB_RX_HASH_FUNC_TOEPLITZ;
  519. resp.rss_caps.rx_hash_fields_mask =
  520. MLX4_IB_RX_HASH_SRC_IPV4 |
  521. MLX4_IB_RX_HASH_DST_IPV4 |
  522. MLX4_IB_RX_HASH_SRC_IPV6 |
  523. MLX4_IB_RX_HASH_DST_IPV6 |
  524. MLX4_IB_RX_HASH_SRC_PORT_TCP |
  525. MLX4_IB_RX_HASH_DST_PORT_TCP |
  526. MLX4_IB_RX_HASH_SRC_PORT_UDP |
  527. MLX4_IB_RX_HASH_DST_PORT_UDP;
  528. if (dev->dev->caps.tunnel_offload_mode ==
  529. MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
  530. resp.rss_caps.rx_hash_fields_mask |=
  531. MLX4_IB_RX_HASH_INNER;
  532. }
  533. resp.response_length = offsetof(typeof(resp), rss_caps) +
  534. sizeof(resp.rss_caps);
  535. }
  536. if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
  537. if (dev->dev->caps.max_gso_sz &&
  538. ((mlx4_ib_port_link_layer(ibdev, 1) ==
  539. IB_LINK_LAYER_ETHERNET) ||
  540. (mlx4_ib_port_link_layer(ibdev, 2) ==
  541. IB_LINK_LAYER_ETHERNET))) {
  542. resp.tso_caps.max_tso = dev->dev->caps.max_gso_sz;
  543. resp.tso_caps.supported_qpts |=
  544. 1 << IB_QPT_RAW_PACKET;
  545. }
  546. resp.response_length = offsetof(typeof(resp), tso_caps) +
  547. sizeof(resp.tso_caps);
  548. }
  549. if (uhw->outlen) {
  550. err = ib_copy_to_udata(uhw, &resp, resp.response_length);
  551. if (err)
  552. goto out;
  553. }
  554. out:
  555. kfree(in_mad);
  556. kfree(out_mad);
  557. return err;
  558. }
  559. static enum rdma_link_layer
  560. mlx4_ib_port_link_layer(struct ib_device *device, u8 port_num)
  561. {
  562. struct mlx4_dev *dev = to_mdev(device)->dev;
  563. return dev->caps.port_mask[port_num] == MLX4_PORT_TYPE_IB ?
  564. IB_LINK_LAYER_INFINIBAND : IB_LINK_LAYER_ETHERNET;
  565. }
  566. static int ib_link_query_port(struct ib_device *ibdev, u8 port,
  567. struct ib_port_attr *props, int netw_view)
  568. {
  569. struct ib_smp *in_mad = NULL;
  570. struct ib_smp *out_mad = NULL;
  571. int ext_active_speed;
  572. int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
  573. int err = -ENOMEM;
  574. in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
  575. out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
  576. if (!in_mad || !out_mad)
  577. goto out;
  578. init_query_mad(in_mad);
  579. in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
  580. in_mad->attr_mod = cpu_to_be32(port);
  581. if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view)
  582. mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
  583. err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
  584. in_mad, out_mad);
  585. if (err)
  586. goto out;
  587. props->lid = be16_to_cpup((__be16 *) (out_mad->data + 16));
  588. props->lmc = out_mad->data[34] & 0x7;
  589. props->sm_lid = be16_to_cpup((__be16 *) (out_mad->data + 18));
  590. props->sm_sl = out_mad->data[36] & 0xf;
  591. props->state = out_mad->data[32] & 0xf;
  592. props->phys_state = out_mad->data[33] >> 4;
  593. props->port_cap_flags = be32_to_cpup((__be32 *) (out_mad->data + 20));
  594. if (netw_view)
  595. props->gid_tbl_len = out_mad->data[50];
  596. else
  597. props->gid_tbl_len = to_mdev(ibdev)->dev->caps.gid_table_len[port];
  598. props->max_msg_sz = to_mdev(ibdev)->dev->caps.max_msg_sz;
  599. props->pkey_tbl_len = to_mdev(ibdev)->dev->caps.pkey_table_len[port];
  600. props->bad_pkey_cntr = be16_to_cpup((__be16 *) (out_mad->data + 46));
  601. props->qkey_viol_cntr = be16_to_cpup((__be16 *) (out_mad->data + 48));
  602. props->active_width = out_mad->data[31] & 0xf;
  603. props->active_speed = out_mad->data[35] >> 4;
  604. props->max_mtu = out_mad->data[41] & 0xf;
  605. props->active_mtu = out_mad->data[36] >> 4;
  606. props->subnet_timeout = out_mad->data[51] & 0x1f;
  607. props->max_vl_num = out_mad->data[37] >> 4;
  608. props->init_type_reply = out_mad->data[41] >> 4;
  609. /* Check if extended speeds (EDR/FDR/...) are supported */
  610. if (props->port_cap_flags & IB_PORT_EXTENDED_SPEEDS_SUP) {
  611. ext_active_speed = out_mad->data[62] >> 4;
  612. switch (ext_active_speed) {
  613. case 1:
  614. props->active_speed = IB_SPEED_FDR;
  615. break;
  616. case 2:
  617. props->active_speed = IB_SPEED_EDR;
  618. break;
  619. }
  620. }
  621. /* If reported active speed is QDR, check if is FDR-10 */
  622. if (props->active_speed == IB_SPEED_QDR) {
  623. init_query_mad(in_mad);
  624. in_mad->attr_id = MLX4_ATTR_EXTENDED_PORT_INFO;
  625. in_mad->attr_mod = cpu_to_be32(port);
  626. err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port,
  627. NULL, NULL, in_mad, out_mad);
  628. if (err)
  629. goto out;
  630. /* Checking LinkSpeedActive for FDR-10 */
  631. if (out_mad->data[15] & 0x1)
  632. props->active_speed = IB_SPEED_FDR10;
  633. }
  634. /* Avoid wrong speed value returned by FW if the IB link is down. */
  635. if (props->state == IB_PORT_DOWN)
  636. props->active_speed = IB_SPEED_SDR;
  637. out:
  638. kfree(in_mad);
  639. kfree(out_mad);
  640. return err;
  641. }
  642. static u8 state_to_phys_state(enum ib_port_state state)
  643. {
  644. return state == IB_PORT_ACTIVE ? 5 : 3;
  645. }
  646. static int eth_link_query_port(struct ib_device *ibdev, u8 port,
  647. struct ib_port_attr *props)
  648. {
  649. struct mlx4_ib_dev *mdev = to_mdev(ibdev);
  650. struct mlx4_ib_iboe *iboe = &mdev->iboe;
  651. struct net_device *ndev;
  652. enum ib_mtu tmp;
  653. struct mlx4_cmd_mailbox *mailbox;
  654. int err = 0;
  655. int is_bonded = mlx4_is_bonded(mdev->dev);
  656. mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
  657. if (IS_ERR(mailbox))
  658. return PTR_ERR(mailbox);
  659. err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0,
  660. MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
  661. MLX4_CMD_WRAPPED);
  662. if (err)
  663. goto out;
  664. props->active_width = (((u8 *)mailbox->buf)[5] == 0x40) ||
  665. (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ?
  666. IB_WIDTH_4X : IB_WIDTH_1X;
  667. props->active_speed = (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ?
  668. IB_SPEED_FDR : IB_SPEED_QDR;
  669. props->port_cap_flags = IB_PORT_CM_SUP;
  670. props->ip_gids = true;
  671. props->gid_tbl_len = mdev->dev->caps.gid_table_len[port];
  672. props->max_msg_sz = mdev->dev->caps.max_msg_sz;
  673. props->pkey_tbl_len = 1;
  674. props->max_mtu = IB_MTU_4096;
  675. props->max_vl_num = 2;
  676. props->state = IB_PORT_DOWN;
  677. props->phys_state = state_to_phys_state(props->state);
  678. props->active_mtu = IB_MTU_256;
  679. spin_lock_bh(&iboe->lock);
  680. ndev = iboe->netdevs[port - 1];
  681. if (ndev && is_bonded) {
  682. rcu_read_lock(); /* required to get upper dev */
  683. ndev = netdev_master_upper_dev_get_rcu(ndev);
  684. rcu_read_unlock();
  685. }
  686. if (!ndev)
  687. goto out_unlock;
  688. tmp = iboe_get_mtu(ndev->mtu);
  689. props->active_mtu = tmp ? min(props->max_mtu, tmp) : IB_MTU_256;
  690. props->state = (netif_running(ndev) && netif_carrier_ok(ndev)) ?
  691. IB_PORT_ACTIVE : IB_PORT_DOWN;
  692. props->phys_state = state_to_phys_state(props->state);
  693. out_unlock:
  694. spin_unlock_bh(&iboe->lock);
  695. out:
  696. mlx4_free_cmd_mailbox(mdev->dev, mailbox);
  697. return err;
  698. }
  699. int __mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
  700. struct ib_port_attr *props, int netw_view)
  701. {
  702. int err;
  703. /* props being zeroed by the caller, avoid zeroing it here */
  704. err = mlx4_ib_port_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND ?
  705. ib_link_query_port(ibdev, port, props, netw_view) :
  706. eth_link_query_port(ibdev, port, props);
  707. return err;
  708. }
  709. static int mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
  710. struct ib_port_attr *props)
  711. {
  712. /* returns host view */
  713. return __mlx4_ib_query_port(ibdev, port, props, 0);
  714. }
  715. int __mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
  716. union ib_gid *gid, int netw_view)
  717. {
  718. struct ib_smp *in_mad = NULL;
  719. struct ib_smp *out_mad = NULL;
  720. int err = -ENOMEM;
  721. struct mlx4_ib_dev *dev = to_mdev(ibdev);
  722. int clear = 0;
  723. int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
  724. in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
  725. out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
  726. if (!in_mad || !out_mad)
  727. goto out;
  728. init_query_mad(in_mad);
  729. in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
  730. in_mad->attr_mod = cpu_to_be32(port);
  731. if (mlx4_is_mfunc(dev->dev) && netw_view)
  732. mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
  733. err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, NULL, NULL, in_mad, out_mad);
  734. if (err)
  735. goto out;
  736. memcpy(gid->raw, out_mad->data + 8, 8);
  737. if (mlx4_is_mfunc(dev->dev) && !netw_view) {
  738. if (index) {
  739. /* For any index > 0, return the null guid */
  740. err = 0;
  741. clear = 1;
  742. goto out;
  743. }
  744. }
  745. init_query_mad(in_mad);
  746. in_mad->attr_id = IB_SMP_ATTR_GUID_INFO;
  747. in_mad->attr_mod = cpu_to_be32(index / 8);
  748. err = mlx4_MAD_IFC(dev, mad_ifc_flags, port,
  749. NULL, NULL, in_mad, out_mad);
  750. if (err)
  751. goto out;
  752. memcpy(gid->raw + 8, out_mad->data + (index % 8) * 8, 8);
  753. out:
  754. if (clear)
  755. memset(gid->raw + 8, 0, 8);
  756. kfree(in_mad);
  757. kfree(out_mad);
  758. return err;
  759. }
  760. static int mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
  761. union ib_gid *gid)
  762. {
  763. if (rdma_protocol_ib(ibdev, port))
  764. return __mlx4_ib_query_gid(ibdev, port, index, gid, 0);
  765. return 0;
  766. }
  767. static int mlx4_ib_query_sl2vl(struct ib_device *ibdev, u8 port, u64 *sl2vl_tbl)
  768. {
  769. union sl2vl_tbl_to_u64 sl2vl64;
  770. struct ib_smp *in_mad = NULL;
  771. struct ib_smp *out_mad = NULL;
  772. int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
  773. int err = -ENOMEM;
  774. int jj;
  775. if (mlx4_is_slave(to_mdev(ibdev)->dev)) {
  776. *sl2vl_tbl = 0;
  777. return 0;
  778. }
  779. in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL);
  780. out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
  781. if (!in_mad || !out_mad)
  782. goto out;
  783. init_query_mad(in_mad);
  784. in_mad->attr_id = IB_SMP_ATTR_SL_TO_VL_TABLE;
  785. in_mad->attr_mod = 0;
  786. if (mlx4_is_mfunc(to_mdev(ibdev)->dev))
  787. mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
  788. err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
  789. in_mad, out_mad);
  790. if (err)
  791. goto out;
  792. for (jj = 0; jj < 8; jj++)
  793. sl2vl64.sl8[jj] = ((struct ib_smp *)out_mad)->data[jj];
  794. *sl2vl_tbl = sl2vl64.sl64;
  795. out:
  796. kfree(in_mad);
  797. kfree(out_mad);
  798. return err;
  799. }
  800. static void mlx4_init_sl2vl_tbl(struct mlx4_ib_dev *mdev)
  801. {
  802. u64 sl2vl;
  803. int i;
  804. int err;
  805. for (i = 1; i <= mdev->dev->caps.num_ports; i++) {
  806. if (mdev->dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
  807. continue;
  808. err = mlx4_ib_query_sl2vl(&mdev->ib_dev, i, &sl2vl);
  809. if (err) {
  810. pr_err("Unable to get default sl to vl mapping for port %d. Using all zeroes (%d)\n",
  811. i, err);
  812. sl2vl = 0;
  813. }
  814. atomic64_set(&mdev->sl2vl[i - 1], sl2vl);
  815. }
  816. }
  817. int __mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
  818. u16 *pkey, int netw_view)
  819. {
  820. struct ib_smp *in_mad = NULL;
  821. struct ib_smp *out_mad = NULL;
  822. int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
  823. int err = -ENOMEM;
  824. in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
  825. out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
  826. if (!in_mad || !out_mad)
  827. goto out;
  828. init_query_mad(in_mad);
  829. in_mad->attr_id = IB_SMP_ATTR_PKEY_TABLE;
  830. in_mad->attr_mod = cpu_to_be32(index / 32);
  831. if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view)
  832. mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
  833. err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
  834. in_mad, out_mad);
  835. if (err)
  836. goto out;
  837. *pkey = be16_to_cpu(((__be16 *) out_mad->data)[index % 32]);
  838. out:
  839. kfree(in_mad);
  840. kfree(out_mad);
  841. return err;
  842. }
  843. static int mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, u16 *pkey)
  844. {
  845. return __mlx4_ib_query_pkey(ibdev, port, index, pkey, 0);
  846. }
  847. static int mlx4_ib_modify_device(struct ib_device *ibdev, int mask,
  848. struct ib_device_modify *props)
  849. {
  850. struct mlx4_cmd_mailbox *mailbox;
  851. unsigned long flags;
  852. if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
  853. return -EOPNOTSUPP;
  854. if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
  855. return 0;
  856. if (mlx4_is_slave(to_mdev(ibdev)->dev))
  857. return -EOPNOTSUPP;
  858. spin_lock_irqsave(&to_mdev(ibdev)->sm_lock, flags);
  859. memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
  860. spin_unlock_irqrestore(&to_mdev(ibdev)->sm_lock, flags);
  861. /*
  862. * If possible, pass node desc to FW, so it can generate
  863. * a 144 trap. If cmd fails, just ignore.
  864. */
  865. mailbox = mlx4_alloc_cmd_mailbox(to_mdev(ibdev)->dev);
  866. if (IS_ERR(mailbox))
  867. return 0;
  868. memcpy(mailbox->buf, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
  869. mlx4_cmd(to_mdev(ibdev)->dev, mailbox->dma, 1, 0,
  870. MLX4_CMD_SET_NODE, MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
  871. mlx4_free_cmd_mailbox(to_mdev(ibdev)->dev, mailbox);
  872. return 0;
  873. }
  874. static int mlx4_ib_SET_PORT(struct mlx4_ib_dev *dev, u8 port, int reset_qkey_viols,
  875. u32 cap_mask)
  876. {
  877. struct mlx4_cmd_mailbox *mailbox;
  878. int err;
  879. mailbox = mlx4_alloc_cmd_mailbox(dev->dev);
  880. if (IS_ERR(mailbox))
  881. return PTR_ERR(mailbox);
  882. if (dev->dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
  883. *(u8 *) mailbox->buf = !!reset_qkey_viols << 6;
  884. ((__be32 *) mailbox->buf)[2] = cpu_to_be32(cap_mask);
  885. } else {
  886. ((u8 *) mailbox->buf)[3] = !!reset_qkey_viols;
  887. ((__be32 *) mailbox->buf)[1] = cpu_to_be32(cap_mask);
  888. }
  889. err = mlx4_cmd(dev->dev, mailbox->dma, port, MLX4_SET_PORT_IB_OPCODE,
  890. MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
  891. MLX4_CMD_WRAPPED);
  892. mlx4_free_cmd_mailbox(dev->dev, mailbox);
  893. return err;
  894. }
  895. static int mlx4_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
  896. struct ib_port_modify *props)
  897. {
  898. struct mlx4_ib_dev *mdev = to_mdev(ibdev);
  899. u8 is_eth = mdev->dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH;
  900. struct ib_port_attr attr;
  901. u32 cap_mask;
  902. int err;
  903. /* return OK if this is RoCE. CM calls ib_modify_port() regardless
  904. * of whether port link layer is ETH or IB. For ETH ports, qkey
  905. * violations and port capabilities are not meaningful.
  906. */
  907. if (is_eth)
  908. return 0;
  909. mutex_lock(&mdev->cap_mask_mutex);
  910. err = ib_query_port(ibdev, port, &attr);
  911. if (err)
  912. goto out;
  913. cap_mask = (attr.port_cap_flags | props->set_port_cap_mask) &
  914. ~props->clr_port_cap_mask;
  915. err = mlx4_ib_SET_PORT(mdev, port,
  916. !!(mask & IB_PORT_RESET_QKEY_CNTR),
  917. cap_mask);
  918. out:
  919. mutex_unlock(&to_mdev(ibdev)->cap_mask_mutex);
  920. return err;
  921. }
  922. static struct ib_ucontext *mlx4_ib_alloc_ucontext(struct ib_device *ibdev,
  923. struct ib_udata *udata)
  924. {
  925. struct mlx4_ib_dev *dev = to_mdev(ibdev);
  926. struct mlx4_ib_ucontext *context;
  927. struct mlx4_ib_alloc_ucontext_resp_v3 resp_v3;
  928. struct mlx4_ib_alloc_ucontext_resp resp;
  929. int err;
  930. if (!dev->ib_active)
  931. return ERR_PTR(-EAGAIN);
  932. if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) {
  933. resp_v3.qp_tab_size = dev->dev->caps.num_qps;
  934. resp_v3.bf_reg_size = dev->dev->caps.bf_reg_size;
  935. resp_v3.bf_regs_per_page = dev->dev->caps.bf_regs_per_page;
  936. } else {
  937. resp.dev_caps = dev->dev->caps.userspace_caps;
  938. resp.qp_tab_size = dev->dev->caps.num_qps;
  939. resp.bf_reg_size = dev->dev->caps.bf_reg_size;
  940. resp.bf_regs_per_page = dev->dev->caps.bf_regs_per_page;
  941. resp.cqe_size = dev->dev->caps.cqe_size;
  942. }
  943. context = kzalloc(sizeof(*context), GFP_KERNEL);
  944. if (!context)
  945. return ERR_PTR(-ENOMEM);
  946. err = mlx4_uar_alloc(to_mdev(ibdev)->dev, &context->uar);
  947. if (err) {
  948. kfree(context);
  949. return ERR_PTR(err);
  950. }
  951. INIT_LIST_HEAD(&context->db_page_list);
  952. mutex_init(&context->db_page_mutex);
  953. INIT_LIST_HEAD(&context->wqn_ranges_list);
  954. mutex_init(&context->wqn_ranges_mutex);
  955. if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION)
  956. err = ib_copy_to_udata(udata, &resp_v3, sizeof(resp_v3));
  957. else
  958. err = ib_copy_to_udata(udata, &resp, sizeof(resp));
  959. if (err) {
  960. mlx4_uar_free(to_mdev(ibdev)->dev, &context->uar);
  961. kfree(context);
  962. return ERR_PTR(-EFAULT);
  963. }
  964. return &context->ibucontext;
  965. }
  966. static int mlx4_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
  967. {
  968. struct mlx4_ib_ucontext *context = to_mucontext(ibcontext);
  969. mlx4_uar_free(to_mdev(ibcontext->device)->dev, &context->uar);
  970. kfree(context);
  971. return 0;
  972. }
  973. static void mlx4_ib_vma_open(struct vm_area_struct *area)
  974. {
  975. /* vma_open is called when a new VMA is created on top of our VMA.
  976. * This is done through either mremap flow or split_vma (usually due
  977. * to mlock, madvise, munmap, etc.). We do not support a clone of the
  978. * vma, as this VMA is strongly hardware related. Therefore we set the
  979. * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
  980. * calling us again and trying to do incorrect actions. We assume that
  981. * the original vma size is exactly a single page that there will be no
  982. * "splitting" operations on.
  983. */
  984. area->vm_ops = NULL;
  985. }
  986. static void mlx4_ib_vma_close(struct vm_area_struct *area)
  987. {
  988. struct mlx4_ib_vma_private_data *mlx4_ib_vma_priv_data;
  989. /* It's guaranteed that all VMAs opened on a FD are closed before the
  990. * file itself is closed, therefore no sync is needed with the regular
  991. * closing flow. (e.g. mlx4_ib_dealloc_ucontext) However need a sync
  992. * with accessing the vma as part of mlx4_ib_disassociate_ucontext.
  993. * The close operation is usually called under mm->mmap_sem except when
  994. * process is exiting. The exiting case is handled explicitly as part
  995. * of mlx4_ib_disassociate_ucontext.
  996. */
  997. mlx4_ib_vma_priv_data = (struct mlx4_ib_vma_private_data *)
  998. area->vm_private_data;
  999. /* set the vma context pointer to null in the mlx4_ib driver's private
  1000. * data to protect against a race condition in mlx4_ib_dissassociate_ucontext().
  1001. */
  1002. mlx4_ib_vma_priv_data->vma = NULL;
  1003. }
  1004. static const struct vm_operations_struct mlx4_ib_vm_ops = {
  1005. .open = mlx4_ib_vma_open,
  1006. .close = mlx4_ib_vma_close
  1007. };
  1008. static void mlx4_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
  1009. {
  1010. int i;
  1011. struct vm_area_struct *vma;
  1012. struct mlx4_ib_ucontext *context = to_mucontext(ibcontext);
  1013. /* need to protect from a race on closing the vma as part of
  1014. * mlx4_ib_vma_close().
  1015. */
  1016. for (i = 0; i < HW_BAR_COUNT; i++) {
  1017. vma = context->hw_bar_info[i].vma;
  1018. if (!vma)
  1019. continue;
  1020. zap_vma_ptes(context->hw_bar_info[i].vma,
  1021. context->hw_bar_info[i].vma->vm_start, PAGE_SIZE);
  1022. context->hw_bar_info[i].vma->vm_flags &=
  1023. ~(VM_SHARED | VM_MAYSHARE);
  1024. /* context going to be destroyed, should not access ops any more */
  1025. context->hw_bar_info[i].vma->vm_ops = NULL;
  1026. }
  1027. }
  1028. static void mlx4_ib_set_vma_data(struct vm_area_struct *vma,
  1029. struct mlx4_ib_vma_private_data *vma_private_data)
  1030. {
  1031. vma_private_data->vma = vma;
  1032. vma->vm_private_data = vma_private_data;
  1033. vma->vm_ops = &mlx4_ib_vm_ops;
  1034. }
  1035. static int mlx4_ib_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
  1036. {
  1037. struct mlx4_ib_dev *dev = to_mdev(context->device);
  1038. struct mlx4_ib_ucontext *mucontext = to_mucontext(context);
  1039. if (vma->vm_end - vma->vm_start != PAGE_SIZE)
  1040. return -EINVAL;
  1041. if (vma->vm_pgoff == 0) {
  1042. /* We prevent double mmaping on same context */
  1043. if (mucontext->hw_bar_info[HW_BAR_DB].vma)
  1044. return -EINVAL;
  1045. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  1046. if (io_remap_pfn_range(vma, vma->vm_start,
  1047. to_mucontext(context)->uar.pfn,
  1048. PAGE_SIZE, vma->vm_page_prot))
  1049. return -EAGAIN;
  1050. mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_DB]);
  1051. } else if (vma->vm_pgoff == 1 && dev->dev->caps.bf_reg_size != 0) {
  1052. /* We prevent double mmaping on same context */
  1053. if (mucontext->hw_bar_info[HW_BAR_BF].vma)
  1054. return -EINVAL;
  1055. vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
  1056. if (io_remap_pfn_range(vma, vma->vm_start,
  1057. to_mucontext(context)->uar.pfn +
  1058. dev->dev->caps.num_uars,
  1059. PAGE_SIZE, vma->vm_page_prot))
  1060. return -EAGAIN;
  1061. mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_BF]);
  1062. } else if (vma->vm_pgoff == 3) {
  1063. struct mlx4_clock_params params;
  1064. int ret;
  1065. /* We prevent double mmaping on same context */
  1066. if (mucontext->hw_bar_info[HW_BAR_CLOCK].vma)
  1067. return -EINVAL;
  1068. ret = mlx4_get_internal_clock_params(dev->dev, &params);
  1069. if (ret)
  1070. return ret;
  1071. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  1072. if (io_remap_pfn_range(vma, vma->vm_start,
  1073. (pci_resource_start(dev->dev->persist->pdev,
  1074. params.bar) +
  1075. params.offset)
  1076. >> PAGE_SHIFT,
  1077. PAGE_SIZE, vma->vm_page_prot))
  1078. return -EAGAIN;
  1079. mlx4_ib_set_vma_data(vma,
  1080. &mucontext->hw_bar_info[HW_BAR_CLOCK]);
  1081. } else {
  1082. return -EINVAL;
  1083. }
  1084. return 0;
  1085. }
  1086. static struct ib_pd *mlx4_ib_alloc_pd(struct ib_device *ibdev,
  1087. struct ib_ucontext *context,
  1088. struct ib_udata *udata)
  1089. {
  1090. struct mlx4_ib_pd *pd;
  1091. int err;
  1092. pd = kzalloc(sizeof(*pd), GFP_KERNEL);
  1093. if (!pd)
  1094. return ERR_PTR(-ENOMEM);
  1095. err = mlx4_pd_alloc(to_mdev(ibdev)->dev, &pd->pdn);
  1096. if (err) {
  1097. kfree(pd);
  1098. return ERR_PTR(err);
  1099. }
  1100. if (context)
  1101. if (ib_copy_to_udata(udata, &pd->pdn, sizeof (__u32))) {
  1102. mlx4_pd_free(to_mdev(ibdev)->dev, pd->pdn);
  1103. kfree(pd);
  1104. return ERR_PTR(-EFAULT);
  1105. }
  1106. return &pd->ibpd;
  1107. }
  1108. static int mlx4_ib_dealloc_pd(struct ib_pd *pd)
  1109. {
  1110. mlx4_pd_free(to_mdev(pd->device)->dev, to_mpd(pd)->pdn);
  1111. kfree(pd);
  1112. return 0;
  1113. }
  1114. static struct ib_xrcd *mlx4_ib_alloc_xrcd(struct ib_device *ibdev,
  1115. struct ib_ucontext *context,
  1116. struct ib_udata *udata)
  1117. {
  1118. struct mlx4_ib_xrcd *xrcd;
  1119. struct ib_cq_init_attr cq_attr = {};
  1120. int err;
  1121. if (!(to_mdev(ibdev)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
  1122. return ERR_PTR(-ENOSYS);
  1123. xrcd = kmalloc(sizeof *xrcd, GFP_KERNEL);
  1124. if (!xrcd)
  1125. return ERR_PTR(-ENOMEM);
  1126. err = mlx4_xrcd_alloc(to_mdev(ibdev)->dev, &xrcd->xrcdn);
  1127. if (err)
  1128. goto err1;
  1129. xrcd->pd = ib_alloc_pd(ibdev, 0);
  1130. if (IS_ERR(xrcd->pd)) {
  1131. err = PTR_ERR(xrcd->pd);
  1132. goto err2;
  1133. }
  1134. cq_attr.cqe = 1;
  1135. xrcd->cq = ib_create_cq(ibdev, NULL, NULL, xrcd, &cq_attr);
  1136. if (IS_ERR(xrcd->cq)) {
  1137. err = PTR_ERR(xrcd->cq);
  1138. goto err3;
  1139. }
  1140. return &xrcd->ibxrcd;
  1141. err3:
  1142. ib_dealloc_pd(xrcd->pd);
  1143. err2:
  1144. mlx4_xrcd_free(to_mdev(ibdev)->dev, xrcd->xrcdn);
  1145. err1:
  1146. kfree(xrcd);
  1147. return ERR_PTR(err);
  1148. }
  1149. static int mlx4_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
  1150. {
  1151. ib_destroy_cq(to_mxrcd(xrcd)->cq);
  1152. ib_dealloc_pd(to_mxrcd(xrcd)->pd);
  1153. mlx4_xrcd_free(to_mdev(xrcd->device)->dev, to_mxrcd(xrcd)->xrcdn);
  1154. kfree(xrcd);
  1155. return 0;
  1156. }
  1157. static int add_gid_entry(struct ib_qp *ibqp, union ib_gid *gid)
  1158. {
  1159. struct mlx4_ib_qp *mqp = to_mqp(ibqp);
  1160. struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
  1161. struct mlx4_ib_gid_entry *ge;
  1162. ge = kzalloc(sizeof *ge, GFP_KERNEL);
  1163. if (!ge)
  1164. return -ENOMEM;
  1165. ge->gid = *gid;
  1166. if (mlx4_ib_add_mc(mdev, mqp, gid)) {
  1167. ge->port = mqp->port;
  1168. ge->added = 1;
  1169. }
  1170. mutex_lock(&mqp->mutex);
  1171. list_add_tail(&ge->list, &mqp->gid_list);
  1172. mutex_unlock(&mqp->mutex);
  1173. return 0;
  1174. }
  1175. static void mlx4_ib_delete_counters_table(struct mlx4_ib_dev *ibdev,
  1176. struct mlx4_ib_counters *ctr_table)
  1177. {
  1178. struct counter_index *counter, *tmp_count;
  1179. mutex_lock(&ctr_table->mutex);
  1180. list_for_each_entry_safe(counter, tmp_count, &ctr_table->counters_list,
  1181. list) {
  1182. if (counter->allocated)
  1183. mlx4_counter_free(ibdev->dev, counter->index);
  1184. list_del(&counter->list);
  1185. kfree(counter);
  1186. }
  1187. mutex_unlock(&ctr_table->mutex);
  1188. }
  1189. int mlx4_ib_add_mc(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
  1190. union ib_gid *gid)
  1191. {
  1192. struct net_device *ndev;
  1193. int ret = 0;
  1194. if (!mqp->port)
  1195. return 0;
  1196. spin_lock_bh(&mdev->iboe.lock);
  1197. ndev = mdev->iboe.netdevs[mqp->port - 1];
  1198. if (ndev)
  1199. dev_hold(ndev);
  1200. spin_unlock_bh(&mdev->iboe.lock);
  1201. if (ndev) {
  1202. ret = 1;
  1203. dev_put(ndev);
  1204. }
  1205. return ret;
  1206. }
  1207. struct mlx4_ib_steering {
  1208. struct list_head list;
  1209. struct mlx4_flow_reg_id reg_id;
  1210. union ib_gid gid;
  1211. };
  1212. #define LAST_ETH_FIELD vlan_tag
  1213. #define LAST_IB_FIELD sl
  1214. #define LAST_IPV4_FIELD dst_ip
  1215. #define LAST_TCP_UDP_FIELD src_port
  1216. /* Field is the last supported field */
  1217. #define FIELDS_NOT_SUPPORTED(filter, field)\
  1218. memchr_inv((void *)&filter.field +\
  1219. sizeof(filter.field), 0,\
  1220. sizeof(filter) -\
  1221. offsetof(typeof(filter), field) -\
  1222. sizeof(filter.field))
  1223. static int parse_flow_attr(struct mlx4_dev *dev,
  1224. u32 qp_num,
  1225. union ib_flow_spec *ib_spec,
  1226. struct _rule_hw *mlx4_spec)
  1227. {
  1228. enum mlx4_net_trans_rule_id type;
  1229. switch (ib_spec->type) {
  1230. case IB_FLOW_SPEC_ETH:
  1231. if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
  1232. return -ENOTSUPP;
  1233. type = MLX4_NET_TRANS_RULE_ID_ETH;
  1234. memcpy(mlx4_spec->eth.dst_mac, ib_spec->eth.val.dst_mac,
  1235. ETH_ALEN);
  1236. memcpy(mlx4_spec->eth.dst_mac_msk, ib_spec->eth.mask.dst_mac,
  1237. ETH_ALEN);
  1238. mlx4_spec->eth.vlan_tag = ib_spec->eth.val.vlan_tag;
  1239. mlx4_spec->eth.vlan_tag_msk = ib_spec->eth.mask.vlan_tag;
  1240. break;
  1241. case IB_FLOW_SPEC_IB:
  1242. if (FIELDS_NOT_SUPPORTED(ib_spec->ib.mask, LAST_IB_FIELD))
  1243. return -ENOTSUPP;
  1244. type = MLX4_NET_TRANS_RULE_ID_IB;
  1245. mlx4_spec->ib.l3_qpn =
  1246. cpu_to_be32(qp_num);
  1247. mlx4_spec->ib.qpn_mask =
  1248. cpu_to_be32(MLX4_IB_FLOW_QPN_MASK);
  1249. break;
  1250. case IB_FLOW_SPEC_IPV4:
  1251. if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
  1252. return -ENOTSUPP;
  1253. type = MLX4_NET_TRANS_RULE_ID_IPV4;
  1254. mlx4_spec->ipv4.src_ip = ib_spec->ipv4.val.src_ip;
  1255. mlx4_spec->ipv4.src_ip_msk = ib_spec->ipv4.mask.src_ip;
  1256. mlx4_spec->ipv4.dst_ip = ib_spec->ipv4.val.dst_ip;
  1257. mlx4_spec->ipv4.dst_ip_msk = ib_spec->ipv4.mask.dst_ip;
  1258. break;
  1259. case IB_FLOW_SPEC_TCP:
  1260. case IB_FLOW_SPEC_UDP:
  1261. if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, LAST_TCP_UDP_FIELD))
  1262. return -ENOTSUPP;
  1263. type = ib_spec->type == IB_FLOW_SPEC_TCP ?
  1264. MLX4_NET_TRANS_RULE_ID_TCP :
  1265. MLX4_NET_TRANS_RULE_ID_UDP;
  1266. mlx4_spec->tcp_udp.dst_port = ib_spec->tcp_udp.val.dst_port;
  1267. mlx4_spec->tcp_udp.dst_port_msk = ib_spec->tcp_udp.mask.dst_port;
  1268. mlx4_spec->tcp_udp.src_port = ib_spec->tcp_udp.val.src_port;
  1269. mlx4_spec->tcp_udp.src_port_msk = ib_spec->tcp_udp.mask.src_port;
  1270. break;
  1271. default:
  1272. return -EINVAL;
  1273. }
  1274. if (mlx4_map_sw_to_hw_steering_id(dev, type) < 0 ||
  1275. mlx4_hw_rule_sz(dev, type) < 0)
  1276. return -EINVAL;
  1277. mlx4_spec->id = cpu_to_be16(mlx4_map_sw_to_hw_steering_id(dev, type));
  1278. mlx4_spec->size = mlx4_hw_rule_sz(dev, type) >> 2;
  1279. return mlx4_hw_rule_sz(dev, type);
  1280. }
  1281. struct default_rules {
  1282. __u32 mandatory_fields[IB_FLOW_SPEC_SUPPORT_LAYERS];
  1283. __u32 mandatory_not_fields[IB_FLOW_SPEC_SUPPORT_LAYERS];
  1284. __u32 rules_create_list[IB_FLOW_SPEC_SUPPORT_LAYERS];
  1285. __u8 link_layer;
  1286. };
  1287. static const struct default_rules default_table[] = {
  1288. {
  1289. .mandatory_fields = {IB_FLOW_SPEC_IPV4},
  1290. .mandatory_not_fields = {IB_FLOW_SPEC_ETH},
  1291. .rules_create_list = {IB_FLOW_SPEC_IB},
  1292. .link_layer = IB_LINK_LAYER_INFINIBAND
  1293. }
  1294. };
  1295. static int __mlx4_ib_default_rules_match(struct ib_qp *qp,
  1296. struct ib_flow_attr *flow_attr)
  1297. {
  1298. int i, j, k;
  1299. void *ib_flow;
  1300. const struct default_rules *pdefault_rules = default_table;
  1301. u8 link_layer = rdma_port_get_link_layer(qp->device, flow_attr->port);
  1302. for (i = 0; i < ARRAY_SIZE(default_table); i++, pdefault_rules++) {
  1303. __u32 field_types[IB_FLOW_SPEC_SUPPORT_LAYERS];
  1304. memset(&field_types, 0, sizeof(field_types));
  1305. if (link_layer != pdefault_rules->link_layer)
  1306. continue;
  1307. ib_flow = flow_attr + 1;
  1308. /* we assume the specs are sorted */
  1309. for (j = 0, k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS &&
  1310. j < flow_attr->num_of_specs; k++) {
  1311. union ib_flow_spec *current_flow =
  1312. (union ib_flow_spec *)ib_flow;
  1313. /* same layer but different type */
  1314. if (((current_flow->type & IB_FLOW_SPEC_LAYER_MASK) ==
  1315. (pdefault_rules->mandatory_fields[k] &
  1316. IB_FLOW_SPEC_LAYER_MASK)) &&
  1317. (current_flow->type !=
  1318. pdefault_rules->mandatory_fields[k]))
  1319. goto out;
  1320. /* same layer, try match next one */
  1321. if (current_flow->type ==
  1322. pdefault_rules->mandatory_fields[k]) {
  1323. j++;
  1324. ib_flow +=
  1325. ((union ib_flow_spec *)ib_flow)->size;
  1326. }
  1327. }
  1328. ib_flow = flow_attr + 1;
  1329. for (j = 0; j < flow_attr->num_of_specs;
  1330. j++, ib_flow += ((union ib_flow_spec *)ib_flow)->size)
  1331. for (k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS; k++)
  1332. /* same layer and same type */
  1333. if (((union ib_flow_spec *)ib_flow)->type ==
  1334. pdefault_rules->mandatory_not_fields[k])
  1335. goto out;
  1336. return i;
  1337. }
  1338. out:
  1339. return -1;
  1340. }
  1341. static int __mlx4_ib_create_default_rules(
  1342. struct mlx4_ib_dev *mdev,
  1343. struct ib_qp *qp,
  1344. const struct default_rules *pdefault_rules,
  1345. struct _rule_hw *mlx4_spec) {
  1346. int size = 0;
  1347. int i;
  1348. for (i = 0; i < ARRAY_SIZE(pdefault_rules->rules_create_list); i++) {
  1349. int ret;
  1350. union ib_flow_spec ib_spec;
  1351. switch (pdefault_rules->rules_create_list[i]) {
  1352. case 0:
  1353. /* no rule */
  1354. continue;
  1355. case IB_FLOW_SPEC_IB:
  1356. ib_spec.type = IB_FLOW_SPEC_IB;
  1357. ib_spec.size = sizeof(struct ib_flow_spec_ib);
  1358. break;
  1359. default:
  1360. /* invalid rule */
  1361. return -EINVAL;
  1362. }
  1363. /* We must put empty rule, qpn is being ignored */
  1364. ret = parse_flow_attr(mdev->dev, 0, &ib_spec,
  1365. mlx4_spec);
  1366. if (ret < 0) {
  1367. pr_info("invalid parsing\n");
  1368. return -EINVAL;
  1369. }
  1370. mlx4_spec = (void *)mlx4_spec + ret;
  1371. size += ret;
  1372. }
  1373. return size;
  1374. }
  1375. static int __mlx4_ib_create_flow(struct ib_qp *qp, struct ib_flow_attr *flow_attr,
  1376. int domain,
  1377. enum mlx4_net_trans_promisc_mode flow_type,
  1378. u64 *reg_id)
  1379. {
  1380. int ret, i;
  1381. int size = 0;
  1382. void *ib_flow;
  1383. struct mlx4_ib_dev *mdev = to_mdev(qp->device);
  1384. struct mlx4_cmd_mailbox *mailbox;
  1385. struct mlx4_net_trans_rule_hw_ctrl *ctrl;
  1386. int default_flow;
  1387. static const u16 __mlx4_domain[] = {
  1388. [IB_FLOW_DOMAIN_USER] = MLX4_DOMAIN_UVERBS,
  1389. [IB_FLOW_DOMAIN_ETHTOOL] = MLX4_DOMAIN_ETHTOOL,
  1390. [IB_FLOW_DOMAIN_RFS] = MLX4_DOMAIN_RFS,
  1391. [IB_FLOW_DOMAIN_NIC] = MLX4_DOMAIN_NIC,
  1392. };
  1393. if (flow_attr->priority > MLX4_IB_FLOW_MAX_PRIO) {
  1394. pr_err("Invalid priority value %d\n", flow_attr->priority);
  1395. return -EINVAL;
  1396. }
  1397. if (domain >= IB_FLOW_DOMAIN_NUM) {
  1398. pr_err("Invalid domain value %d\n", domain);
  1399. return -EINVAL;
  1400. }
  1401. if (mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type) < 0)
  1402. return -EINVAL;
  1403. mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
  1404. if (IS_ERR(mailbox))
  1405. return PTR_ERR(mailbox);
  1406. ctrl = mailbox->buf;
  1407. ctrl->prio = cpu_to_be16(__mlx4_domain[domain] |
  1408. flow_attr->priority);
  1409. ctrl->type = mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type);
  1410. ctrl->port = flow_attr->port;
  1411. ctrl->qpn = cpu_to_be32(qp->qp_num);
  1412. ib_flow = flow_attr + 1;
  1413. size += sizeof(struct mlx4_net_trans_rule_hw_ctrl);
  1414. /* Add default flows */
  1415. default_flow = __mlx4_ib_default_rules_match(qp, flow_attr);
  1416. if (default_flow >= 0) {
  1417. ret = __mlx4_ib_create_default_rules(
  1418. mdev, qp, default_table + default_flow,
  1419. mailbox->buf + size);
  1420. if (ret < 0) {
  1421. mlx4_free_cmd_mailbox(mdev->dev, mailbox);
  1422. return -EINVAL;
  1423. }
  1424. size += ret;
  1425. }
  1426. for (i = 0; i < flow_attr->num_of_specs; i++) {
  1427. ret = parse_flow_attr(mdev->dev, qp->qp_num, ib_flow,
  1428. mailbox->buf + size);
  1429. if (ret < 0) {
  1430. mlx4_free_cmd_mailbox(mdev->dev, mailbox);
  1431. return -EINVAL;
  1432. }
  1433. ib_flow += ((union ib_flow_spec *) ib_flow)->size;
  1434. size += ret;
  1435. }
  1436. if (mlx4_is_master(mdev->dev) && flow_type == MLX4_FS_REGULAR &&
  1437. flow_attr->num_of_specs == 1) {
  1438. struct _rule_hw *rule_header = (struct _rule_hw *)(ctrl + 1);
  1439. enum ib_flow_spec_type header_spec =
  1440. ((union ib_flow_spec *)(flow_attr + 1))->type;
  1441. if (header_spec == IB_FLOW_SPEC_ETH)
  1442. mlx4_handle_eth_header_mcast_prio(ctrl, rule_header);
  1443. }
  1444. ret = mlx4_cmd_imm(mdev->dev, mailbox->dma, reg_id, size >> 2, 0,
  1445. MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
  1446. MLX4_CMD_NATIVE);
  1447. if (ret == -ENOMEM)
  1448. pr_err("mcg table is full. Fail to register network rule.\n");
  1449. else if (ret == -ENXIO)
  1450. pr_err("Device managed flow steering is disabled. Fail to register network rule.\n");
  1451. else if (ret)
  1452. pr_err("Invalid argument. Fail to register network rule.\n");
  1453. mlx4_free_cmd_mailbox(mdev->dev, mailbox);
  1454. return ret;
  1455. }
  1456. static int __mlx4_ib_destroy_flow(struct mlx4_dev *dev, u64 reg_id)
  1457. {
  1458. int err;
  1459. err = mlx4_cmd(dev, reg_id, 0, 0,
  1460. MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
  1461. MLX4_CMD_NATIVE);
  1462. if (err)
  1463. pr_err("Fail to detach network rule. registration id = 0x%llx\n",
  1464. reg_id);
  1465. return err;
  1466. }
  1467. static int mlx4_ib_tunnel_steer_add(struct ib_qp *qp, struct ib_flow_attr *flow_attr,
  1468. u64 *reg_id)
  1469. {
  1470. void *ib_flow;
  1471. union ib_flow_spec *ib_spec;
  1472. struct mlx4_dev *dev = to_mdev(qp->device)->dev;
  1473. int err = 0;
  1474. if (dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN ||
  1475. dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC)
  1476. return 0; /* do nothing */
  1477. ib_flow = flow_attr + 1;
  1478. ib_spec = (union ib_flow_spec *)ib_flow;
  1479. if (ib_spec->type != IB_FLOW_SPEC_ETH || flow_attr->num_of_specs != 1)
  1480. return 0; /* do nothing */
  1481. err = mlx4_tunnel_steer_add(to_mdev(qp->device)->dev, ib_spec->eth.val.dst_mac,
  1482. flow_attr->port, qp->qp_num,
  1483. MLX4_DOMAIN_UVERBS | (flow_attr->priority & 0xff),
  1484. reg_id);
  1485. return err;
  1486. }
  1487. static int mlx4_ib_add_dont_trap_rule(struct mlx4_dev *dev,
  1488. struct ib_flow_attr *flow_attr,
  1489. enum mlx4_net_trans_promisc_mode *type)
  1490. {
  1491. int err = 0;
  1492. if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER) ||
  1493. (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC) ||
  1494. (flow_attr->num_of_specs > 1) || (flow_attr->priority != 0)) {
  1495. return -EOPNOTSUPP;
  1496. }
  1497. if (flow_attr->num_of_specs == 0) {
  1498. type[0] = MLX4_FS_MC_SNIFFER;
  1499. type[1] = MLX4_FS_UC_SNIFFER;
  1500. } else {
  1501. union ib_flow_spec *ib_spec;
  1502. ib_spec = (union ib_flow_spec *)(flow_attr + 1);
  1503. if (ib_spec->type != IB_FLOW_SPEC_ETH)
  1504. return -EINVAL;
  1505. /* if all is zero than MC and UC */
  1506. if (is_zero_ether_addr(ib_spec->eth.mask.dst_mac)) {
  1507. type[0] = MLX4_FS_MC_SNIFFER;
  1508. type[1] = MLX4_FS_UC_SNIFFER;
  1509. } else {
  1510. u8 mac[ETH_ALEN] = {ib_spec->eth.mask.dst_mac[0] ^ 0x01,
  1511. ib_spec->eth.mask.dst_mac[1],
  1512. ib_spec->eth.mask.dst_mac[2],
  1513. ib_spec->eth.mask.dst_mac[3],
  1514. ib_spec->eth.mask.dst_mac[4],
  1515. ib_spec->eth.mask.dst_mac[5]};
  1516. /* Above xor was only on MC bit, non empty mask is valid
  1517. * only if this bit is set and rest are zero.
  1518. */
  1519. if (!is_zero_ether_addr(&mac[0]))
  1520. return -EINVAL;
  1521. if (is_multicast_ether_addr(ib_spec->eth.val.dst_mac))
  1522. type[0] = MLX4_FS_MC_SNIFFER;
  1523. else
  1524. type[0] = MLX4_FS_UC_SNIFFER;
  1525. }
  1526. }
  1527. return err;
  1528. }
  1529. static struct ib_flow *mlx4_ib_create_flow(struct ib_qp *qp,
  1530. struct ib_flow_attr *flow_attr,
  1531. int domain, struct ib_udata *udata)
  1532. {
  1533. int err = 0, i = 0, j = 0;
  1534. struct mlx4_ib_flow *mflow;
  1535. enum mlx4_net_trans_promisc_mode type[2];
  1536. struct mlx4_dev *dev = (to_mdev(qp->device))->dev;
  1537. int is_bonded = mlx4_is_bonded(dev);
  1538. if (flow_attr->port < 1 || flow_attr->port > qp->device->phys_port_cnt)
  1539. return ERR_PTR(-EINVAL);
  1540. if (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP)
  1541. return ERR_PTR(-EOPNOTSUPP);
  1542. if ((flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) &&
  1543. (flow_attr->type != IB_FLOW_ATTR_NORMAL))
  1544. return ERR_PTR(-EOPNOTSUPP);
  1545. if (udata &&
  1546. udata->inlen && !ib_is_udata_cleared(udata, 0, udata->inlen))
  1547. return ERR_PTR(-EOPNOTSUPP);
  1548. memset(type, 0, sizeof(type));
  1549. mflow = kzalloc(sizeof(*mflow), GFP_KERNEL);
  1550. if (!mflow) {
  1551. err = -ENOMEM;
  1552. goto err_free;
  1553. }
  1554. switch (flow_attr->type) {
  1555. case IB_FLOW_ATTR_NORMAL:
  1556. /* If dont trap flag (continue match) is set, under specific
  1557. * condition traffic be replicated to given qp,
  1558. * without stealing it
  1559. */
  1560. if (unlikely(flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)) {
  1561. err = mlx4_ib_add_dont_trap_rule(dev,
  1562. flow_attr,
  1563. type);
  1564. if (err)
  1565. goto err_free;
  1566. } else {
  1567. type[0] = MLX4_FS_REGULAR;
  1568. }
  1569. break;
  1570. case IB_FLOW_ATTR_ALL_DEFAULT:
  1571. type[0] = MLX4_FS_ALL_DEFAULT;
  1572. break;
  1573. case IB_FLOW_ATTR_MC_DEFAULT:
  1574. type[0] = MLX4_FS_MC_DEFAULT;
  1575. break;
  1576. case IB_FLOW_ATTR_SNIFFER:
  1577. type[0] = MLX4_FS_MIRROR_RX_PORT;
  1578. type[1] = MLX4_FS_MIRROR_SX_PORT;
  1579. break;
  1580. default:
  1581. err = -EINVAL;
  1582. goto err_free;
  1583. }
  1584. while (i < ARRAY_SIZE(type) && type[i]) {
  1585. err = __mlx4_ib_create_flow(qp, flow_attr, domain, type[i],
  1586. &mflow->reg_id[i].id);
  1587. if (err)
  1588. goto err_create_flow;
  1589. if (is_bonded) {
  1590. /* Application always sees one port so the mirror rule
  1591. * must be on port #2
  1592. */
  1593. flow_attr->port = 2;
  1594. err = __mlx4_ib_create_flow(qp, flow_attr,
  1595. domain, type[j],
  1596. &mflow->reg_id[j].mirror);
  1597. flow_attr->port = 1;
  1598. if (err)
  1599. goto err_create_flow;
  1600. j++;
  1601. }
  1602. i++;
  1603. }
  1604. if (i < ARRAY_SIZE(type) && flow_attr->type == IB_FLOW_ATTR_NORMAL) {
  1605. err = mlx4_ib_tunnel_steer_add(qp, flow_attr,
  1606. &mflow->reg_id[i].id);
  1607. if (err)
  1608. goto err_create_flow;
  1609. if (is_bonded) {
  1610. flow_attr->port = 2;
  1611. err = mlx4_ib_tunnel_steer_add(qp, flow_attr,
  1612. &mflow->reg_id[j].mirror);
  1613. flow_attr->port = 1;
  1614. if (err)
  1615. goto err_create_flow;
  1616. j++;
  1617. }
  1618. /* function to create mirror rule */
  1619. i++;
  1620. }
  1621. return &mflow->ibflow;
  1622. err_create_flow:
  1623. while (i) {
  1624. (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev,
  1625. mflow->reg_id[i].id);
  1626. i--;
  1627. }
  1628. while (j) {
  1629. (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev,
  1630. mflow->reg_id[j].mirror);
  1631. j--;
  1632. }
  1633. err_free:
  1634. kfree(mflow);
  1635. return ERR_PTR(err);
  1636. }
  1637. static int mlx4_ib_destroy_flow(struct ib_flow *flow_id)
  1638. {
  1639. int err, ret = 0;
  1640. int i = 0;
  1641. struct mlx4_ib_dev *mdev = to_mdev(flow_id->qp->device);
  1642. struct mlx4_ib_flow *mflow = to_mflow(flow_id);
  1643. while (i < ARRAY_SIZE(mflow->reg_id) && mflow->reg_id[i].id) {
  1644. err = __mlx4_ib_destroy_flow(mdev->dev, mflow->reg_id[i].id);
  1645. if (err)
  1646. ret = err;
  1647. if (mflow->reg_id[i].mirror) {
  1648. err = __mlx4_ib_destroy_flow(mdev->dev,
  1649. mflow->reg_id[i].mirror);
  1650. if (err)
  1651. ret = err;
  1652. }
  1653. i++;
  1654. }
  1655. kfree(mflow);
  1656. return ret;
  1657. }
  1658. static int mlx4_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
  1659. {
  1660. int err;
  1661. struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
  1662. struct mlx4_dev *dev = mdev->dev;
  1663. struct mlx4_ib_qp *mqp = to_mqp(ibqp);
  1664. struct mlx4_ib_steering *ib_steering = NULL;
  1665. enum mlx4_protocol prot = MLX4_PROT_IB_IPV6;
  1666. struct mlx4_flow_reg_id reg_id;
  1667. if (mdev->dev->caps.steering_mode ==
  1668. MLX4_STEERING_MODE_DEVICE_MANAGED) {
  1669. ib_steering = kmalloc(sizeof(*ib_steering), GFP_KERNEL);
  1670. if (!ib_steering)
  1671. return -ENOMEM;
  1672. }
  1673. err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, mqp->port,
  1674. !!(mqp->flags &
  1675. MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK),
  1676. prot, &reg_id.id);
  1677. if (err) {
  1678. pr_err("multicast attach op failed, err %d\n", err);
  1679. goto err_malloc;
  1680. }
  1681. reg_id.mirror = 0;
  1682. if (mlx4_is_bonded(dev)) {
  1683. err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw,
  1684. (mqp->port == 1) ? 2 : 1,
  1685. !!(mqp->flags &
  1686. MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK),
  1687. prot, &reg_id.mirror);
  1688. if (err)
  1689. goto err_add;
  1690. }
  1691. err = add_gid_entry(ibqp, gid);
  1692. if (err)
  1693. goto err_add;
  1694. if (ib_steering) {
  1695. memcpy(ib_steering->gid.raw, gid->raw, 16);
  1696. ib_steering->reg_id = reg_id;
  1697. mutex_lock(&mqp->mutex);
  1698. list_add(&ib_steering->list, &mqp->steering_rules);
  1699. mutex_unlock(&mqp->mutex);
  1700. }
  1701. return 0;
  1702. err_add:
  1703. mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
  1704. prot, reg_id.id);
  1705. if (reg_id.mirror)
  1706. mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
  1707. prot, reg_id.mirror);
  1708. err_malloc:
  1709. kfree(ib_steering);
  1710. return err;
  1711. }
  1712. static struct mlx4_ib_gid_entry *find_gid_entry(struct mlx4_ib_qp *qp, u8 *raw)
  1713. {
  1714. struct mlx4_ib_gid_entry *ge;
  1715. struct mlx4_ib_gid_entry *tmp;
  1716. struct mlx4_ib_gid_entry *ret = NULL;
  1717. list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
  1718. if (!memcmp(raw, ge->gid.raw, 16)) {
  1719. ret = ge;
  1720. break;
  1721. }
  1722. }
  1723. return ret;
  1724. }
  1725. static int mlx4_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
  1726. {
  1727. int err;
  1728. struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
  1729. struct mlx4_dev *dev = mdev->dev;
  1730. struct mlx4_ib_qp *mqp = to_mqp(ibqp);
  1731. struct net_device *ndev;
  1732. struct mlx4_ib_gid_entry *ge;
  1733. struct mlx4_flow_reg_id reg_id = {0, 0};
  1734. enum mlx4_protocol prot = MLX4_PROT_IB_IPV6;
  1735. if (mdev->dev->caps.steering_mode ==
  1736. MLX4_STEERING_MODE_DEVICE_MANAGED) {
  1737. struct mlx4_ib_steering *ib_steering;
  1738. mutex_lock(&mqp->mutex);
  1739. list_for_each_entry(ib_steering, &mqp->steering_rules, list) {
  1740. if (!memcmp(ib_steering->gid.raw, gid->raw, 16)) {
  1741. list_del(&ib_steering->list);
  1742. break;
  1743. }
  1744. }
  1745. mutex_unlock(&mqp->mutex);
  1746. if (&ib_steering->list == &mqp->steering_rules) {
  1747. pr_err("Couldn't find reg_id for mgid. Steering rule is left attached\n");
  1748. return -EINVAL;
  1749. }
  1750. reg_id = ib_steering->reg_id;
  1751. kfree(ib_steering);
  1752. }
  1753. err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
  1754. prot, reg_id.id);
  1755. if (err)
  1756. return err;
  1757. if (mlx4_is_bonded(dev)) {
  1758. err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
  1759. prot, reg_id.mirror);
  1760. if (err)
  1761. return err;
  1762. }
  1763. mutex_lock(&mqp->mutex);
  1764. ge = find_gid_entry(mqp, gid->raw);
  1765. if (ge) {
  1766. spin_lock_bh(&mdev->iboe.lock);
  1767. ndev = ge->added ? mdev->iboe.netdevs[ge->port - 1] : NULL;
  1768. if (ndev)
  1769. dev_hold(ndev);
  1770. spin_unlock_bh(&mdev->iboe.lock);
  1771. if (ndev)
  1772. dev_put(ndev);
  1773. list_del(&ge->list);
  1774. kfree(ge);
  1775. } else
  1776. pr_warn("could not find mgid entry\n");
  1777. mutex_unlock(&mqp->mutex);
  1778. return 0;
  1779. }
  1780. static int init_node_data(struct mlx4_ib_dev *dev)
  1781. {
  1782. struct ib_smp *in_mad = NULL;
  1783. struct ib_smp *out_mad = NULL;
  1784. int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
  1785. int err = -ENOMEM;
  1786. in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
  1787. out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
  1788. if (!in_mad || !out_mad)
  1789. goto out;
  1790. init_query_mad(in_mad);
  1791. in_mad->attr_id = IB_SMP_ATTR_NODE_DESC;
  1792. if (mlx4_is_master(dev->dev))
  1793. mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
  1794. err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad);
  1795. if (err)
  1796. goto out;
  1797. memcpy(dev->ib_dev.node_desc, out_mad->data, IB_DEVICE_NODE_DESC_MAX);
  1798. in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
  1799. err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad);
  1800. if (err)
  1801. goto out;
  1802. dev->dev->rev_id = be32_to_cpup((__be32 *) (out_mad->data + 32));
  1803. memcpy(&dev->ib_dev.node_guid, out_mad->data + 12, 8);
  1804. out:
  1805. kfree(in_mad);
  1806. kfree(out_mad);
  1807. return err;
  1808. }
  1809. static ssize_t show_hca(struct device *device, struct device_attribute *attr,
  1810. char *buf)
  1811. {
  1812. struct mlx4_ib_dev *dev =
  1813. container_of(device, struct mlx4_ib_dev, ib_dev.dev);
  1814. return sprintf(buf, "MT%d\n", dev->dev->persist->pdev->device);
  1815. }
  1816. static ssize_t show_rev(struct device *device, struct device_attribute *attr,
  1817. char *buf)
  1818. {
  1819. struct mlx4_ib_dev *dev =
  1820. container_of(device, struct mlx4_ib_dev, ib_dev.dev);
  1821. return sprintf(buf, "%x\n", dev->dev->rev_id);
  1822. }
  1823. static ssize_t show_board(struct device *device, struct device_attribute *attr,
  1824. char *buf)
  1825. {
  1826. struct mlx4_ib_dev *dev =
  1827. container_of(device, struct mlx4_ib_dev, ib_dev.dev);
  1828. return sprintf(buf, "%.*s\n", MLX4_BOARD_ID_LEN,
  1829. dev->dev->board_id);
  1830. }
  1831. static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
  1832. static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
  1833. static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
  1834. static struct device_attribute *mlx4_class_attributes[] = {
  1835. &dev_attr_hw_rev,
  1836. &dev_attr_hca_type,
  1837. &dev_attr_board_id
  1838. };
  1839. struct diag_counter {
  1840. const char *name;
  1841. u32 offset;
  1842. };
  1843. #define DIAG_COUNTER(_name, _offset) \
  1844. { .name = #_name, .offset = _offset }
  1845. static const struct diag_counter diag_basic[] = {
  1846. DIAG_COUNTER(rq_num_lle, 0x00),
  1847. DIAG_COUNTER(sq_num_lle, 0x04),
  1848. DIAG_COUNTER(rq_num_lqpoe, 0x08),
  1849. DIAG_COUNTER(sq_num_lqpoe, 0x0C),
  1850. DIAG_COUNTER(rq_num_lpe, 0x18),
  1851. DIAG_COUNTER(sq_num_lpe, 0x1C),
  1852. DIAG_COUNTER(rq_num_wrfe, 0x20),
  1853. DIAG_COUNTER(sq_num_wrfe, 0x24),
  1854. DIAG_COUNTER(sq_num_mwbe, 0x2C),
  1855. DIAG_COUNTER(sq_num_bre, 0x34),
  1856. DIAG_COUNTER(sq_num_rire, 0x44),
  1857. DIAG_COUNTER(rq_num_rire, 0x48),
  1858. DIAG_COUNTER(sq_num_rae, 0x4C),
  1859. DIAG_COUNTER(rq_num_rae, 0x50),
  1860. DIAG_COUNTER(sq_num_roe, 0x54),
  1861. DIAG_COUNTER(sq_num_tree, 0x5C),
  1862. DIAG_COUNTER(sq_num_rree, 0x64),
  1863. DIAG_COUNTER(rq_num_rnr, 0x68),
  1864. DIAG_COUNTER(sq_num_rnr, 0x6C),
  1865. DIAG_COUNTER(rq_num_oos, 0x100),
  1866. DIAG_COUNTER(sq_num_oos, 0x104),
  1867. };
  1868. static const struct diag_counter diag_ext[] = {
  1869. DIAG_COUNTER(rq_num_dup, 0x130),
  1870. DIAG_COUNTER(sq_num_to, 0x134),
  1871. };
  1872. static const struct diag_counter diag_device_only[] = {
  1873. DIAG_COUNTER(num_cqovf, 0x1A0),
  1874. DIAG_COUNTER(rq_num_udsdprd, 0x118),
  1875. };
  1876. static struct rdma_hw_stats *mlx4_ib_alloc_hw_stats(struct ib_device *ibdev,
  1877. u8 port_num)
  1878. {
  1879. struct mlx4_ib_dev *dev = to_mdev(ibdev);
  1880. struct mlx4_ib_diag_counters *diag = dev->diag_counters;
  1881. if (!diag[!!port_num].name)
  1882. return NULL;
  1883. return rdma_alloc_hw_stats_struct(diag[!!port_num].name,
  1884. diag[!!port_num].num_counters,
  1885. RDMA_HW_STATS_DEFAULT_LIFESPAN);
  1886. }
  1887. static int mlx4_ib_get_hw_stats(struct ib_device *ibdev,
  1888. struct rdma_hw_stats *stats,
  1889. u8 port, int index)
  1890. {
  1891. struct mlx4_ib_dev *dev = to_mdev(ibdev);
  1892. struct mlx4_ib_diag_counters *diag = dev->diag_counters;
  1893. u32 hw_value[ARRAY_SIZE(diag_device_only) +
  1894. ARRAY_SIZE(diag_ext) + ARRAY_SIZE(diag_basic)] = {};
  1895. int ret;
  1896. int i;
  1897. ret = mlx4_query_diag_counters(dev->dev,
  1898. MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS,
  1899. diag[!!port].offset, hw_value,
  1900. diag[!!port].num_counters, port);
  1901. if (ret)
  1902. return ret;
  1903. for (i = 0; i < diag[!!port].num_counters; i++)
  1904. stats->value[i] = hw_value[i];
  1905. return diag[!!port].num_counters;
  1906. }
  1907. static int __mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev,
  1908. const char ***name,
  1909. u32 **offset,
  1910. u32 *num,
  1911. bool port)
  1912. {
  1913. u32 num_counters;
  1914. num_counters = ARRAY_SIZE(diag_basic);
  1915. if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT)
  1916. num_counters += ARRAY_SIZE(diag_ext);
  1917. if (!port)
  1918. num_counters += ARRAY_SIZE(diag_device_only);
  1919. *name = kcalloc(num_counters, sizeof(**name), GFP_KERNEL);
  1920. if (!*name)
  1921. return -ENOMEM;
  1922. *offset = kcalloc(num_counters, sizeof(**offset), GFP_KERNEL);
  1923. if (!*offset)
  1924. goto err_name;
  1925. *num = num_counters;
  1926. return 0;
  1927. err_name:
  1928. kfree(*name);
  1929. return -ENOMEM;
  1930. }
  1931. static void mlx4_ib_fill_diag_counters(struct mlx4_ib_dev *ibdev,
  1932. const char **name,
  1933. u32 *offset,
  1934. bool port)
  1935. {
  1936. int i;
  1937. int j;
  1938. for (i = 0, j = 0; i < ARRAY_SIZE(diag_basic); i++, j++) {
  1939. name[i] = diag_basic[i].name;
  1940. offset[i] = diag_basic[i].offset;
  1941. }
  1942. if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT) {
  1943. for (i = 0; i < ARRAY_SIZE(diag_ext); i++, j++) {
  1944. name[j] = diag_ext[i].name;
  1945. offset[j] = diag_ext[i].offset;
  1946. }
  1947. }
  1948. if (!port) {
  1949. for (i = 0; i < ARRAY_SIZE(diag_device_only); i++, j++) {
  1950. name[j] = diag_device_only[i].name;
  1951. offset[j] = diag_device_only[i].offset;
  1952. }
  1953. }
  1954. }
  1955. static int mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev)
  1956. {
  1957. struct mlx4_ib_diag_counters *diag = ibdev->diag_counters;
  1958. int i;
  1959. int ret;
  1960. bool per_port = !!(ibdev->dev->caps.flags2 &
  1961. MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT);
  1962. if (mlx4_is_slave(ibdev->dev))
  1963. return 0;
  1964. for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) {
  1965. /* i == 1 means we are building port counters */
  1966. if (i && !per_port)
  1967. continue;
  1968. ret = __mlx4_ib_alloc_diag_counters(ibdev, &diag[i].name,
  1969. &diag[i].offset,
  1970. &diag[i].num_counters, i);
  1971. if (ret)
  1972. goto err_alloc;
  1973. mlx4_ib_fill_diag_counters(ibdev, diag[i].name,
  1974. diag[i].offset, i);
  1975. }
  1976. ibdev->ib_dev.get_hw_stats = mlx4_ib_get_hw_stats;
  1977. ibdev->ib_dev.alloc_hw_stats = mlx4_ib_alloc_hw_stats;
  1978. return 0;
  1979. err_alloc:
  1980. if (i) {
  1981. kfree(diag[i - 1].name);
  1982. kfree(diag[i - 1].offset);
  1983. }
  1984. return ret;
  1985. }
  1986. static void mlx4_ib_diag_cleanup(struct mlx4_ib_dev *ibdev)
  1987. {
  1988. int i;
  1989. for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) {
  1990. kfree(ibdev->diag_counters[i].offset);
  1991. kfree(ibdev->diag_counters[i].name);
  1992. }
  1993. }
  1994. #define MLX4_IB_INVALID_MAC ((u64)-1)
  1995. static void mlx4_ib_update_qps(struct mlx4_ib_dev *ibdev,
  1996. struct net_device *dev,
  1997. int port)
  1998. {
  1999. u64 new_smac = 0;
  2000. u64 release_mac = MLX4_IB_INVALID_MAC;
  2001. struct mlx4_ib_qp *qp;
  2002. read_lock(&dev_base_lock);
  2003. new_smac = mlx4_mac_to_u64(dev->dev_addr);
  2004. read_unlock(&dev_base_lock);
  2005. atomic64_set(&ibdev->iboe.mac[port - 1], new_smac);
  2006. /* no need for update QP1 and mac registration in non-SRIOV */
  2007. if (!mlx4_is_mfunc(ibdev->dev))
  2008. return;
  2009. mutex_lock(&ibdev->qp1_proxy_lock[port - 1]);
  2010. qp = ibdev->qp1_proxy[port - 1];
  2011. if (qp) {
  2012. int new_smac_index;
  2013. u64 old_smac;
  2014. struct mlx4_update_qp_params update_params;
  2015. mutex_lock(&qp->mutex);
  2016. old_smac = qp->pri.smac;
  2017. if (new_smac == old_smac)
  2018. goto unlock;
  2019. new_smac_index = mlx4_register_mac(ibdev->dev, port, new_smac);
  2020. if (new_smac_index < 0)
  2021. goto unlock;
  2022. update_params.smac_index = new_smac_index;
  2023. if (mlx4_update_qp(ibdev->dev, qp->mqp.qpn, MLX4_UPDATE_QP_SMAC,
  2024. &update_params)) {
  2025. release_mac = new_smac;
  2026. goto unlock;
  2027. }
  2028. /* if old port was zero, no mac was yet registered for this QP */
  2029. if (qp->pri.smac_port)
  2030. release_mac = old_smac;
  2031. qp->pri.smac = new_smac;
  2032. qp->pri.smac_port = port;
  2033. qp->pri.smac_index = new_smac_index;
  2034. }
  2035. unlock:
  2036. if (release_mac != MLX4_IB_INVALID_MAC)
  2037. mlx4_unregister_mac(ibdev->dev, port, release_mac);
  2038. if (qp)
  2039. mutex_unlock(&qp->mutex);
  2040. mutex_unlock(&ibdev->qp1_proxy_lock[port - 1]);
  2041. }
  2042. static void mlx4_ib_scan_netdevs(struct mlx4_ib_dev *ibdev,
  2043. struct net_device *dev,
  2044. unsigned long event)
  2045. {
  2046. struct mlx4_ib_iboe *iboe;
  2047. int update_qps_port = -1;
  2048. int port;
  2049. ASSERT_RTNL();
  2050. iboe = &ibdev->iboe;
  2051. spin_lock_bh(&iboe->lock);
  2052. mlx4_foreach_ib_transport_port(port, ibdev->dev) {
  2053. iboe->netdevs[port - 1] =
  2054. mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port);
  2055. if (dev == iboe->netdevs[port - 1] &&
  2056. (event == NETDEV_CHANGEADDR || event == NETDEV_REGISTER ||
  2057. event == NETDEV_UP || event == NETDEV_CHANGE))
  2058. update_qps_port = port;
  2059. }
  2060. spin_unlock_bh(&iboe->lock);
  2061. if (update_qps_port > 0)
  2062. mlx4_ib_update_qps(ibdev, dev, update_qps_port);
  2063. }
  2064. static int mlx4_ib_netdev_event(struct notifier_block *this,
  2065. unsigned long event, void *ptr)
  2066. {
  2067. struct net_device *dev = netdev_notifier_info_to_dev(ptr);
  2068. struct mlx4_ib_dev *ibdev;
  2069. if (!net_eq(dev_net(dev), &init_net))
  2070. return NOTIFY_DONE;
  2071. ibdev = container_of(this, struct mlx4_ib_dev, iboe.nb);
  2072. mlx4_ib_scan_netdevs(ibdev, dev, event);
  2073. return NOTIFY_DONE;
  2074. }
  2075. static void init_pkeys(struct mlx4_ib_dev *ibdev)
  2076. {
  2077. int port;
  2078. int slave;
  2079. int i;
  2080. if (mlx4_is_master(ibdev->dev)) {
  2081. for (slave = 0; slave <= ibdev->dev->persist->num_vfs;
  2082. ++slave) {
  2083. for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) {
  2084. for (i = 0;
  2085. i < ibdev->dev->phys_caps.pkey_phys_table_len[port];
  2086. ++i) {
  2087. ibdev->pkeys.virt2phys_pkey[slave][port - 1][i] =
  2088. /* master has the identity virt2phys pkey mapping */
  2089. (slave == mlx4_master_func_num(ibdev->dev) || !i) ? i :
  2090. ibdev->dev->phys_caps.pkey_phys_table_len[port] - 1;
  2091. mlx4_sync_pkey_table(ibdev->dev, slave, port, i,
  2092. ibdev->pkeys.virt2phys_pkey[slave][port - 1][i]);
  2093. }
  2094. }
  2095. }
  2096. /* initialize pkey cache */
  2097. for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) {
  2098. for (i = 0;
  2099. i < ibdev->dev->phys_caps.pkey_phys_table_len[port];
  2100. ++i)
  2101. ibdev->pkeys.phys_pkey_cache[port-1][i] =
  2102. (i) ? 0 : 0xFFFF;
  2103. }
  2104. }
  2105. }
  2106. static void mlx4_ib_alloc_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev)
  2107. {
  2108. int i, j, eq = 0, total_eqs = 0;
  2109. ibdev->eq_table = kcalloc(dev->caps.num_comp_vectors,
  2110. sizeof(ibdev->eq_table[0]), GFP_KERNEL);
  2111. if (!ibdev->eq_table)
  2112. return;
  2113. for (i = 1; i <= dev->caps.num_ports; i++) {
  2114. for (j = 0; j < mlx4_get_eqs_per_port(dev, i);
  2115. j++, total_eqs++) {
  2116. if (i > 1 && mlx4_is_eq_shared(dev, total_eqs))
  2117. continue;
  2118. ibdev->eq_table[eq] = total_eqs;
  2119. if (!mlx4_assign_eq(dev, i,
  2120. &ibdev->eq_table[eq]))
  2121. eq++;
  2122. else
  2123. ibdev->eq_table[eq] = -1;
  2124. }
  2125. }
  2126. for (i = eq; i < dev->caps.num_comp_vectors;
  2127. ibdev->eq_table[i++] = -1)
  2128. ;
  2129. /* Advertise the new number of EQs to clients */
  2130. ibdev->ib_dev.num_comp_vectors = eq;
  2131. }
  2132. static void mlx4_ib_free_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev)
  2133. {
  2134. int i;
  2135. int total_eqs = ibdev->ib_dev.num_comp_vectors;
  2136. /* no eqs were allocated */
  2137. if (!ibdev->eq_table)
  2138. return;
  2139. /* Reset the advertised EQ number */
  2140. ibdev->ib_dev.num_comp_vectors = 0;
  2141. for (i = 0; i < total_eqs; i++)
  2142. mlx4_release_eq(dev, ibdev->eq_table[i]);
  2143. kfree(ibdev->eq_table);
  2144. ibdev->eq_table = NULL;
  2145. }
  2146. static int mlx4_port_immutable(struct ib_device *ibdev, u8 port_num,
  2147. struct ib_port_immutable *immutable)
  2148. {
  2149. struct ib_port_attr attr;
  2150. struct mlx4_ib_dev *mdev = to_mdev(ibdev);
  2151. int err;
  2152. if (mlx4_ib_port_link_layer(ibdev, port_num) == IB_LINK_LAYER_INFINIBAND) {
  2153. immutable->core_cap_flags = RDMA_CORE_PORT_IBA_IB;
  2154. immutable->max_mad_size = IB_MGMT_MAD_SIZE;
  2155. } else {
  2156. if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)
  2157. immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
  2158. if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2)
  2159. immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE |
  2160. RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
  2161. immutable->core_cap_flags |= RDMA_CORE_PORT_RAW_PACKET;
  2162. if (immutable->core_cap_flags & (RDMA_CORE_PORT_IBA_ROCE |
  2163. RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP))
  2164. immutable->max_mad_size = IB_MGMT_MAD_SIZE;
  2165. }
  2166. err = ib_query_port(ibdev, port_num, &attr);
  2167. if (err)
  2168. return err;
  2169. immutable->pkey_tbl_len = attr.pkey_tbl_len;
  2170. immutable->gid_tbl_len = attr.gid_tbl_len;
  2171. return 0;
  2172. }
  2173. static void get_fw_ver_str(struct ib_device *device, char *str)
  2174. {
  2175. struct mlx4_ib_dev *dev =
  2176. container_of(device, struct mlx4_ib_dev, ib_dev);
  2177. snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d",
  2178. (int) (dev->dev->caps.fw_ver >> 32),
  2179. (int) (dev->dev->caps.fw_ver >> 16) & 0xffff,
  2180. (int) dev->dev->caps.fw_ver & 0xffff);
  2181. }
  2182. static void *mlx4_ib_add(struct mlx4_dev *dev)
  2183. {
  2184. struct mlx4_ib_dev *ibdev;
  2185. int num_ports = 0;
  2186. int i, j;
  2187. int err;
  2188. struct mlx4_ib_iboe *iboe;
  2189. int ib_num_ports = 0;
  2190. int num_req_counters;
  2191. int allocated;
  2192. u32 counter_index;
  2193. struct counter_index *new_counter_index = NULL;
  2194. pr_info_once("%s", mlx4_ib_version);
  2195. num_ports = 0;
  2196. mlx4_foreach_ib_transport_port(i, dev)
  2197. num_ports++;
  2198. /* No point in registering a device with no ports... */
  2199. if (num_ports == 0)
  2200. return NULL;
  2201. ibdev = (struct mlx4_ib_dev *) ib_alloc_device(sizeof *ibdev);
  2202. if (!ibdev) {
  2203. dev_err(&dev->persist->pdev->dev,
  2204. "Device struct alloc failed\n");
  2205. return NULL;
  2206. }
  2207. iboe = &ibdev->iboe;
  2208. if (mlx4_pd_alloc(dev, &ibdev->priv_pdn))
  2209. goto err_dealloc;
  2210. if (mlx4_uar_alloc(dev, &ibdev->priv_uar))
  2211. goto err_pd;
  2212. ibdev->uar_map = ioremap((phys_addr_t) ibdev->priv_uar.pfn << PAGE_SHIFT,
  2213. PAGE_SIZE);
  2214. if (!ibdev->uar_map)
  2215. goto err_uar;
  2216. MLX4_INIT_DOORBELL_LOCK(&ibdev->uar_lock);
  2217. ibdev->dev = dev;
  2218. ibdev->bond_next_port = 0;
  2219. strlcpy(ibdev->ib_dev.name, "mlx4_%d", IB_DEVICE_NAME_MAX);
  2220. ibdev->ib_dev.owner = THIS_MODULE;
  2221. ibdev->ib_dev.node_type = RDMA_NODE_IB_CA;
  2222. ibdev->ib_dev.local_dma_lkey = dev->caps.reserved_lkey;
  2223. ibdev->num_ports = num_ports;
  2224. ibdev->ib_dev.phys_port_cnt = mlx4_is_bonded(dev) ?
  2225. 1 : ibdev->num_ports;
  2226. ibdev->ib_dev.num_comp_vectors = dev->caps.num_comp_vectors;
  2227. ibdev->ib_dev.dev.parent = &dev->persist->pdev->dev;
  2228. ibdev->ib_dev.get_netdev = mlx4_ib_get_netdev;
  2229. ibdev->ib_dev.add_gid = mlx4_ib_add_gid;
  2230. ibdev->ib_dev.del_gid = mlx4_ib_del_gid;
  2231. if (dev->caps.userspace_caps)
  2232. ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_ABI_VERSION;
  2233. else
  2234. ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION;
  2235. ibdev->ib_dev.uverbs_cmd_mask =
  2236. (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
  2237. (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
  2238. (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
  2239. (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
  2240. (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
  2241. (1ull << IB_USER_VERBS_CMD_REG_MR) |
  2242. (1ull << IB_USER_VERBS_CMD_REREG_MR) |
  2243. (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
  2244. (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
  2245. (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
  2246. (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
  2247. (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
  2248. (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
  2249. (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
  2250. (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
  2251. (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
  2252. (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
  2253. (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
  2254. (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
  2255. (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
  2256. (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
  2257. (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
  2258. (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
  2259. (1ull << IB_USER_VERBS_CMD_OPEN_QP);
  2260. ibdev->ib_dev.query_device = mlx4_ib_query_device;
  2261. ibdev->ib_dev.query_port = mlx4_ib_query_port;
  2262. ibdev->ib_dev.get_link_layer = mlx4_ib_port_link_layer;
  2263. ibdev->ib_dev.query_gid = mlx4_ib_query_gid;
  2264. ibdev->ib_dev.query_pkey = mlx4_ib_query_pkey;
  2265. ibdev->ib_dev.modify_device = mlx4_ib_modify_device;
  2266. ibdev->ib_dev.modify_port = mlx4_ib_modify_port;
  2267. ibdev->ib_dev.alloc_ucontext = mlx4_ib_alloc_ucontext;
  2268. ibdev->ib_dev.dealloc_ucontext = mlx4_ib_dealloc_ucontext;
  2269. ibdev->ib_dev.mmap = mlx4_ib_mmap;
  2270. ibdev->ib_dev.alloc_pd = mlx4_ib_alloc_pd;
  2271. ibdev->ib_dev.dealloc_pd = mlx4_ib_dealloc_pd;
  2272. ibdev->ib_dev.create_ah = mlx4_ib_create_ah;
  2273. ibdev->ib_dev.query_ah = mlx4_ib_query_ah;
  2274. ibdev->ib_dev.destroy_ah = mlx4_ib_destroy_ah;
  2275. ibdev->ib_dev.create_srq = mlx4_ib_create_srq;
  2276. ibdev->ib_dev.modify_srq = mlx4_ib_modify_srq;
  2277. ibdev->ib_dev.query_srq = mlx4_ib_query_srq;
  2278. ibdev->ib_dev.destroy_srq = mlx4_ib_destroy_srq;
  2279. ibdev->ib_dev.post_srq_recv = mlx4_ib_post_srq_recv;
  2280. ibdev->ib_dev.create_qp = mlx4_ib_create_qp;
  2281. ibdev->ib_dev.modify_qp = mlx4_ib_modify_qp;
  2282. ibdev->ib_dev.query_qp = mlx4_ib_query_qp;
  2283. ibdev->ib_dev.destroy_qp = mlx4_ib_destroy_qp;
  2284. ibdev->ib_dev.drain_sq = mlx4_ib_drain_sq;
  2285. ibdev->ib_dev.drain_rq = mlx4_ib_drain_rq;
  2286. ibdev->ib_dev.post_send = mlx4_ib_post_send;
  2287. ibdev->ib_dev.post_recv = mlx4_ib_post_recv;
  2288. ibdev->ib_dev.create_cq = mlx4_ib_create_cq;
  2289. ibdev->ib_dev.modify_cq = mlx4_ib_modify_cq;
  2290. ibdev->ib_dev.resize_cq = mlx4_ib_resize_cq;
  2291. ibdev->ib_dev.destroy_cq = mlx4_ib_destroy_cq;
  2292. ibdev->ib_dev.poll_cq = mlx4_ib_poll_cq;
  2293. ibdev->ib_dev.req_notify_cq = mlx4_ib_arm_cq;
  2294. ibdev->ib_dev.get_dma_mr = mlx4_ib_get_dma_mr;
  2295. ibdev->ib_dev.reg_user_mr = mlx4_ib_reg_user_mr;
  2296. ibdev->ib_dev.rereg_user_mr = mlx4_ib_rereg_user_mr;
  2297. ibdev->ib_dev.dereg_mr = mlx4_ib_dereg_mr;
  2298. ibdev->ib_dev.alloc_mr = mlx4_ib_alloc_mr;
  2299. ibdev->ib_dev.map_mr_sg = mlx4_ib_map_mr_sg;
  2300. ibdev->ib_dev.attach_mcast = mlx4_ib_mcg_attach;
  2301. ibdev->ib_dev.detach_mcast = mlx4_ib_mcg_detach;
  2302. ibdev->ib_dev.process_mad = mlx4_ib_process_mad;
  2303. ibdev->ib_dev.get_port_immutable = mlx4_port_immutable;
  2304. ibdev->ib_dev.get_dev_fw_str = get_fw_ver_str;
  2305. ibdev->ib_dev.disassociate_ucontext = mlx4_ib_disassociate_ucontext;
  2306. ibdev->ib_dev.uverbs_ex_cmd_mask |=
  2307. (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
  2308. if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS) &&
  2309. ((mlx4_ib_port_link_layer(&ibdev->ib_dev, 1) ==
  2310. IB_LINK_LAYER_ETHERNET) ||
  2311. (mlx4_ib_port_link_layer(&ibdev->ib_dev, 2) ==
  2312. IB_LINK_LAYER_ETHERNET))) {
  2313. ibdev->ib_dev.create_wq = mlx4_ib_create_wq;
  2314. ibdev->ib_dev.modify_wq = mlx4_ib_modify_wq;
  2315. ibdev->ib_dev.destroy_wq = mlx4_ib_destroy_wq;
  2316. ibdev->ib_dev.create_rwq_ind_table =
  2317. mlx4_ib_create_rwq_ind_table;
  2318. ibdev->ib_dev.destroy_rwq_ind_table =
  2319. mlx4_ib_destroy_rwq_ind_table;
  2320. ibdev->ib_dev.uverbs_ex_cmd_mask |=
  2321. (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
  2322. (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
  2323. (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
  2324. (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
  2325. (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
  2326. }
  2327. if (!mlx4_is_slave(ibdev->dev)) {
  2328. ibdev->ib_dev.alloc_fmr = mlx4_ib_fmr_alloc;
  2329. ibdev->ib_dev.map_phys_fmr = mlx4_ib_map_phys_fmr;
  2330. ibdev->ib_dev.unmap_fmr = mlx4_ib_unmap_fmr;
  2331. ibdev->ib_dev.dealloc_fmr = mlx4_ib_fmr_dealloc;
  2332. }
  2333. if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
  2334. dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) {
  2335. ibdev->ib_dev.alloc_mw = mlx4_ib_alloc_mw;
  2336. ibdev->ib_dev.dealloc_mw = mlx4_ib_dealloc_mw;
  2337. ibdev->ib_dev.uverbs_cmd_mask |=
  2338. (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
  2339. (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
  2340. }
  2341. if (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) {
  2342. ibdev->ib_dev.alloc_xrcd = mlx4_ib_alloc_xrcd;
  2343. ibdev->ib_dev.dealloc_xrcd = mlx4_ib_dealloc_xrcd;
  2344. ibdev->ib_dev.uverbs_cmd_mask |=
  2345. (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
  2346. (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
  2347. }
  2348. if (check_flow_steering_support(dev)) {
  2349. ibdev->steering_support = MLX4_STEERING_MODE_DEVICE_MANAGED;
  2350. ibdev->ib_dev.create_flow = mlx4_ib_create_flow;
  2351. ibdev->ib_dev.destroy_flow = mlx4_ib_destroy_flow;
  2352. ibdev->ib_dev.uverbs_ex_cmd_mask |=
  2353. (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
  2354. (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
  2355. }
  2356. ibdev->ib_dev.uverbs_ex_cmd_mask |=
  2357. (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
  2358. (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
  2359. (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
  2360. mlx4_ib_alloc_eqs(dev, ibdev);
  2361. spin_lock_init(&iboe->lock);
  2362. if (init_node_data(ibdev))
  2363. goto err_map;
  2364. mlx4_init_sl2vl_tbl(ibdev);
  2365. for (i = 0; i < ibdev->num_ports; ++i) {
  2366. mutex_init(&ibdev->counters_table[i].mutex);
  2367. INIT_LIST_HEAD(&ibdev->counters_table[i].counters_list);
  2368. }
  2369. num_req_counters = mlx4_is_bonded(dev) ? 1 : ibdev->num_ports;
  2370. for (i = 0; i < num_req_counters; ++i) {
  2371. mutex_init(&ibdev->qp1_proxy_lock[i]);
  2372. allocated = 0;
  2373. if (mlx4_ib_port_link_layer(&ibdev->ib_dev, i + 1) ==
  2374. IB_LINK_LAYER_ETHERNET) {
  2375. err = mlx4_counter_alloc(ibdev->dev, &counter_index,
  2376. MLX4_RES_USAGE_DRIVER);
  2377. /* if failed to allocate a new counter, use default */
  2378. if (err)
  2379. counter_index =
  2380. mlx4_get_default_counter_index(dev,
  2381. i + 1);
  2382. else
  2383. allocated = 1;
  2384. } else { /* IB_LINK_LAYER_INFINIBAND use the default counter */
  2385. counter_index = mlx4_get_default_counter_index(dev,
  2386. i + 1);
  2387. }
  2388. new_counter_index = kmalloc(sizeof(*new_counter_index),
  2389. GFP_KERNEL);
  2390. if (!new_counter_index) {
  2391. if (allocated)
  2392. mlx4_counter_free(ibdev->dev, counter_index);
  2393. goto err_counter;
  2394. }
  2395. new_counter_index->index = counter_index;
  2396. new_counter_index->allocated = allocated;
  2397. list_add_tail(&new_counter_index->list,
  2398. &ibdev->counters_table[i].counters_list);
  2399. ibdev->counters_table[i].default_counter = counter_index;
  2400. pr_info("counter index %d for port %d allocated %d\n",
  2401. counter_index, i + 1, allocated);
  2402. }
  2403. if (mlx4_is_bonded(dev))
  2404. for (i = 1; i < ibdev->num_ports ; ++i) {
  2405. new_counter_index =
  2406. kmalloc(sizeof(struct counter_index),
  2407. GFP_KERNEL);
  2408. if (!new_counter_index)
  2409. goto err_counter;
  2410. new_counter_index->index = counter_index;
  2411. new_counter_index->allocated = 0;
  2412. list_add_tail(&new_counter_index->list,
  2413. &ibdev->counters_table[i].counters_list);
  2414. ibdev->counters_table[i].default_counter =
  2415. counter_index;
  2416. }
  2417. mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
  2418. ib_num_ports++;
  2419. spin_lock_init(&ibdev->sm_lock);
  2420. mutex_init(&ibdev->cap_mask_mutex);
  2421. INIT_LIST_HEAD(&ibdev->qp_list);
  2422. spin_lock_init(&ibdev->reset_flow_resource_lock);
  2423. if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED &&
  2424. ib_num_ports) {
  2425. ibdev->steer_qpn_count = MLX4_IB_UC_MAX_NUM_QPS;
  2426. err = mlx4_qp_reserve_range(dev, ibdev->steer_qpn_count,
  2427. MLX4_IB_UC_STEER_QPN_ALIGN,
  2428. &ibdev->steer_qpn_base, 0,
  2429. MLX4_RES_USAGE_DRIVER);
  2430. if (err)
  2431. goto err_counter;
  2432. ibdev->ib_uc_qpns_bitmap =
  2433. kmalloc_array(BITS_TO_LONGS(ibdev->steer_qpn_count),
  2434. sizeof(long),
  2435. GFP_KERNEL);
  2436. if (!ibdev->ib_uc_qpns_bitmap)
  2437. goto err_steer_qp_release;
  2438. if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB) {
  2439. bitmap_zero(ibdev->ib_uc_qpns_bitmap,
  2440. ibdev->steer_qpn_count);
  2441. err = mlx4_FLOW_STEERING_IB_UC_QP_RANGE(
  2442. dev, ibdev->steer_qpn_base,
  2443. ibdev->steer_qpn_base +
  2444. ibdev->steer_qpn_count - 1);
  2445. if (err)
  2446. goto err_steer_free_bitmap;
  2447. } else {
  2448. bitmap_fill(ibdev->ib_uc_qpns_bitmap,
  2449. ibdev->steer_qpn_count);
  2450. }
  2451. }
  2452. for (j = 1; j <= ibdev->dev->caps.num_ports; j++)
  2453. atomic64_set(&iboe->mac[j - 1], ibdev->dev->caps.def_mac[j]);
  2454. if (mlx4_ib_alloc_diag_counters(ibdev))
  2455. goto err_steer_free_bitmap;
  2456. ibdev->ib_dev.driver_id = RDMA_DRIVER_MLX4;
  2457. if (ib_register_device(&ibdev->ib_dev, NULL))
  2458. goto err_diag_counters;
  2459. if (mlx4_ib_mad_init(ibdev))
  2460. goto err_reg;
  2461. if (mlx4_ib_init_sriov(ibdev))
  2462. goto err_mad;
  2463. if (!iboe->nb.notifier_call) {
  2464. iboe->nb.notifier_call = mlx4_ib_netdev_event;
  2465. err = register_netdevice_notifier(&iboe->nb);
  2466. if (err) {
  2467. iboe->nb.notifier_call = NULL;
  2468. goto err_notif;
  2469. }
  2470. }
  2471. if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
  2472. err = mlx4_config_roce_v2_port(dev, ROCE_V2_UDP_DPORT);
  2473. if (err)
  2474. goto err_notif;
  2475. }
  2476. for (j = 0; j < ARRAY_SIZE(mlx4_class_attributes); ++j) {
  2477. if (device_create_file(&ibdev->ib_dev.dev,
  2478. mlx4_class_attributes[j]))
  2479. goto err_notif;
  2480. }
  2481. ibdev->ib_active = true;
  2482. mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
  2483. devlink_port_type_ib_set(mlx4_get_devlink_port(dev, i),
  2484. &ibdev->ib_dev);
  2485. if (mlx4_is_mfunc(ibdev->dev))
  2486. init_pkeys(ibdev);
  2487. /* create paravirt contexts for any VFs which are active */
  2488. if (mlx4_is_master(ibdev->dev)) {
  2489. for (j = 0; j < MLX4_MFUNC_MAX; j++) {
  2490. if (j == mlx4_master_func_num(ibdev->dev))
  2491. continue;
  2492. if (mlx4_is_slave_active(ibdev->dev, j))
  2493. do_slave_init(ibdev, j, 1);
  2494. }
  2495. }
  2496. return ibdev;
  2497. err_notif:
  2498. if (ibdev->iboe.nb.notifier_call) {
  2499. if (unregister_netdevice_notifier(&ibdev->iboe.nb))
  2500. pr_warn("failure unregistering notifier\n");
  2501. ibdev->iboe.nb.notifier_call = NULL;
  2502. }
  2503. flush_workqueue(wq);
  2504. mlx4_ib_close_sriov(ibdev);
  2505. err_mad:
  2506. mlx4_ib_mad_cleanup(ibdev);
  2507. err_reg:
  2508. ib_unregister_device(&ibdev->ib_dev);
  2509. err_diag_counters:
  2510. mlx4_ib_diag_cleanup(ibdev);
  2511. err_steer_free_bitmap:
  2512. kfree(ibdev->ib_uc_qpns_bitmap);
  2513. err_steer_qp_release:
  2514. mlx4_qp_release_range(dev, ibdev->steer_qpn_base,
  2515. ibdev->steer_qpn_count);
  2516. err_counter:
  2517. for (i = 0; i < ibdev->num_ports; ++i)
  2518. mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[i]);
  2519. err_map:
  2520. mlx4_ib_free_eqs(dev, ibdev);
  2521. iounmap(ibdev->uar_map);
  2522. err_uar:
  2523. mlx4_uar_free(dev, &ibdev->priv_uar);
  2524. err_pd:
  2525. mlx4_pd_free(dev, ibdev->priv_pdn);
  2526. err_dealloc:
  2527. ib_dealloc_device(&ibdev->ib_dev);
  2528. return NULL;
  2529. }
  2530. int mlx4_ib_steer_qp_alloc(struct mlx4_ib_dev *dev, int count, int *qpn)
  2531. {
  2532. int offset;
  2533. WARN_ON(!dev->ib_uc_qpns_bitmap);
  2534. offset = bitmap_find_free_region(dev->ib_uc_qpns_bitmap,
  2535. dev->steer_qpn_count,
  2536. get_count_order(count));
  2537. if (offset < 0)
  2538. return offset;
  2539. *qpn = dev->steer_qpn_base + offset;
  2540. return 0;
  2541. }
  2542. void mlx4_ib_steer_qp_free(struct mlx4_ib_dev *dev, u32 qpn, int count)
  2543. {
  2544. if (!qpn ||
  2545. dev->steering_support != MLX4_STEERING_MODE_DEVICE_MANAGED)
  2546. return;
  2547. if (WARN(qpn < dev->steer_qpn_base, "qpn = %u, steer_qpn_base = %u\n",
  2548. qpn, dev->steer_qpn_base))
  2549. /* not supposed to be here */
  2550. return;
  2551. bitmap_release_region(dev->ib_uc_qpns_bitmap,
  2552. qpn - dev->steer_qpn_base,
  2553. get_count_order(count));
  2554. }
  2555. int mlx4_ib_steer_qp_reg(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
  2556. int is_attach)
  2557. {
  2558. int err;
  2559. size_t flow_size;
  2560. struct ib_flow_attr *flow = NULL;
  2561. struct ib_flow_spec_ib *ib_spec;
  2562. if (is_attach) {
  2563. flow_size = sizeof(struct ib_flow_attr) +
  2564. sizeof(struct ib_flow_spec_ib);
  2565. flow = kzalloc(flow_size, GFP_KERNEL);
  2566. if (!flow)
  2567. return -ENOMEM;
  2568. flow->port = mqp->port;
  2569. flow->num_of_specs = 1;
  2570. flow->size = flow_size;
  2571. ib_spec = (struct ib_flow_spec_ib *)(flow + 1);
  2572. ib_spec->type = IB_FLOW_SPEC_IB;
  2573. ib_spec->size = sizeof(struct ib_flow_spec_ib);
  2574. /* Add an empty rule for IB L2 */
  2575. memset(&ib_spec->mask, 0, sizeof(ib_spec->mask));
  2576. err = __mlx4_ib_create_flow(&mqp->ibqp, flow,
  2577. IB_FLOW_DOMAIN_NIC,
  2578. MLX4_FS_REGULAR,
  2579. &mqp->reg_id);
  2580. } else {
  2581. err = __mlx4_ib_destroy_flow(mdev->dev, mqp->reg_id);
  2582. }
  2583. kfree(flow);
  2584. return err;
  2585. }
  2586. static void mlx4_ib_remove(struct mlx4_dev *dev, void *ibdev_ptr)
  2587. {
  2588. struct mlx4_ib_dev *ibdev = ibdev_ptr;
  2589. int p;
  2590. int i;
  2591. mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
  2592. devlink_port_type_clear(mlx4_get_devlink_port(dev, i));
  2593. ibdev->ib_active = false;
  2594. flush_workqueue(wq);
  2595. if (ibdev->iboe.nb.notifier_call) {
  2596. if (unregister_netdevice_notifier(&ibdev->iboe.nb))
  2597. pr_warn("failure unregistering notifier\n");
  2598. ibdev->iboe.nb.notifier_call = NULL;
  2599. }
  2600. mlx4_ib_close_sriov(ibdev);
  2601. mlx4_ib_mad_cleanup(ibdev);
  2602. ib_unregister_device(&ibdev->ib_dev);
  2603. mlx4_ib_diag_cleanup(ibdev);
  2604. mlx4_qp_release_range(dev, ibdev->steer_qpn_base,
  2605. ibdev->steer_qpn_count);
  2606. kfree(ibdev->ib_uc_qpns_bitmap);
  2607. iounmap(ibdev->uar_map);
  2608. for (p = 0; p < ibdev->num_ports; ++p)
  2609. mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[p]);
  2610. mlx4_foreach_port(p, dev, MLX4_PORT_TYPE_IB)
  2611. mlx4_CLOSE_PORT(dev, p);
  2612. mlx4_ib_free_eqs(dev, ibdev);
  2613. mlx4_uar_free(dev, &ibdev->priv_uar);
  2614. mlx4_pd_free(dev, ibdev->priv_pdn);
  2615. ib_dealloc_device(&ibdev->ib_dev);
  2616. }
  2617. static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init)
  2618. {
  2619. struct mlx4_ib_demux_work **dm = NULL;
  2620. struct mlx4_dev *dev = ibdev->dev;
  2621. int i;
  2622. unsigned long flags;
  2623. struct mlx4_active_ports actv_ports;
  2624. unsigned int ports;
  2625. unsigned int first_port;
  2626. if (!mlx4_is_master(dev))
  2627. return;
  2628. actv_ports = mlx4_get_active_ports(dev, slave);
  2629. ports = bitmap_weight(actv_ports.ports, dev->caps.num_ports);
  2630. first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports);
  2631. dm = kcalloc(ports, sizeof(*dm), GFP_ATOMIC);
  2632. if (!dm)
  2633. return;
  2634. for (i = 0; i < ports; i++) {
  2635. dm[i] = kmalloc(sizeof (struct mlx4_ib_demux_work), GFP_ATOMIC);
  2636. if (!dm[i]) {
  2637. while (--i >= 0)
  2638. kfree(dm[i]);
  2639. goto out;
  2640. }
  2641. INIT_WORK(&dm[i]->work, mlx4_ib_tunnels_update_work);
  2642. dm[i]->port = first_port + i + 1;
  2643. dm[i]->slave = slave;
  2644. dm[i]->do_init = do_init;
  2645. dm[i]->dev = ibdev;
  2646. }
  2647. /* initialize or tear down tunnel QPs for the slave */
  2648. spin_lock_irqsave(&ibdev->sriov.going_down_lock, flags);
  2649. if (!ibdev->sriov.is_going_down) {
  2650. for (i = 0; i < ports; i++)
  2651. queue_work(ibdev->sriov.demux[i].ud_wq, &dm[i]->work);
  2652. spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags);
  2653. } else {
  2654. spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags);
  2655. for (i = 0; i < ports; i++)
  2656. kfree(dm[i]);
  2657. }
  2658. out:
  2659. kfree(dm);
  2660. return;
  2661. }
  2662. static void mlx4_ib_handle_catas_error(struct mlx4_ib_dev *ibdev)
  2663. {
  2664. struct mlx4_ib_qp *mqp;
  2665. unsigned long flags_qp;
  2666. unsigned long flags_cq;
  2667. struct mlx4_ib_cq *send_mcq, *recv_mcq;
  2668. struct list_head cq_notify_list;
  2669. struct mlx4_cq *mcq;
  2670. unsigned long flags;
  2671. pr_warn("mlx4_ib_handle_catas_error was started\n");
  2672. INIT_LIST_HEAD(&cq_notify_list);
  2673. /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
  2674. spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
  2675. list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
  2676. spin_lock_irqsave(&mqp->sq.lock, flags_qp);
  2677. if (mqp->sq.tail != mqp->sq.head) {
  2678. send_mcq = to_mcq(mqp->ibqp.send_cq);
  2679. spin_lock_irqsave(&send_mcq->lock, flags_cq);
  2680. if (send_mcq->mcq.comp &&
  2681. mqp->ibqp.send_cq->comp_handler) {
  2682. if (!send_mcq->mcq.reset_notify_added) {
  2683. send_mcq->mcq.reset_notify_added = 1;
  2684. list_add_tail(&send_mcq->mcq.reset_notify,
  2685. &cq_notify_list);
  2686. }
  2687. }
  2688. spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
  2689. }
  2690. spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
  2691. /* Now, handle the QP's receive queue */
  2692. spin_lock_irqsave(&mqp->rq.lock, flags_qp);
  2693. /* no handling is needed for SRQ */
  2694. if (!mqp->ibqp.srq) {
  2695. if (mqp->rq.tail != mqp->rq.head) {
  2696. recv_mcq = to_mcq(mqp->ibqp.recv_cq);
  2697. spin_lock_irqsave(&recv_mcq->lock, flags_cq);
  2698. if (recv_mcq->mcq.comp &&
  2699. mqp->ibqp.recv_cq->comp_handler) {
  2700. if (!recv_mcq->mcq.reset_notify_added) {
  2701. recv_mcq->mcq.reset_notify_added = 1;
  2702. list_add_tail(&recv_mcq->mcq.reset_notify,
  2703. &cq_notify_list);
  2704. }
  2705. }
  2706. spin_unlock_irqrestore(&recv_mcq->lock,
  2707. flags_cq);
  2708. }
  2709. }
  2710. spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
  2711. }
  2712. list_for_each_entry(mcq, &cq_notify_list, reset_notify) {
  2713. mcq->comp(mcq);
  2714. }
  2715. spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
  2716. pr_warn("mlx4_ib_handle_catas_error ended\n");
  2717. }
  2718. static void handle_bonded_port_state_event(struct work_struct *work)
  2719. {
  2720. struct ib_event_work *ew =
  2721. container_of(work, struct ib_event_work, work);
  2722. struct mlx4_ib_dev *ibdev = ew->ib_dev;
  2723. enum ib_port_state bonded_port_state = IB_PORT_NOP;
  2724. int i;
  2725. struct ib_event ibev;
  2726. kfree(ew);
  2727. spin_lock_bh(&ibdev->iboe.lock);
  2728. for (i = 0; i < MLX4_MAX_PORTS; ++i) {
  2729. struct net_device *curr_netdev = ibdev->iboe.netdevs[i];
  2730. enum ib_port_state curr_port_state;
  2731. if (!curr_netdev)
  2732. continue;
  2733. curr_port_state =
  2734. (netif_running(curr_netdev) &&
  2735. netif_carrier_ok(curr_netdev)) ?
  2736. IB_PORT_ACTIVE : IB_PORT_DOWN;
  2737. bonded_port_state = (bonded_port_state != IB_PORT_ACTIVE) ?
  2738. curr_port_state : IB_PORT_ACTIVE;
  2739. }
  2740. spin_unlock_bh(&ibdev->iboe.lock);
  2741. ibev.device = &ibdev->ib_dev;
  2742. ibev.element.port_num = 1;
  2743. ibev.event = (bonded_port_state == IB_PORT_ACTIVE) ?
  2744. IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
  2745. ib_dispatch_event(&ibev);
  2746. }
  2747. void mlx4_ib_sl2vl_update(struct mlx4_ib_dev *mdev, int port)
  2748. {
  2749. u64 sl2vl;
  2750. int err;
  2751. err = mlx4_ib_query_sl2vl(&mdev->ib_dev, port, &sl2vl);
  2752. if (err) {
  2753. pr_err("Unable to get current sl to vl mapping for port %d. Using all zeroes (%d)\n",
  2754. port, err);
  2755. sl2vl = 0;
  2756. }
  2757. atomic64_set(&mdev->sl2vl[port - 1], sl2vl);
  2758. }
  2759. static void ib_sl2vl_update_work(struct work_struct *work)
  2760. {
  2761. struct ib_event_work *ew = container_of(work, struct ib_event_work, work);
  2762. struct mlx4_ib_dev *mdev = ew->ib_dev;
  2763. int port = ew->port;
  2764. mlx4_ib_sl2vl_update(mdev, port);
  2765. kfree(ew);
  2766. }
  2767. void mlx4_sched_ib_sl2vl_update_work(struct mlx4_ib_dev *ibdev,
  2768. int port)
  2769. {
  2770. struct ib_event_work *ew;
  2771. ew = kmalloc(sizeof(*ew), GFP_ATOMIC);
  2772. if (ew) {
  2773. INIT_WORK(&ew->work, ib_sl2vl_update_work);
  2774. ew->port = port;
  2775. ew->ib_dev = ibdev;
  2776. queue_work(wq, &ew->work);
  2777. }
  2778. }
  2779. static void mlx4_ib_event(struct mlx4_dev *dev, void *ibdev_ptr,
  2780. enum mlx4_dev_event event, unsigned long param)
  2781. {
  2782. struct ib_event ibev;
  2783. struct mlx4_ib_dev *ibdev = to_mdev((struct ib_device *) ibdev_ptr);
  2784. struct mlx4_eqe *eqe = NULL;
  2785. struct ib_event_work *ew;
  2786. int p = 0;
  2787. if (mlx4_is_bonded(dev) &&
  2788. ((event == MLX4_DEV_EVENT_PORT_UP) ||
  2789. (event == MLX4_DEV_EVENT_PORT_DOWN))) {
  2790. ew = kmalloc(sizeof(*ew), GFP_ATOMIC);
  2791. if (!ew)
  2792. return;
  2793. INIT_WORK(&ew->work, handle_bonded_port_state_event);
  2794. ew->ib_dev = ibdev;
  2795. queue_work(wq, &ew->work);
  2796. return;
  2797. }
  2798. if (event == MLX4_DEV_EVENT_PORT_MGMT_CHANGE)
  2799. eqe = (struct mlx4_eqe *)param;
  2800. else
  2801. p = (int) param;
  2802. switch (event) {
  2803. case MLX4_DEV_EVENT_PORT_UP:
  2804. if (p > ibdev->num_ports)
  2805. return;
  2806. if (!mlx4_is_slave(dev) &&
  2807. rdma_port_get_link_layer(&ibdev->ib_dev, p) ==
  2808. IB_LINK_LAYER_INFINIBAND) {
  2809. if (mlx4_is_master(dev))
  2810. mlx4_ib_invalidate_all_guid_record(ibdev, p);
  2811. if (ibdev->dev->flags & MLX4_FLAG_SECURE_HOST &&
  2812. !(ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT))
  2813. mlx4_sched_ib_sl2vl_update_work(ibdev, p);
  2814. }
  2815. ibev.event = IB_EVENT_PORT_ACTIVE;
  2816. break;
  2817. case MLX4_DEV_EVENT_PORT_DOWN:
  2818. if (p > ibdev->num_ports)
  2819. return;
  2820. ibev.event = IB_EVENT_PORT_ERR;
  2821. break;
  2822. case MLX4_DEV_EVENT_CATASTROPHIC_ERROR:
  2823. ibdev->ib_active = false;
  2824. ibev.event = IB_EVENT_DEVICE_FATAL;
  2825. mlx4_ib_handle_catas_error(ibdev);
  2826. break;
  2827. case MLX4_DEV_EVENT_PORT_MGMT_CHANGE:
  2828. ew = kmalloc(sizeof *ew, GFP_ATOMIC);
  2829. if (!ew)
  2830. break;
  2831. INIT_WORK(&ew->work, handle_port_mgmt_change_event);
  2832. memcpy(&ew->ib_eqe, eqe, sizeof *eqe);
  2833. ew->ib_dev = ibdev;
  2834. /* need to queue only for port owner, which uses GEN_EQE */
  2835. if (mlx4_is_master(dev))
  2836. queue_work(wq, &ew->work);
  2837. else
  2838. handle_port_mgmt_change_event(&ew->work);
  2839. return;
  2840. case MLX4_DEV_EVENT_SLAVE_INIT:
  2841. /* here, p is the slave id */
  2842. do_slave_init(ibdev, p, 1);
  2843. if (mlx4_is_master(dev)) {
  2844. int i;
  2845. for (i = 1; i <= ibdev->num_ports; i++) {
  2846. if (rdma_port_get_link_layer(&ibdev->ib_dev, i)
  2847. == IB_LINK_LAYER_INFINIBAND)
  2848. mlx4_ib_slave_alias_guid_event(ibdev,
  2849. p, i,
  2850. 1);
  2851. }
  2852. }
  2853. return;
  2854. case MLX4_DEV_EVENT_SLAVE_SHUTDOWN:
  2855. if (mlx4_is_master(dev)) {
  2856. int i;
  2857. for (i = 1; i <= ibdev->num_ports; i++) {
  2858. if (rdma_port_get_link_layer(&ibdev->ib_dev, i)
  2859. == IB_LINK_LAYER_INFINIBAND)
  2860. mlx4_ib_slave_alias_guid_event(ibdev,
  2861. p, i,
  2862. 0);
  2863. }
  2864. }
  2865. /* here, p is the slave id */
  2866. do_slave_init(ibdev, p, 0);
  2867. return;
  2868. default:
  2869. return;
  2870. }
  2871. ibev.device = ibdev_ptr;
  2872. ibev.element.port_num = mlx4_is_bonded(ibdev->dev) ? 1 : (u8)p;
  2873. ib_dispatch_event(&ibev);
  2874. }
  2875. static struct mlx4_interface mlx4_ib_interface = {
  2876. .add = mlx4_ib_add,
  2877. .remove = mlx4_ib_remove,
  2878. .event = mlx4_ib_event,
  2879. .protocol = MLX4_PROT_IB_IPV6,
  2880. .flags = MLX4_INTFF_BONDING
  2881. };
  2882. static int __init mlx4_ib_init(void)
  2883. {
  2884. int err;
  2885. wq = alloc_ordered_workqueue("mlx4_ib", WQ_MEM_RECLAIM);
  2886. if (!wq)
  2887. return -ENOMEM;
  2888. err = mlx4_ib_mcg_init();
  2889. if (err)
  2890. goto clean_wq;
  2891. err = mlx4_register_interface(&mlx4_ib_interface);
  2892. if (err)
  2893. goto clean_mcg;
  2894. return 0;
  2895. clean_mcg:
  2896. mlx4_ib_mcg_destroy();
  2897. clean_wq:
  2898. destroy_workqueue(wq);
  2899. return err;
  2900. }
  2901. static void __exit mlx4_ib_cleanup(void)
  2902. {
  2903. mlx4_unregister_interface(&mlx4_ib_interface);
  2904. mlx4_ib_mcg_destroy();
  2905. destroy_workqueue(wq);
  2906. }
  2907. module_init(mlx4_ib_init);
  2908. module_exit(mlx4_ib_cleanup);