device.c 43 KB

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  1. /*
  2. * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <linux/module.h>
  33. #include <linux/moduleparam.h>
  34. #include <linux/debugfs.h>
  35. #include <linux/vmalloc.h>
  36. #include <linux/math64.h>
  37. #include <rdma/ib_verbs.h>
  38. #include "iw_cxgb4.h"
  39. #define DRV_VERSION "0.1"
  40. MODULE_AUTHOR("Steve Wise");
  41. MODULE_DESCRIPTION("Chelsio T4/T5 RDMA Driver");
  42. MODULE_LICENSE("Dual BSD/GPL");
  43. static int allow_db_fc_on_t5;
  44. module_param(allow_db_fc_on_t5, int, 0644);
  45. MODULE_PARM_DESC(allow_db_fc_on_t5,
  46. "Allow DB Flow Control on T5 (default = 0)");
  47. static int allow_db_coalescing_on_t5;
  48. module_param(allow_db_coalescing_on_t5, int, 0644);
  49. MODULE_PARM_DESC(allow_db_coalescing_on_t5,
  50. "Allow DB Coalescing on T5 (default = 0)");
  51. int c4iw_wr_log = 0;
  52. module_param(c4iw_wr_log, int, 0444);
  53. MODULE_PARM_DESC(c4iw_wr_log, "Enables logging of work request timing data.");
  54. static int c4iw_wr_log_size_order = 12;
  55. module_param(c4iw_wr_log_size_order, int, 0444);
  56. MODULE_PARM_DESC(c4iw_wr_log_size_order,
  57. "Number of entries (log2) in the work request timing log.");
  58. static LIST_HEAD(uld_ctx_list);
  59. static DEFINE_MUTEX(dev_mutex);
  60. static struct workqueue_struct *reg_workq;
  61. #define DB_FC_RESUME_SIZE 64
  62. #define DB_FC_RESUME_DELAY 1
  63. #define DB_FC_DRAIN_THRESH 0
  64. static struct dentry *c4iw_debugfs_root;
  65. struct c4iw_debugfs_data {
  66. struct c4iw_dev *devp;
  67. char *buf;
  68. int bufsize;
  69. int pos;
  70. };
  71. static int count_idrs(int id, void *p, void *data)
  72. {
  73. int *countp = data;
  74. *countp = *countp + 1;
  75. return 0;
  76. }
  77. static ssize_t debugfs_read(struct file *file, char __user *buf, size_t count,
  78. loff_t *ppos)
  79. {
  80. struct c4iw_debugfs_data *d = file->private_data;
  81. return simple_read_from_buffer(buf, count, ppos, d->buf, d->pos);
  82. }
  83. void c4iw_log_wr_stats(struct t4_wq *wq, struct t4_cqe *cqe)
  84. {
  85. struct wr_log_entry le;
  86. int idx;
  87. if (!wq->rdev->wr_log)
  88. return;
  89. idx = (atomic_inc_return(&wq->rdev->wr_log_idx) - 1) &
  90. (wq->rdev->wr_log_size - 1);
  91. le.poll_sge_ts = cxgb4_read_sge_timestamp(wq->rdev->lldi.ports[0]);
  92. le.poll_host_time = ktime_get();
  93. le.valid = 1;
  94. le.cqe_sge_ts = CQE_TS(cqe);
  95. if (SQ_TYPE(cqe)) {
  96. le.qid = wq->sq.qid;
  97. le.opcode = CQE_OPCODE(cqe);
  98. le.post_host_time = wq->sq.sw_sq[wq->sq.cidx].host_time;
  99. le.post_sge_ts = wq->sq.sw_sq[wq->sq.cidx].sge_ts;
  100. le.wr_id = CQE_WRID_SQ_IDX(cqe);
  101. } else {
  102. le.qid = wq->rq.qid;
  103. le.opcode = FW_RI_RECEIVE;
  104. le.post_host_time = wq->rq.sw_rq[wq->rq.cidx].host_time;
  105. le.post_sge_ts = wq->rq.sw_rq[wq->rq.cidx].sge_ts;
  106. le.wr_id = CQE_WRID_MSN(cqe);
  107. }
  108. wq->rdev->wr_log[idx] = le;
  109. }
  110. static int wr_log_show(struct seq_file *seq, void *v)
  111. {
  112. struct c4iw_dev *dev = seq->private;
  113. ktime_t prev_time;
  114. struct wr_log_entry *lep;
  115. int prev_time_set = 0;
  116. int idx, end;
  117. #define ts2ns(ts) div64_u64((ts) * dev->rdev.lldi.cclk_ps, 1000)
  118. idx = atomic_read(&dev->rdev.wr_log_idx) &
  119. (dev->rdev.wr_log_size - 1);
  120. end = idx - 1;
  121. if (end < 0)
  122. end = dev->rdev.wr_log_size - 1;
  123. lep = &dev->rdev.wr_log[idx];
  124. while (idx != end) {
  125. if (lep->valid) {
  126. if (!prev_time_set) {
  127. prev_time_set = 1;
  128. prev_time = lep->poll_host_time;
  129. }
  130. seq_printf(seq, "%04u: nsec %llu qid %u opcode "
  131. "%u %s 0x%x host_wr_delta nsec %llu "
  132. "post_sge_ts 0x%llx cqe_sge_ts 0x%llx "
  133. "poll_sge_ts 0x%llx post_poll_delta_ns %llu "
  134. "cqe_poll_delta_ns %llu\n",
  135. idx,
  136. ktime_to_ns(ktime_sub(lep->poll_host_time,
  137. prev_time)),
  138. lep->qid, lep->opcode,
  139. lep->opcode == FW_RI_RECEIVE ?
  140. "msn" : "wrid",
  141. lep->wr_id,
  142. ktime_to_ns(ktime_sub(lep->poll_host_time,
  143. lep->post_host_time)),
  144. lep->post_sge_ts, lep->cqe_sge_ts,
  145. lep->poll_sge_ts,
  146. ts2ns(lep->poll_sge_ts - lep->post_sge_ts),
  147. ts2ns(lep->poll_sge_ts - lep->cqe_sge_ts));
  148. prev_time = lep->poll_host_time;
  149. }
  150. idx++;
  151. if (idx > (dev->rdev.wr_log_size - 1))
  152. idx = 0;
  153. lep = &dev->rdev.wr_log[idx];
  154. }
  155. #undef ts2ns
  156. return 0;
  157. }
  158. static int wr_log_open(struct inode *inode, struct file *file)
  159. {
  160. return single_open(file, wr_log_show, inode->i_private);
  161. }
  162. static ssize_t wr_log_clear(struct file *file, const char __user *buf,
  163. size_t count, loff_t *pos)
  164. {
  165. struct c4iw_dev *dev = ((struct seq_file *)file->private_data)->private;
  166. int i;
  167. if (dev->rdev.wr_log)
  168. for (i = 0; i < dev->rdev.wr_log_size; i++)
  169. dev->rdev.wr_log[i].valid = 0;
  170. return count;
  171. }
  172. static const struct file_operations wr_log_debugfs_fops = {
  173. .owner = THIS_MODULE,
  174. .open = wr_log_open,
  175. .release = single_release,
  176. .read = seq_read,
  177. .llseek = seq_lseek,
  178. .write = wr_log_clear,
  179. };
  180. static struct sockaddr_in zero_sin = {
  181. .sin_family = AF_INET,
  182. };
  183. static struct sockaddr_in6 zero_sin6 = {
  184. .sin6_family = AF_INET6,
  185. };
  186. static void set_ep_sin_addrs(struct c4iw_ep *ep,
  187. struct sockaddr_in **lsin,
  188. struct sockaddr_in **rsin,
  189. struct sockaddr_in **m_lsin,
  190. struct sockaddr_in **m_rsin)
  191. {
  192. struct iw_cm_id *id = ep->com.cm_id;
  193. *m_lsin = (struct sockaddr_in *)&ep->com.local_addr;
  194. *m_rsin = (struct sockaddr_in *)&ep->com.remote_addr;
  195. if (id) {
  196. *lsin = (struct sockaddr_in *)&id->local_addr;
  197. *rsin = (struct sockaddr_in *)&id->remote_addr;
  198. } else {
  199. *lsin = &zero_sin;
  200. *rsin = &zero_sin;
  201. }
  202. }
  203. static void set_ep_sin6_addrs(struct c4iw_ep *ep,
  204. struct sockaddr_in6 **lsin6,
  205. struct sockaddr_in6 **rsin6,
  206. struct sockaddr_in6 **m_lsin6,
  207. struct sockaddr_in6 **m_rsin6)
  208. {
  209. struct iw_cm_id *id = ep->com.cm_id;
  210. *m_lsin6 = (struct sockaddr_in6 *)&ep->com.local_addr;
  211. *m_rsin6 = (struct sockaddr_in6 *)&ep->com.remote_addr;
  212. if (id) {
  213. *lsin6 = (struct sockaddr_in6 *)&id->local_addr;
  214. *rsin6 = (struct sockaddr_in6 *)&id->remote_addr;
  215. } else {
  216. *lsin6 = &zero_sin6;
  217. *rsin6 = &zero_sin6;
  218. }
  219. }
  220. static int dump_qp(int id, void *p, void *data)
  221. {
  222. struct c4iw_qp *qp = p;
  223. struct c4iw_debugfs_data *qpd = data;
  224. int space;
  225. int cc;
  226. if (id != qp->wq.sq.qid)
  227. return 0;
  228. space = qpd->bufsize - qpd->pos - 1;
  229. if (space == 0)
  230. return 1;
  231. if (qp->ep) {
  232. struct c4iw_ep *ep = qp->ep;
  233. if (ep->com.local_addr.ss_family == AF_INET) {
  234. struct sockaddr_in *lsin;
  235. struct sockaddr_in *rsin;
  236. struct sockaddr_in *m_lsin;
  237. struct sockaddr_in *m_rsin;
  238. set_ep_sin_addrs(ep, &lsin, &rsin, &m_lsin, &m_rsin);
  239. cc = snprintf(qpd->buf + qpd->pos, space,
  240. "rc qp sq id %u %s id %u state %u "
  241. "onchip %u ep tid %u state %u "
  242. "%pI4:%u/%u->%pI4:%u/%u\n",
  243. qp->wq.sq.qid, qp->srq ? "srq" : "rq",
  244. qp->srq ? qp->srq->idx : qp->wq.rq.qid,
  245. (int)qp->attr.state,
  246. qp->wq.sq.flags & T4_SQ_ONCHIP,
  247. ep->hwtid, (int)ep->com.state,
  248. &lsin->sin_addr, ntohs(lsin->sin_port),
  249. ntohs(m_lsin->sin_port),
  250. &rsin->sin_addr, ntohs(rsin->sin_port),
  251. ntohs(m_rsin->sin_port));
  252. } else {
  253. struct sockaddr_in6 *lsin6;
  254. struct sockaddr_in6 *rsin6;
  255. struct sockaddr_in6 *m_lsin6;
  256. struct sockaddr_in6 *m_rsin6;
  257. set_ep_sin6_addrs(ep, &lsin6, &rsin6, &m_lsin6,
  258. &m_rsin6);
  259. cc = snprintf(qpd->buf + qpd->pos, space,
  260. "rc qp sq id %u rq id %u state %u "
  261. "onchip %u ep tid %u state %u "
  262. "%pI6:%u/%u->%pI6:%u/%u\n",
  263. qp->wq.sq.qid, qp->wq.rq.qid,
  264. (int)qp->attr.state,
  265. qp->wq.sq.flags & T4_SQ_ONCHIP,
  266. ep->hwtid, (int)ep->com.state,
  267. &lsin6->sin6_addr,
  268. ntohs(lsin6->sin6_port),
  269. ntohs(m_lsin6->sin6_port),
  270. &rsin6->sin6_addr,
  271. ntohs(rsin6->sin6_port),
  272. ntohs(m_rsin6->sin6_port));
  273. }
  274. } else
  275. cc = snprintf(qpd->buf + qpd->pos, space,
  276. "qp sq id %u rq id %u state %u onchip %u\n",
  277. qp->wq.sq.qid, qp->wq.rq.qid,
  278. (int)qp->attr.state,
  279. qp->wq.sq.flags & T4_SQ_ONCHIP);
  280. if (cc < space)
  281. qpd->pos += cc;
  282. return 0;
  283. }
  284. static int qp_release(struct inode *inode, struct file *file)
  285. {
  286. struct c4iw_debugfs_data *qpd = file->private_data;
  287. if (!qpd) {
  288. pr_info("%s null qpd?\n", __func__);
  289. return 0;
  290. }
  291. vfree(qpd->buf);
  292. kfree(qpd);
  293. return 0;
  294. }
  295. static int qp_open(struct inode *inode, struct file *file)
  296. {
  297. struct c4iw_debugfs_data *qpd;
  298. int count = 1;
  299. qpd = kmalloc(sizeof *qpd, GFP_KERNEL);
  300. if (!qpd)
  301. return -ENOMEM;
  302. qpd->devp = inode->i_private;
  303. qpd->pos = 0;
  304. spin_lock_irq(&qpd->devp->lock);
  305. idr_for_each(&qpd->devp->qpidr, count_idrs, &count);
  306. spin_unlock_irq(&qpd->devp->lock);
  307. qpd->bufsize = count * 180;
  308. qpd->buf = vmalloc(qpd->bufsize);
  309. if (!qpd->buf) {
  310. kfree(qpd);
  311. return -ENOMEM;
  312. }
  313. spin_lock_irq(&qpd->devp->lock);
  314. idr_for_each(&qpd->devp->qpidr, dump_qp, qpd);
  315. spin_unlock_irq(&qpd->devp->lock);
  316. qpd->buf[qpd->pos++] = 0;
  317. file->private_data = qpd;
  318. return 0;
  319. }
  320. static const struct file_operations qp_debugfs_fops = {
  321. .owner = THIS_MODULE,
  322. .open = qp_open,
  323. .release = qp_release,
  324. .read = debugfs_read,
  325. .llseek = default_llseek,
  326. };
  327. static int dump_stag(int id, void *p, void *data)
  328. {
  329. struct c4iw_debugfs_data *stagd = data;
  330. int space;
  331. int cc;
  332. struct fw_ri_tpte tpte;
  333. int ret;
  334. space = stagd->bufsize - stagd->pos - 1;
  335. if (space == 0)
  336. return 1;
  337. ret = cxgb4_read_tpte(stagd->devp->rdev.lldi.ports[0], (u32)id<<8,
  338. (__be32 *)&tpte);
  339. if (ret) {
  340. dev_err(&stagd->devp->rdev.lldi.pdev->dev,
  341. "%s cxgb4_read_tpte err %d\n", __func__, ret);
  342. return ret;
  343. }
  344. cc = snprintf(stagd->buf + stagd->pos, space,
  345. "stag: idx 0x%x valid %d key 0x%x state %d pdid %d "
  346. "perm 0x%x ps %d len 0x%llx va 0x%llx\n",
  347. (u32)id<<8,
  348. FW_RI_TPTE_VALID_G(ntohl(tpte.valid_to_pdid)),
  349. FW_RI_TPTE_STAGKEY_G(ntohl(tpte.valid_to_pdid)),
  350. FW_RI_TPTE_STAGSTATE_G(ntohl(tpte.valid_to_pdid)),
  351. FW_RI_TPTE_PDID_G(ntohl(tpte.valid_to_pdid)),
  352. FW_RI_TPTE_PERM_G(ntohl(tpte.locread_to_qpid)),
  353. FW_RI_TPTE_PS_G(ntohl(tpte.locread_to_qpid)),
  354. ((u64)ntohl(tpte.len_hi) << 32) | ntohl(tpte.len_lo),
  355. ((u64)ntohl(tpte.va_hi) << 32) | ntohl(tpte.va_lo_fbo));
  356. if (cc < space)
  357. stagd->pos += cc;
  358. return 0;
  359. }
  360. static int stag_release(struct inode *inode, struct file *file)
  361. {
  362. struct c4iw_debugfs_data *stagd = file->private_data;
  363. if (!stagd) {
  364. pr_info("%s null stagd?\n", __func__);
  365. return 0;
  366. }
  367. vfree(stagd->buf);
  368. kfree(stagd);
  369. return 0;
  370. }
  371. static int stag_open(struct inode *inode, struct file *file)
  372. {
  373. struct c4iw_debugfs_data *stagd;
  374. int ret = 0;
  375. int count = 1;
  376. stagd = kmalloc(sizeof *stagd, GFP_KERNEL);
  377. if (!stagd) {
  378. ret = -ENOMEM;
  379. goto out;
  380. }
  381. stagd->devp = inode->i_private;
  382. stagd->pos = 0;
  383. spin_lock_irq(&stagd->devp->lock);
  384. idr_for_each(&stagd->devp->mmidr, count_idrs, &count);
  385. spin_unlock_irq(&stagd->devp->lock);
  386. stagd->bufsize = count * 256;
  387. stagd->buf = vmalloc(stagd->bufsize);
  388. if (!stagd->buf) {
  389. ret = -ENOMEM;
  390. goto err1;
  391. }
  392. spin_lock_irq(&stagd->devp->lock);
  393. idr_for_each(&stagd->devp->mmidr, dump_stag, stagd);
  394. spin_unlock_irq(&stagd->devp->lock);
  395. stagd->buf[stagd->pos++] = 0;
  396. file->private_data = stagd;
  397. goto out;
  398. err1:
  399. kfree(stagd);
  400. out:
  401. return ret;
  402. }
  403. static const struct file_operations stag_debugfs_fops = {
  404. .owner = THIS_MODULE,
  405. .open = stag_open,
  406. .release = stag_release,
  407. .read = debugfs_read,
  408. .llseek = default_llseek,
  409. };
  410. static char *db_state_str[] = {"NORMAL", "FLOW_CONTROL", "RECOVERY", "STOPPED"};
  411. static int stats_show(struct seq_file *seq, void *v)
  412. {
  413. struct c4iw_dev *dev = seq->private;
  414. seq_printf(seq, " Object: %10s %10s %10s %10s\n", "Total", "Current",
  415. "Max", "Fail");
  416. seq_printf(seq, " PDID: %10llu %10llu %10llu %10llu\n",
  417. dev->rdev.stats.pd.total, dev->rdev.stats.pd.cur,
  418. dev->rdev.stats.pd.max, dev->rdev.stats.pd.fail);
  419. seq_printf(seq, " QID: %10llu %10llu %10llu %10llu\n",
  420. dev->rdev.stats.qid.total, dev->rdev.stats.qid.cur,
  421. dev->rdev.stats.qid.max, dev->rdev.stats.qid.fail);
  422. seq_printf(seq, " SRQS: %10llu %10llu %10llu %10llu\n",
  423. dev->rdev.stats.srqt.total, dev->rdev.stats.srqt.cur,
  424. dev->rdev.stats.srqt.max, dev->rdev.stats.srqt.fail);
  425. seq_printf(seq, " TPTMEM: %10llu %10llu %10llu %10llu\n",
  426. dev->rdev.stats.stag.total, dev->rdev.stats.stag.cur,
  427. dev->rdev.stats.stag.max, dev->rdev.stats.stag.fail);
  428. seq_printf(seq, " PBLMEM: %10llu %10llu %10llu %10llu\n",
  429. dev->rdev.stats.pbl.total, dev->rdev.stats.pbl.cur,
  430. dev->rdev.stats.pbl.max, dev->rdev.stats.pbl.fail);
  431. seq_printf(seq, " RQTMEM: %10llu %10llu %10llu %10llu\n",
  432. dev->rdev.stats.rqt.total, dev->rdev.stats.rqt.cur,
  433. dev->rdev.stats.rqt.max, dev->rdev.stats.rqt.fail);
  434. seq_printf(seq, " OCQPMEM: %10llu %10llu %10llu %10llu\n",
  435. dev->rdev.stats.ocqp.total, dev->rdev.stats.ocqp.cur,
  436. dev->rdev.stats.ocqp.max, dev->rdev.stats.ocqp.fail);
  437. seq_printf(seq, " DB FULL: %10llu\n", dev->rdev.stats.db_full);
  438. seq_printf(seq, " DB EMPTY: %10llu\n", dev->rdev.stats.db_empty);
  439. seq_printf(seq, " DB DROP: %10llu\n", dev->rdev.stats.db_drop);
  440. seq_printf(seq, " DB State: %s Transitions %llu FC Interruptions %llu\n",
  441. db_state_str[dev->db_state],
  442. dev->rdev.stats.db_state_transitions,
  443. dev->rdev.stats.db_fc_interruptions);
  444. seq_printf(seq, "TCAM_FULL: %10llu\n", dev->rdev.stats.tcam_full);
  445. seq_printf(seq, "ACT_OFLD_CONN_FAILS: %10llu\n",
  446. dev->rdev.stats.act_ofld_conn_fails);
  447. seq_printf(seq, "PAS_OFLD_CONN_FAILS: %10llu\n",
  448. dev->rdev.stats.pas_ofld_conn_fails);
  449. seq_printf(seq, "NEG_ADV_RCVD: %10llu\n", dev->rdev.stats.neg_adv);
  450. seq_printf(seq, "AVAILABLE IRD: %10u\n", dev->avail_ird);
  451. return 0;
  452. }
  453. static int stats_open(struct inode *inode, struct file *file)
  454. {
  455. return single_open(file, stats_show, inode->i_private);
  456. }
  457. static ssize_t stats_clear(struct file *file, const char __user *buf,
  458. size_t count, loff_t *pos)
  459. {
  460. struct c4iw_dev *dev = ((struct seq_file *)file->private_data)->private;
  461. mutex_lock(&dev->rdev.stats.lock);
  462. dev->rdev.stats.pd.max = 0;
  463. dev->rdev.stats.pd.fail = 0;
  464. dev->rdev.stats.qid.max = 0;
  465. dev->rdev.stats.qid.fail = 0;
  466. dev->rdev.stats.stag.max = 0;
  467. dev->rdev.stats.stag.fail = 0;
  468. dev->rdev.stats.pbl.max = 0;
  469. dev->rdev.stats.pbl.fail = 0;
  470. dev->rdev.stats.rqt.max = 0;
  471. dev->rdev.stats.rqt.fail = 0;
  472. dev->rdev.stats.rqt.max = 0;
  473. dev->rdev.stats.rqt.fail = 0;
  474. dev->rdev.stats.ocqp.max = 0;
  475. dev->rdev.stats.ocqp.fail = 0;
  476. dev->rdev.stats.db_full = 0;
  477. dev->rdev.stats.db_empty = 0;
  478. dev->rdev.stats.db_drop = 0;
  479. dev->rdev.stats.db_state_transitions = 0;
  480. dev->rdev.stats.tcam_full = 0;
  481. dev->rdev.stats.act_ofld_conn_fails = 0;
  482. dev->rdev.stats.pas_ofld_conn_fails = 0;
  483. mutex_unlock(&dev->rdev.stats.lock);
  484. return count;
  485. }
  486. static const struct file_operations stats_debugfs_fops = {
  487. .owner = THIS_MODULE,
  488. .open = stats_open,
  489. .release = single_release,
  490. .read = seq_read,
  491. .llseek = seq_lseek,
  492. .write = stats_clear,
  493. };
  494. static int dump_ep(int id, void *p, void *data)
  495. {
  496. struct c4iw_ep *ep = p;
  497. struct c4iw_debugfs_data *epd = data;
  498. int space;
  499. int cc;
  500. space = epd->bufsize - epd->pos - 1;
  501. if (space == 0)
  502. return 1;
  503. if (ep->com.local_addr.ss_family == AF_INET) {
  504. struct sockaddr_in *lsin;
  505. struct sockaddr_in *rsin;
  506. struct sockaddr_in *m_lsin;
  507. struct sockaddr_in *m_rsin;
  508. set_ep_sin_addrs(ep, &lsin, &rsin, &m_lsin, &m_rsin);
  509. cc = snprintf(epd->buf + epd->pos, space,
  510. "ep %p cm_id %p qp %p state %d flags 0x%lx "
  511. "history 0x%lx hwtid %d atid %d "
  512. "conn_na %u abort_na %u "
  513. "%pI4:%d/%d <-> %pI4:%d/%d\n",
  514. ep, ep->com.cm_id, ep->com.qp,
  515. (int)ep->com.state, ep->com.flags,
  516. ep->com.history, ep->hwtid, ep->atid,
  517. ep->stats.connect_neg_adv,
  518. ep->stats.abort_neg_adv,
  519. &lsin->sin_addr, ntohs(lsin->sin_port),
  520. ntohs(m_lsin->sin_port),
  521. &rsin->sin_addr, ntohs(rsin->sin_port),
  522. ntohs(m_rsin->sin_port));
  523. } else {
  524. struct sockaddr_in6 *lsin6;
  525. struct sockaddr_in6 *rsin6;
  526. struct sockaddr_in6 *m_lsin6;
  527. struct sockaddr_in6 *m_rsin6;
  528. set_ep_sin6_addrs(ep, &lsin6, &rsin6, &m_lsin6, &m_rsin6);
  529. cc = snprintf(epd->buf + epd->pos, space,
  530. "ep %p cm_id %p qp %p state %d flags 0x%lx "
  531. "history 0x%lx hwtid %d atid %d "
  532. "conn_na %u abort_na %u "
  533. "%pI6:%d/%d <-> %pI6:%d/%d\n",
  534. ep, ep->com.cm_id, ep->com.qp,
  535. (int)ep->com.state, ep->com.flags,
  536. ep->com.history, ep->hwtid, ep->atid,
  537. ep->stats.connect_neg_adv,
  538. ep->stats.abort_neg_adv,
  539. &lsin6->sin6_addr, ntohs(lsin6->sin6_port),
  540. ntohs(m_lsin6->sin6_port),
  541. &rsin6->sin6_addr, ntohs(rsin6->sin6_port),
  542. ntohs(m_rsin6->sin6_port));
  543. }
  544. if (cc < space)
  545. epd->pos += cc;
  546. return 0;
  547. }
  548. static int dump_listen_ep(int id, void *p, void *data)
  549. {
  550. struct c4iw_listen_ep *ep = p;
  551. struct c4iw_debugfs_data *epd = data;
  552. int space;
  553. int cc;
  554. space = epd->bufsize - epd->pos - 1;
  555. if (space == 0)
  556. return 1;
  557. if (ep->com.local_addr.ss_family == AF_INET) {
  558. struct sockaddr_in *lsin = (struct sockaddr_in *)
  559. &ep->com.cm_id->local_addr;
  560. struct sockaddr_in *m_lsin = (struct sockaddr_in *)
  561. &ep->com.cm_id->m_local_addr;
  562. cc = snprintf(epd->buf + epd->pos, space,
  563. "ep %p cm_id %p state %d flags 0x%lx stid %d "
  564. "backlog %d %pI4:%d/%d\n",
  565. ep, ep->com.cm_id, (int)ep->com.state,
  566. ep->com.flags, ep->stid, ep->backlog,
  567. &lsin->sin_addr, ntohs(lsin->sin_port),
  568. ntohs(m_lsin->sin_port));
  569. } else {
  570. struct sockaddr_in6 *lsin6 = (struct sockaddr_in6 *)
  571. &ep->com.cm_id->local_addr;
  572. struct sockaddr_in6 *m_lsin6 = (struct sockaddr_in6 *)
  573. &ep->com.cm_id->m_local_addr;
  574. cc = snprintf(epd->buf + epd->pos, space,
  575. "ep %p cm_id %p state %d flags 0x%lx stid %d "
  576. "backlog %d %pI6:%d/%d\n",
  577. ep, ep->com.cm_id, (int)ep->com.state,
  578. ep->com.flags, ep->stid, ep->backlog,
  579. &lsin6->sin6_addr, ntohs(lsin6->sin6_port),
  580. ntohs(m_lsin6->sin6_port));
  581. }
  582. if (cc < space)
  583. epd->pos += cc;
  584. return 0;
  585. }
  586. static int ep_release(struct inode *inode, struct file *file)
  587. {
  588. struct c4iw_debugfs_data *epd = file->private_data;
  589. if (!epd) {
  590. pr_info("%s null qpd?\n", __func__);
  591. return 0;
  592. }
  593. vfree(epd->buf);
  594. kfree(epd);
  595. return 0;
  596. }
  597. static int ep_open(struct inode *inode, struct file *file)
  598. {
  599. struct c4iw_debugfs_data *epd;
  600. int ret = 0;
  601. int count = 1;
  602. epd = kmalloc(sizeof(*epd), GFP_KERNEL);
  603. if (!epd) {
  604. ret = -ENOMEM;
  605. goto out;
  606. }
  607. epd->devp = inode->i_private;
  608. epd->pos = 0;
  609. spin_lock_irq(&epd->devp->lock);
  610. idr_for_each(&epd->devp->hwtid_idr, count_idrs, &count);
  611. idr_for_each(&epd->devp->atid_idr, count_idrs, &count);
  612. idr_for_each(&epd->devp->stid_idr, count_idrs, &count);
  613. spin_unlock_irq(&epd->devp->lock);
  614. epd->bufsize = count * 240;
  615. epd->buf = vmalloc(epd->bufsize);
  616. if (!epd->buf) {
  617. ret = -ENOMEM;
  618. goto err1;
  619. }
  620. spin_lock_irq(&epd->devp->lock);
  621. idr_for_each(&epd->devp->hwtid_idr, dump_ep, epd);
  622. idr_for_each(&epd->devp->atid_idr, dump_ep, epd);
  623. idr_for_each(&epd->devp->stid_idr, dump_listen_ep, epd);
  624. spin_unlock_irq(&epd->devp->lock);
  625. file->private_data = epd;
  626. goto out;
  627. err1:
  628. kfree(epd);
  629. out:
  630. return ret;
  631. }
  632. static const struct file_operations ep_debugfs_fops = {
  633. .owner = THIS_MODULE,
  634. .open = ep_open,
  635. .release = ep_release,
  636. .read = debugfs_read,
  637. };
  638. static int setup_debugfs(struct c4iw_dev *devp)
  639. {
  640. if (!devp->debugfs_root)
  641. return -1;
  642. debugfs_create_file_size("qps", S_IWUSR, devp->debugfs_root,
  643. (void *)devp, &qp_debugfs_fops, 4096);
  644. debugfs_create_file_size("stags", S_IWUSR, devp->debugfs_root,
  645. (void *)devp, &stag_debugfs_fops, 4096);
  646. debugfs_create_file_size("stats", S_IWUSR, devp->debugfs_root,
  647. (void *)devp, &stats_debugfs_fops, 4096);
  648. debugfs_create_file_size("eps", S_IWUSR, devp->debugfs_root,
  649. (void *)devp, &ep_debugfs_fops, 4096);
  650. if (c4iw_wr_log)
  651. debugfs_create_file_size("wr_log", S_IWUSR, devp->debugfs_root,
  652. (void *)devp, &wr_log_debugfs_fops, 4096);
  653. return 0;
  654. }
  655. void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
  656. struct c4iw_dev_ucontext *uctx)
  657. {
  658. struct list_head *pos, *nxt;
  659. struct c4iw_qid_list *entry;
  660. mutex_lock(&uctx->lock);
  661. list_for_each_safe(pos, nxt, &uctx->qpids) {
  662. entry = list_entry(pos, struct c4iw_qid_list, entry);
  663. list_del_init(&entry->entry);
  664. if (!(entry->qid & rdev->qpmask)) {
  665. c4iw_put_resource(&rdev->resource.qid_table,
  666. entry->qid);
  667. mutex_lock(&rdev->stats.lock);
  668. rdev->stats.qid.cur -= rdev->qpmask + 1;
  669. mutex_unlock(&rdev->stats.lock);
  670. }
  671. kfree(entry);
  672. }
  673. list_for_each_safe(pos, nxt, &uctx->cqids) {
  674. entry = list_entry(pos, struct c4iw_qid_list, entry);
  675. list_del_init(&entry->entry);
  676. kfree(entry);
  677. }
  678. mutex_unlock(&uctx->lock);
  679. }
  680. void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
  681. struct c4iw_dev_ucontext *uctx)
  682. {
  683. INIT_LIST_HEAD(&uctx->qpids);
  684. INIT_LIST_HEAD(&uctx->cqids);
  685. mutex_init(&uctx->lock);
  686. }
  687. /* Caller takes care of locking if needed */
  688. static int c4iw_rdev_open(struct c4iw_rdev *rdev)
  689. {
  690. int err;
  691. c4iw_init_dev_ucontext(rdev, &rdev->uctx);
  692. /*
  693. * This implementation assumes udb_density == ucq_density! Eventually
  694. * we might need to support this but for now fail the open. Also the
  695. * cqid and qpid range must match for now.
  696. */
  697. if (rdev->lldi.udb_density != rdev->lldi.ucq_density) {
  698. pr_err("%s: unsupported udb/ucq densities %u/%u\n",
  699. pci_name(rdev->lldi.pdev), rdev->lldi.udb_density,
  700. rdev->lldi.ucq_density);
  701. return -EINVAL;
  702. }
  703. if (rdev->lldi.vr->qp.start != rdev->lldi.vr->cq.start ||
  704. rdev->lldi.vr->qp.size != rdev->lldi.vr->cq.size) {
  705. pr_err("%s: unsupported qp and cq id ranges qp start %u size %u cq start %u size %u\n",
  706. pci_name(rdev->lldi.pdev), rdev->lldi.vr->qp.start,
  707. rdev->lldi.vr->qp.size, rdev->lldi.vr->cq.size,
  708. rdev->lldi.vr->cq.size);
  709. return -EINVAL;
  710. }
  711. rdev->qpmask = rdev->lldi.udb_density - 1;
  712. rdev->cqmask = rdev->lldi.ucq_density - 1;
  713. pr_debug("dev %s stag start 0x%0x size 0x%0x num stags %d pbl start 0x%0x size 0x%0x rq start 0x%0x size 0x%0x qp qid start %u size %u cq qid start %u size %u srq size %u\n",
  714. pci_name(rdev->lldi.pdev), rdev->lldi.vr->stag.start,
  715. rdev->lldi.vr->stag.size, c4iw_num_stags(rdev),
  716. rdev->lldi.vr->pbl.start,
  717. rdev->lldi.vr->pbl.size, rdev->lldi.vr->rq.start,
  718. rdev->lldi.vr->rq.size,
  719. rdev->lldi.vr->qp.start,
  720. rdev->lldi.vr->qp.size,
  721. rdev->lldi.vr->cq.start,
  722. rdev->lldi.vr->cq.size,
  723. rdev->lldi.vr->srq.size);
  724. pr_debug("udb %pR db_reg %p gts_reg %p qpmask 0x%x cqmask 0x%x\n",
  725. &rdev->lldi.pdev->resource[2],
  726. rdev->lldi.db_reg, rdev->lldi.gts_reg,
  727. rdev->qpmask, rdev->cqmask);
  728. if (c4iw_num_stags(rdev) == 0)
  729. return -EINVAL;
  730. rdev->stats.pd.total = T4_MAX_NUM_PD;
  731. rdev->stats.stag.total = rdev->lldi.vr->stag.size;
  732. rdev->stats.pbl.total = rdev->lldi.vr->pbl.size;
  733. rdev->stats.rqt.total = rdev->lldi.vr->rq.size;
  734. rdev->stats.srqt.total = rdev->lldi.vr->srq.size;
  735. rdev->stats.ocqp.total = rdev->lldi.vr->ocq.size;
  736. rdev->stats.qid.total = rdev->lldi.vr->qp.size;
  737. err = c4iw_init_resource(rdev, c4iw_num_stags(rdev),
  738. T4_MAX_NUM_PD, rdev->lldi.vr->srq.size);
  739. if (err) {
  740. pr_err("error %d initializing resources\n", err);
  741. return err;
  742. }
  743. err = c4iw_pblpool_create(rdev);
  744. if (err) {
  745. pr_err("error %d initializing pbl pool\n", err);
  746. goto destroy_resource;
  747. }
  748. err = c4iw_rqtpool_create(rdev);
  749. if (err) {
  750. pr_err("error %d initializing rqt pool\n", err);
  751. goto destroy_pblpool;
  752. }
  753. err = c4iw_ocqp_pool_create(rdev);
  754. if (err) {
  755. pr_err("error %d initializing ocqp pool\n", err);
  756. goto destroy_rqtpool;
  757. }
  758. rdev->status_page = (struct t4_dev_status_page *)
  759. __get_free_page(GFP_KERNEL);
  760. if (!rdev->status_page) {
  761. err = -ENOMEM;
  762. goto destroy_ocqp_pool;
  763. }
  764. rdev->status_page->qp_start = rdev->lldi.vr->qp.start;
  765. rdev->status_page->qp_size = rdev->lldi.vr->qp.size;
  766. rdev->status_page->cq_start = rdev->lldi.vr->cq.start;
  767. rdev->status_page->cq_size = rdev->lldi.vr->cq.size;
  768. rdev->status_page->write_cmpl_supported = rdev->lldi.write_cmpl_support;
  769. if (c4iw_wr_log) {
  770. rdev->wr_log = kcalloc(1 << c4iw_wr_log_size_order,
  771. sizeof(*rdev->wr_log),
  772. GFP_KERNEL);
  773. if (rdev->wr_log) {
  774. rdev->wr_log_size = 1 << c4iw_wr_log_size_order;
  775. atomic_set(&rdev->wr_log_idx, 0);
  776. }
  777. }
  778. rdev->free_workq = create_singlethread_workqueue("iw_cxgb4_free");
  779. if (!rdev->free_workq) {
  780. err = -ENOMEM;
  781. goto err_free_status_page_and_wr_log;
  782. }
  783. rdev->status_page->db_off = 0;
  784. init_completion(&rdev->rqt_compl);
  785. init_completion(&rdev->pbl_compl);
  786. kref_init(&rdev->rqt_kref);
  787. kref_init(&rdev->pbl_kref);
  788. return 0;
  789. err_free_status_page_and_wr_log:
  790. if (c4iw_wr_log && rdev->wr_log)
  791. kfree(rdev->wr_log);
  792. free_page((unsigned long)rdev->status_page);
  793. destroy_ocqp_pool:
  794. c4iw_ocqp_pool_destroy(rdev);
  795. destroy_rqtpool:
  796. c4iw_rqtpool_destroy(rdev);
  797. destroy_pblpool:
  798. c4iw_pblpool_destroy(rdev);
  799. destroy_resource:
  800. c4iw_destroy_resource(&rdev->resource);
  801. return err;
  802. }
  803. static void c4iw_rdev_close(struct c4iw_rdev *rdev)
  804. {
  805. kfree(rdev->wr_log);
  806. c4iw_release_dev_ucontext(rdev, &rdev->uctx);
  807. free_page((unsigned long)rdev->status_page);
  808. c4iw_pblpool_destroy(rdev);
  809. c4iw_rqtpool_destroy(rdev);
  810. wait_for_completion(&rdev->pbl_compl);
  811. wait_for_completion(&rdev->rqt_compl);
  812. c4iw_ocqp_pool_destroy(rdev);
  813. destroy_workqueue(rdev->free_workq);
  814. c4iw_destroy_resource(&rdev->resource);
  815. }
  816. void c4iw_dealloc(struct uld_ctx *ctx)
  817. {
  818. c4iw_rdev_close(&ctx->dev->rdev);
  819. WARN_ON_ONCE(!idr_is_empty(&ctx->dev->cqidr));
  820. idr_destroy(&ctx->dev->cqidr);
  821. WARN_ON_ONCE(!idr_is_empty(&ctx->dev->qpidr));
  822. idr_destroy(&ctx->dev->qpidr);
  823. WARN_ON_ONCE(!idr_is_empty(&ctx->dev->mmidr));
  824. idr_destroy(&ctx->dev->mmidr);
  825. wait_event(ctx->dev->wait, idr_is_empty(&ctx->dev->hwtid_idr));
  826. idr_destroy(&ctx->dev->hwtid_idr);
  827. idr_destroy(&ctx->dev->stid_idr);
  828. idr_destroy(&ctx->dev->atid_idr);
  829. if (ctx->dev->rdev.bar2_kva)
  830. iounmap(ctx->dev->rdev.bar2_kva);
  831. if (ctx->dev->rdev.oc_mw_kva)
  832. iounmap(ctx->dev->rdev.oc_mw_kva);
  833. ib_dealloc_device(&ctx->dev->ibdev);
  834. ctx->dev = NULL;
  835. }
  836. static void c4iw_remove(struct uld_ctx *ctx)
  837. {
  838. pr_debug("c4iw_dev %p\n", ctx->dev);
  839. c4iw_unregister_device(ctx->dev);
  840. c4iw_dealloc(ctx);
  841. }
  842. static int rdma_supported(const struct cxgb4_lld_info *infop)
  843. {
  844. return infop->vr->stag.size > 0 && infop->vr->pbl.size > 0 &&
  845. infop->vr->rq.size > 0 && infop->vr->qp.size > 0 &&
  846. infop->vr->cq.size > 0;
  847. }
  848. static struct c4iw_dev *c4iw_alloc(const struct cxgb4_lld_info *infop)
  849. {
  850. struct c4iw_dev *devp;
  851. int ret;
  852. if (!rdma_supported(infop)) {
  853. pr_info("%s: RDMA not supported on this device\n",
  854. pci_name(infop->pdev));
  855. return ERR_PTR(-ENOSYS);
  856. }
  857. if (!ocqp_supported(infop))
  858. pr_info("%s: On-Chip Queues not supported on this device\n",
  859. pci_name(infop->pdev));
  860. devp = (struct c4iw_dev *)ib_alloc_device(sizeof(*devp));
  861. if (!devp) {
  862. pr_err("Cannot allocate ib device\n");
  863. return ERR_PTR(-ENOMEM);
  864. }
  865. devp->rdev.lldi = *infop;
  866. /* init various hw-queue params based on lld info */
  867. pr_debug("Ing. padding boundary is %d, egrsstatuspagesize = %d\n",
  868. devp->rdev.lldi.sge_ingpadboundary,
  869. devp->rdev.lldi.sge_egrstatuspagesize);
  870. devp->rdev.hw_queue.t4_eq_status_entries =
  871. devp->rdev.lldi.sge_egrstatuspagesize / 64;
  872. devp->rdev.hw_queue.t4_max_eq_size = 65520;
  873. devp->rdev.hw_queue.t4_max_iq_size = 65520;
  874. devp->rdev.hw_queue.t4_max_rq_size = 8192 -
  875. devp->rdev.hw_queue.t4_eq_status_entries - 1;
  876. devp->rdev.hw_queue.t4_max_sq_size =
  877. devp->rdev.hw_queue.t4_max_eq_size -
  878. devp->rdev.hw_queue.t4_eq_status_entries - 1;
  879. devp->rdev.hw_queue.t4_max_qp_depth =
  880. devp->rdev.hw_queue.t4_max_rq_size;
  881. devp->rdev.hw_queue.t4_max_cq_depth =
  882. devp->rdev.hw_queue.t4_max_iq_size - 2;
  883. devp->rdev.hw_queue.t4_stat_len =
  884. devp->rdev.lldi.sge_egrstatuspagesize;
  885. /*
  886. * For T5/T6 devices, we map all of BAR2 with WC.
  887. * For T4 devices with onchip qp mem, we map only that part
  888. * of BAR2 with WC.
  889. */
  890. devp->rdev.bar2_pa = pci_resource_start(devp->rdev.lldi.pdev, 2);
  891. if (!is_t4(devp->rdev.lldi.adapter_type)) {
  892. devp->rdev.bar2_kva = ioremap_wc(devp->rdev.bar2_pa,
  893. pci_resource_len(devp->rdev.lldi.pdev, 2));
  894. if (!devp->rdev.bar2_kva) {
  895. pr_err("Unable to ioremap BAR2\n");
  896. ib_dealloc_device(&devp->ibdev);
  897. return ERR_PTR(-EINVAL);
  898. }
  899. } else if (ocqp_supported(infop)) {
  900. devp->rdev.oc_mw_pa =
  901. pci_resource_start(devp->rdev.lldi.pdev, 2) +
  902. pci_resource_len(devp->rdev.lldi.pdev, 2) -
  903. roundup_pow_of_two(devp->rdev.lldi.vr->ocq.size);
  904. devp->rdev.oc_mw_kva = ioremap_wc(devp->rdev.oc_mw_pa,
  905. devp->rdev.lldi.vr->ocq.size);
  906. if (!devp->rdev.oc_mw_kva) {
  907. pr_err("Unable to ioremap onchip mem\n");
  908. ib_dealloc_device(&devp->ibdev);
  909. return ERR_PTR(-EINVAL);
  910. }
  911. }
  912. pr_debug("ocq memory: hw_start 0x%x size %u mw_pa 0x%lx mw_kva %p\n",
  913. devp->rdev.lldi.vr->ocq.start, devp->rdev.lldi.vr->ocq.size,
  914. devp->rdev.oc_mw_pa, devp->rdev.oc_mw_kva);
  915. ret = c4iw_rdev_open(&devp->rdev);
  916. if (ret) {
  917. pr_err("Unable to open CXIO rdev err %d\n", ret);
  918. ib_dealloc_device(&devp->ibdev);
  919. return ERR_PTR(ret);
  920. }
  921. idr_init(&devp->cqidr);
  922. idr_init(&devp->qpidr);
  923. idr_init(&devp->mmidr);
  924. idr_init(&devp->hwtid_idr);
  925. idr_init(&devp->stid_idr);
  926. idr_init(&devp->atid_idr);
  927. spin_lock_init(&devp->lock);
  928. mutex_init(&devp->rdev.stats.lock);
  929. mutex_init(&devp->db_mutex);
  930. INIT_LIST_HEAD(&devp->db_fc_list);
  931. init_waitqueue_head(&devp->wait);
  932. devp->avail_ird = devp->rdev.lldi.max_ird_adapter;
  933. if (c4iw_debugfs_root) {
  934. devp->debugfs_root = debugfs_create_dir(
  935. pci_name(devp->rdev.lldi.pdev),
  936. c4iw_debugfs_root);
  937. setup_debugfs(devp);
  938. }
  939. return devp;
  940. }
  941. static void *c4iw_uld_add(const struct cxgb4_lld_info *infop)
  942. {
  943. struct uld_ctx *ctx;
  944. static int vers_printed;
  945. int i;
  946. if (!vers_printed++)
  947. pr_info("Chelsio T4/T5 RDMA Driver - version %s\n",
  948. DRV_VERSION);
  949. ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
  950. if (!ctx) {
  951. ctx = ERR_PTR(-ENOMEM);
  952. goto out;
  953. }
  954. ctx->lldi = *infop;
  955. pr_debug("found device %s nchan %u nrxq %u ntxq %u nports %u\n",
  956. pci_name(ctx->lldi.pdev),
  957. ctx->lldi.nchan, ctx->lldi.nrxq,
  958. ctx->lldi.ntxq, ctx->lldi.nports);
  959. mutex_lock(&dev_mutex);
  960. list_add_tail(&ctx->entry, &uld_ctx_list);
  961. mutex_unlock(&dev_mutex);
  962. for (i = 0; i < ctx->lldi.nrxq; i++)
  963. pr_debug("rxqid[%u] %u\n", i, ctx->lldi.rxq_ids[i]);
  964. out:
  965. return ctx;
  966. }
  967. static inline struct sk_buff *copy_gl_to_skb_pkt(const struct pkt_gl *gl,
  968. const __be64 *rsp,
  969. u32 pktshift)
  970. {
  971. struct sk_buff *skb;
  972. /*
  973. * Allocate space for cpl_pass_accept_req which will be synthesized by
  974. * driver. Once the driver synthesizes the request the skb will go
  975. * through the regular cpl_pass_accept_req processing.
  976. * The math here assumes sizeof cpl_pass_accept_req >= sizeof
  977. * cpl_rx_pkt.
  978. */
  979. skb = alloc_skb(gl->tot_len + sizeof(struct cpl_pass_accept_req) +
  980. sizeof(struct rss_header) - pktshift, GFP_ATOMIC);
  981. if (unlikely(!skb))
  982. return NULL;
  983. __skb_put(skb, gl->tot_len + sizeof(struct cpl_pass_accept_req) +
  984. sizeof(struct rss_header) - pktshift);
  985. /*
  986. * This skb will contain:
  987. * rss_header from the rspq descriptor (1 flit)
  988. * cpl_rx_pkt struct from the rspq descriptor (2 flits)
  989. * space for the difference between the size of an
  990. * rx_pkt and pass_accept_req cpl (1 flit)
  991. * the packet data from the gl
  992. */
  993. skb_copy_to_linear_data(skb, rsp, sizeof(struct cpl_pass_accept_req) +
  994. sizeof(struct rss_header));
  995. skb_copy_to_linear_data_offset(skb, sizeof(struct rss_header) +
  996. sizeof(struct cpl_pass_accept_req),
  997. gl->va + pktshift,
  998. gl->tot_len - pktshift);
  999. return skb;
  1000. }
  1001. static inline int recv_rx_pkt(struct c4iw_dev *dev, const struct pkt_gl *gl,
  1002. const __be64 *rsp)
  1003. {
  1004. unsigned int opcode = *(u8 *)rsp;
  1005. struct sk_buff *skb;
  1006. if (opcode != CPL_RX_PKT)
  1007. goto out;
  1008. skb = copy_gl_to_skb_pkt(gl , rsp, dev->rdev.lldi.sge_pktshift);
  1009. if (skb == NULL)
  1010. goto out;
  1011. if (c4iw_handlers[opcode] == NULL) {
  1012. pr_info("%s no handler opcode 0x%x...\n", __func__, opcode);
  1013. kfree_skb(skb);
  1014. goto out;
  1015. }
  1016. c4iw_handlers[opcode](dev, skb);
  1017. return 1;
  1018. out:
  1019. return 0;
  1020. }
  1021. static int c4iw_uld_rx_handler(void *handle, const __be64 *rsp,
  1022. const struct pkt_gl *gl)
  1023. {
  1024. struct uld_ctx *ctx = handle;
  1025. struct c4iw_dev *dev = ctx->dev;
  1026. struct sk_buff *skb;
  1027. u8 opcode;
  1028. if (gl == NULL) {
  1029. /* omit RSS and rsp_ctrl at end of descriptor */
  1030. unsigned int len = 64 - sizeof(struct rsp_ctrl) - 8;
  1031. skb = alloc_skb(256, GFP_ATOMIC);
  1032. if (!skb)
  1033. goto nomem;
  1034. __skb_put(skb, len);
  1035. skb_copy_to_linear_data(skb, &rsp[1], len);
  1036. } else if (gl == CXGB4_MSG_AN) {
  1037. const struct rsp_ctrl *rc = (void *)rsp;
  1038. u32 qid = be32_to_cpu(rc->pldbuflen_qid);
  1039. c4iw_ev_handler(dev, qid);
  1040. return 0;
  1041. } else if (unlikely(*(u8 *)rsp != *(u8 *)gl->va)) {
  1042. if (recv_rx_pkt(dev, gl, rsp))
  1043. return 0;
  1044. pr_info("%s: unexpected FL contents at %p, RSS %#llx, FL %#llx, len %u\n",
  1045. pci_name(ctx->lldi.pdev), gl->va,
  1046. be64_to_cpu(*rsp),
  1047. be64_to_cpu(*(__force __be64 *)gl->va),
  1048. gl->tot_len);
  1049. return 0;
  1050. } else {
  1051. skb = cxgb4_pktgl_to_skb(gl, 128, 128);
  1052. if (unlikely(!skb))
  1053. goto nomem;
  1054. }
  1055. opcode = *(u8 *)rsp;
  1056. if (c4iw_handlers[opcode]) {
  1057. c4iw_handlers[opcode](dev, skb);
  1058. } else {
  1059. pr_info("%s no handler opcode 0x%x...\n", __func__, opcode);
  1060. kfree_skb(skb);
  1061. }
  1062. return 0;
  1063. nomem:
  1064. return -1;
  1065. }
  1066. static int c4iw_uld_state_change(void *handle, enum cxgb4_state new_state)
  1067. {
  1068. struct uld_ctx *ctx = handle;
  1069. pr_debug("new_state %u\n", new_state);
  1070. switch (new_state) {
  1071. case CXGB4_STATE_UP:
  1072. pr_info("%s: Up\n", pci_name(ctx->lldi.pdev));
  1073. if (!ctx->dev) {
  1074. ctx->dev = c4iw_alloc(&ctx->lldi);
  1075. if (IS_ERR(ctx->dev)) {
  1076. pr_err("%s: initialization failed: %ld\n",
  1077. pci_name(ctx->lldi.pdev),
  1078. PTR_ERR(ctx->dev));
  1079. ctx->dev = NULL;
  1080. break;
  1081. }
  1082. INIT_WORK(&ctx->reg_work, c4iw_register_device);
  1083. queue_work(reg_workq, &ctx->reg_work);
  1084. }
  1085. break;
  1086. case CXGB4_STATE_DOWN:
  1087. pr_info("%s: Down\n", pci_name(ctx->lldi.pdev));
  1088. if (ctx->dev)
  1089. c4iw_remove(ctx);
  1090. break;
  1091. case CXGB4_STATE_FATAL_ERROR:
  1092. case CXGB4_STATE_START_RECOVERY:
  1093. pr_info("%s: Fatal Error\n", pci_name(ctx->lldi.pdev));
  1094. if (ctx->dev) {
  1095. struct ib_event event;
  1096. ctx->dev->rdev.flags |= T4_FATAL_ERROR;
  1097. memset(&event, 0, sizeof event);
  1098. event.event = IB_EVENT_DEVICE_FATAL;
  1099. event.device = &ctx->dev->ibdev;
  1100. ib_dispatch_event(&event);
  1101. c4iw_remove(ctx);
  1102. }
  1103. break;
  1104. case CXGB4_STATE_DETACH:
  1105. pr_info("%s: Detach\n", pci_name(ctx->lldi.pdev));
  1106. if (ctx->dev)
  1107. c4iw_remove(ctx);
  1108. break;
  1109. }
  1110. return 0;
  1111. }
  1112. static int disable_qp_db(int id, void *p, void *data)
  1113. {
  1114. struct c4iw_qp *qp = p;
  1115. t4_disable_wq_db(&qp->wq);
  1116. return 0;
  1117. }
  1118. static void stop_queues(struct uld_ctx *ctx)
  1119. {
  1120. unsigned long flags;
  1121. spin_lock_irqsave(&ctx->dev->lock, flags);
  1122. ctx->dev->rdev.stats.db_state_transitions++;
  1123. ctx->dev->db_state = STOPPED;
  1124. if (ctx->dev->rdev.flags & T4_STATUS_PAGE_DISABLED)
  1125. idr_for_each(&ctx->dev->qpidr, disable_qp_db, NULL);
  1126. else
  1127. ctx->dev->rdev.status_page->db_off = 1;
  1128. spin_unlock_irqrestore(&ctx->dev->lock, flags);
  1129. }
  1130. static int enable_qp_db(int id, void *p, void *data)
  1131. {
  1132. struct c4iw_qp *qp = p;
  1133. t4_enable_wq_db(&qp->wq);
  1134. return 0;
  1135. }
  1136. static void resume_rc_qp(struct c4iw_qp *qp)
  1137. {
  1138. spin_lock(&qp->lock);
  1139. t4_ring_sq_db(&qp->wq, qp->wq.sq.wq_pidx_inc, NULL);
  1140. qp->wq.sq.wq_pidx_inc = 0;
  1141. t4_ring_rq_db(&qp->wq, qp->wq.rq.wq_pidx_inc, NULL);
  1142. qp->wq.rq.wq_pidx_inc = 0;
  1143. spin_unlock(&qp->lock);
  1144. }
  1145. static void resume_a_chunk(struct uld_ctx *ctx)
  1146. {
  1147. int i;
  1148. struct c4iw_qp *qp;
  1149. for (i = 0; i < DB_FC_RESUME_SIZE; i++) {
  1150. qp = list_first_entry(&ctx->dev->db_fc_list, struct c4iw_qp,
  1151. db_fc_entry);
  1152. list_del_init(&qp->db_fc_entry);
  1153. resume_rc_qp(qp);
  1154. if (list_empty(&ctx->dev->db_fc_list))
  1155. break;
  1156. }
  1157. }
  1158. static void resume_queues(struct uld_ctx *ctx)
  1159. {
  1160. spin_lock_irq(&ctx->dev->lock);
  1161. if (ctx->dev->db_state != STOPPED)
  1162. goto out;
  1163. ctx->dev->db_state = FLOW_CONTROL;
  1164. while (1) {
  1165. if (list_empty(&ctx->dev->db_fc_list)) {
  1166. WARN_ON(ctx->dev->db_state != FLOW_CONTROL);
  1167. ctx->dev->db_state = NORMAL;
  1168. ctx->dev->rdev.stats.db_state_transitions++;
  1169. if (ctx->dev->rdev.flags & T4_STATUS_PAGE_DISABLED) {
  1170. idr_for_each(&ctx->dev->qpidr, enable_qp_db,
  1171. NULL);
  1172. } else {
  1173. ctx->dev->rdev.status_page->db_off = 0;
  1174. }
  1175. break;
  1176. } else {
  1177. if (cxgb4_dbfifo_count(ctx->dev->rdev.lldi.ports[0], 1)
  1178. < (ctx->dev->rdev.lldi.dbfifo_int_thresh <<
  1179. DB_FC_DRAIN_THRESH)) {
  1180. resume_a_chunk(ctx);
  1181. }
  1182. if (!list_empty(&ctx->dev->db_fc_list)) {
  1183. spin_unlock_irq(&ctx->dev->lock);
  1184. if (DB_FC_RESUME_DELAY) {
  1185. set_current_state(TASK_UNINTERRUPTIBLE);
  1186. schedule_timeout(DB_FC_RESUME_DELAY);
  1187. }
  1188. spin_lock_irq(&ctx->dev->lock);
  1189. if (ctx->dev->db_state != FLOW_CONTROL)
  1190. break;
  1191. }
  1192. }
  1193. }
  1194. out:
  1195. if (ctx->dev->db_state != NORMAL)
  1196. ctx->dev->rdev.stats.db_fc_interruptions++;
  1197. spin_unlock_irq(&ctx->dev->lock);
  1198. }
  1199. struct qp_list {
  1200. unsigned idx;
  1201. struct c4iw_qp **qps;
  1202. };
  1203. static int add_and_ref_qp(int id, void *p, void *data)
  1204. {
  1205. struct qp_list *qp_listp = data;
  1206. struct c4iw_qp *qp = p;
  1207. c4iw_qp_add_ref(&qp->ibqp);
  1208. qp_listp->qps[qp_listp->idx++] = qp;
  1209. return 0;
  1210. }
  1211. static int count_qps(int id, void *p, void *data)
  1212. {
  1213. unsigned *countp = data;
  1214. (*countp)++;
  1215. return 0;
  1216. }
  1217. static void deref_qps(struct qp_list *qp_list)
  1218. {
  1219. int idx;
  1220. for (idx = 0; idx < qp_list->idx; idx++)
  1221. c4iw_qp_rem_ref(&qp_list->qps[idx]->ibqp);
  1222. }
  1223. static void recover_lost_dbs(struct uld_ctx *ctx, struct qp_list *qp_list)
  1224. {
  1225. int idx;
  1226. int ret;
  1227. for (idx = 0; idx < qp_list->idx; idx++) {
  1228. struct c4iw_qp *qp = qp_list->qps[idx];
  1229. spin_lock_irq(&qp->rhp->lock);
  1230. spin_lock(&qp->lock);
  1231. ret = cxgb4_sync_txq_pidx(qp->rhp->rdev.lldi.ports[0],
  1232. qp->wq.sq.qid,
  1233. t4_sq_host_wq_pidx(&qp->wq),
  1234. t4_sq_wq_size(&qp->wq));
  1235. if (ret) {
  1236. pr_err("%s: Fatal error - DB overflow recovery failed - error syncing SQ qid %u\n",
  1237. pci_name(ctx->lldi.pdev), qp->wq.sq.qid);
  1238. spin_unlock(&qp->lock);
  1239. spin_unlock_irq(&qp->rhp->lock);
  1240. return;
  1241. }
  1242. qp->wq.sq.wq_pidx_inc = 0;
  1243. ret = cxgb4_sync_txq_pidx(qp->rhp->rdev.lldi.ports[0],
  1244. qp->wq.rq.qid,
  1245. t4_rq_host_wq_pidx(&qp->wq),
  1246. t4_rq_wq_size(&qp->wq));
  1247. if (ret) {
  1248. pr_err("%s: Fatal error - DB overflow recovery failed - error syncing RQ qid %u\n",
  1249. pci_name(ctx->lldi.pdev), qp->wq.rq.qid);
  1250. spin_unlock(&qp->lock);
  1251. spin_unlock_irq(&qp->rhp->lock);
  1252. return;
  1253. }
  1254. qp->wq.rq.wq_pidx_inc = 0;
  1255. spin_unlock(&qp->lock);
  1256. spin_unlock_irq(&qp->rhp->lock);
  1257. /* Wait for the dbfifo to drain */
  1258. while (cxgb4_dbfifo_count(qp->rhp->rdev.lldi.ports[0], 1) > 0) {
  1259. set_current_state(TASK_UNINTERRUPTIBLE);
  1260. schedule_timeout(usecs_to_jiffies(10));
  1261. }
  1262. }
  1263. }
  1264. static void recover_queues(struct uld_ctx *ctx)
  1265. {
  1266. int count = 0;
  1267. struct qp_list qp_list;
  1268. int ret;
  1269. /* slow everybody down */
  1270. set_current_state(TASK_UNINTERRUPTIBLE);
  1271. schedule_timeout(usecs_to_jiffies(1000));
  1272. /* flush the SGE contexts */
  1273. ret = cxgb4_flush_eq_cache(ctx->dev->rdev.lldi.ports[0]);
  1274. if (ret) {
  1275. pr_err("%s: Fatal error - DB overflow recovery failed\n",
  1276. pci_name(ctx->lldi.pdev));
  1277. return;
  1278. }
  1279. /* Count active queues so we can build a list of queues to recover */
  1280. spin_lock_irq(&ctx->dev->lock);
  1281. WARN_ON(ctx->dev->db_state != STOPPED);
  1282. ctx->dev->db_state = RECOVERY;
  1283. idr_for_each(&ctx->dev->qpidr, count_qps, &count);
  1284. qp_list.qps = kcalloc(count, sizeof(*qp_list.qps), GFP_ATOMIC);
  1285. if (!qp_list.qps) {
  1286. spin_unlock_irq(&ctx->dev->lock);
  1287. return;
  1288. }
  1289. qp_list.idx = 0;
  1290. /* add and ref each qp so it doesn't get freed */
  1291. idr_for_each(&ctx->dev->qpidr, add_and_ref_qp, &qp_list);
  1292. spin_unlock_irq(&ctx->dev->lock);
  1293. /* now traverse the list in a safe context to recover the db state*/
  1294. recover_lost_dbs(ctx, &qp_list);
  1295. /* we're almost done! deref the qps and clean up */
  1296. deref_qps(&qp_list);
  1297. kfree(qp_list.qps);
  1298. spin_lock_irq(&ctx->dev->lock);
  1299. WARN_ON(ctx->dev->db_state != RECOVERY);
  1300. ctx->dev->db_state = STOPPED;
  1301. spin_unlock_irq(&ctx->dev->lock);
  1302. }
  1303. static int c4iw_uld_control(void *handle, enum cxgb4_control control, ...)
  1304. {
  1305. struct uld_ctx *ctx = handle;
  1306. switch (control) {
  1307. case CXGB4_CONTROL_DB_FULL:
  1308. stop_queues(ctx);
  1309. ctx->dev->rdev.stats.db_full++;
  1310. break;
  1311. case CXGB4_CONTROL_DB_EMPTY:
  1312. resume_queues(ctx);
  1313. mutex_lock(&ctx->dev->rdev.stats.lock);
  1314. ctx->dev->rdev.stats.db_empty++;
  1315. mutex_unlock(&ctx->dev->rdev.stats.lock);
  1316. break;
  1317. case CXGB4_CONTROL_DB_DROP:
  1318. recover_queues(ctx);
  1319. mutex_lock(&ctx->dev->rdev.stats.lock);
  1320. ctx->dev->rdev.stats.db_drop++;
  1321. mutex_unlock(&ctx->dev->rdev.stats.lock);
  1322. break;
  1323. default:
  1324. pr_warn("%s: unknown control cmd %u\n",
  1325. pci_name(ctx->lldi.pdev), control);
  1326. break;
  1327. }
  1328. return 0;
  1329. }
  1330. static struct cxgb4_uld_info c4iw_uld_info = {
  1331. .name = DRV_NAME,
  1332. .nrxq = MAX_ULD_QSETS,
  1333. .ntxq = MAX_ULD_QSETS,
  1334. .rxq_size = 511,
  1335. .ciq = true,
  1336. .lro = false,
  1337. .add = c4iw_uld_add,
  1338. .rx_handler = c4iw_uld_rx_handler,
  1339. .state_change = c4iw_uld_state_change,
  1340. .control = c4iw_uld_control,
  1341. };
  1342. void _c4iw_free_wr_wait(struct kref *kref)
  1343. {
  1344. struct c4iw_wr_wait *wr_waitp;
  1345. wr_waitp = container_of(kref, struct c4iw_wr_wait, kref);
  1346. pr_debug("Free wr_wait %p\n", wr_waitp);
  1347. kfree(wr_waitp);
  1348. }
  1349. struct c4iw_wr_wait *c4iw_alloc_wr_wait(gfp_t gfp)
  1350. {
  1351. struct c4iw_wr_wait *wr_waitp;
  1352. wr_waitp = kzalloc(sizeof(*wr_waitp), gfp);
  1353. if (wr_waitp) {
  1354. kref_init(&wr_waitp->kref);
  1355. pr_debug("wr_wait %p\n", wr_waitp);
  1356. }
  1357. return wr_waitp;
  1358. }
  1359. static int __init c4iw_init_module(void)
  1360. {
  1361. int err;
  1362. err = c4iw_cm_init();
  1363. if (err)
  1364. return err;
  1365. c4iw_debugfs_root = debugfs_create_dir(DRV_NAME, NULL);
  1366. if (!c4iw_debugfs_root)
  1367. pr_warn("could not create debugfs entry, continuing\n");
  1368. reg_workq = create_singlethread_workqueue("Register_iWARP_device");
  1369. if (!reg_workq) {
  1370. pr_err("Failed creating workqueue to register iwarp device\n");
  1371. return -ENOMEM;
  1372. }
  1373. cxgb4_register_uld(CXGB4_ULD_RDMA, &c4iw_uld_info);
  1374. return 0;
  1375. }
  1376. static void __exit c4iw_exit_module(void)
  1377. {
  1378. struct uld_ctx *ctx, *tmp;
  1379. mutex_lock(&dev_mutex);
  1380. list_for_each_entry_safe(ctx, tmp, &uld_ctx_list, entry) {
  1381. if (ctx->dev)
  1382. c4iw_remove(ctx);
  1383. kfree(ctx);
  1384. }
  1385. mutex_unlock(&dev_mutex);
  1386. flush_workqueue(reg_workq);
  1387. destroy_workqueue(reg_workq);
  1388. cxgb4_unregister_uld(CXGB4_ULD_RDMA);
  1389. c4iw_cm_term();
  1390. debugfs_remove_recursive(c4iw_debugfs_root);
  1391. }
  1392. module_init(c4iw_init_module);
  1393. module_exit(c4iw_exit_module);