tcs3472.c 15 KB

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  1. /*
  2. * tcs3472.c - Support for TAOS TCS3472 color light-to-digital converter
  3. *
  4. * Copyright (c) 2013 Peter Meerwald <pmeerw@pmeerw.net>
  5. *
  6. * This file is subject to the terms and conditions of version 2 of
  7. * the GNU General Public License. See the file COPYING in the main
  8. * directory of this archive for more details.
  9. *
  10. * Color light sensor with 16-bit channels for red, green, blue, clear);
  11. * 7-bit I2C slave address 0x39 (TCS34721, TCS34723) or 0x29 (TCS34725,
  12. * TCS34727)
  13. *
  14. * Datasheet: http://ams.com/eng/content/download/319364/1117183/file/TCS3472_Datasheet_EN_v2.pdf
  15. *
  16. * TODO: wait time
  17. */
  18. #include <linux/module.h>
  19. #include <linux/i2c.h>
  20. #include <linux/delay.h>
  21. #include <linux/pm.h>
  22. #include <linux/iio/iio.h>
  23. #include <linux/iio/sysfs.h>
  24. #include <linux/iio/events.h>
  25. #include <linux/iio/trigger_consumer.h>
  26. #include <linux/iio/buffer.h>
  27. #include <linux/iio/triggered_buffer.h>
  28. #define TCS3472_DRV_NAME "tcs3472"
  29. #define TCS3472_COMMAND BIT(7)
  30. #define TCS3472_AUTO_INCR BIT(5)
  31. #define TCS3472_SPECIAL_FUNC (BIT(5) | BIT(6))
  32. #define TCS3472_INTR_CLEAR (TCS3472_COMMAND | TCS3472_SPECIAL_FUNC | 0x06)
  33. #define TCS3472_ENABLE (TCS3472_COMMAND | 0x00)
  34. #define TCS3472_ATIME (TCS3472_COMMAND | 0x01)
  35. #define TCS3472_WTIME (TCS3472_COMMAND | 0x03)
  36. #define TCS3472_AILT (TCS3472_COMMAND | TCS3472_AUTO_INCR | 0x04)
  37. #define TCS3472_AIHT (TCS3472_COMMAND | TCS3472_AUTO_INCR | 0x06)
  38. #define TCS3472_PERS (TCS3472_COMMAND | 0x0c)
  39. #define TCS3472_CONFIG (TCS3472_COMMAND | 0x0d)
  40. #define TCS3472_CONTROL (TCS3472_COMMAND | 0x0f)
  41. #define TCS3472_ID (TCS3472_COMMAND | 0x12)
  42. #define TCS3472_STATUS (TCS3472_COMMAND | 0x13)
  43. #define TCS3472_CDATA (TCS3472_COMMAND | TCS3472_AUTO_INCR | 0x14)
  44. #define TCS3472_RDATA (TCS3472_COMMAND | TCS3472_AUTO_INCR | 0x16)
  45. #define TCS3472_GDATA (TCS3472_COMMAND | TCS3472_AUTO_INCR | 0x18)
  46. #define TCS3472_BDATA (TCS3472_COMMAND | TCS3472_AUTO_INCR | 0x1a)
  47. #define TCS3472_STATUS_AINT BIT(4)
  48. #define TCS3472_STATUS_AVALID BIT(0)
  49. #define TCS3472_ENABLE_AIEN BIT(4)
  50. #define TCS3472_ENABLE_AEN BIT(1)
  51. #define TCS3472_ENABLE_PON BIT(0)
  52. #define TCS3472_CONTROL_AGAIN_MASK (BIT(0) | BIT(1))
  53. struct tcs3472_data {
  54. struct i2c_client *client;
  55. struct mutex lock;
  56. u16 low_thresh;
  57. u16 high_thresh;
  58. u8 enable;
  59. u8 control;
  60. u8 atime;
  61. u8 apers;
  62. u16 buffer[8]; /* 4 16-bit channels + 64-bit timestamp */
  63. };
  64. static const struct iio_event_spec tcs3472_events[] = {
  65. {
  66. .type = IIO_EV_TYPE_THRESH,
  67. .dir = IIO_EV_DIR_RISING,
  68. .mask_separate = BIT(IIO_EV_INFO_VALUE),
  69. }, {
  70. .type = IIO_EV_TYPE_THRESH,
  71. .dir = IIO_EV_DIR_FALLING,
  72. .mask_separate = BIT(IIO_EV_INFO_VALUE),
  73. }, {
  74. .type = IIO_EV_TYPE_THRESH,
  75. .dir = IIO_EV_DIR_EITHER,
  76. .mask_separate = BIT(IIO_EV_INFO_ENABLE) |
  77. BIT(IIO_EV_INFO_PERIOD),
  78. },
  79. };
  80. #define TCS3472_CHANNEL(_color, _si, _addr) { \
  81. .type = IIO_INTENSITY, \
  82. .modified = 1, \
  83. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  84. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_CALIBSCALE) | \
  85. BIT(IIO_CHAN_INFO_INT_TIME), \
  86. .channel2 = IIO_MOD_LIGHT_##_color, \
  87. .address = _addr, \
  88. .scan_index = _si, \
  89. .scan_type = { \
  90. .sign = 'u', \
  91. .realbits = 16, \
  92. .storagebits = 16, \
  93. .endianness = IIO_CPU, \
  94. }, \
  95. .event_spec = _si ? NULL : tcs3472_events, \
  96. .num_event_specs = _si ? 0 : ARRAY_SIZE(tcs3472_events), \
  97. }
  98. static const int tcs3472_agains[] = { 1, 4, 16, 60 };
  99. static const struct iio_chan_spec tcs3472_channels[] = {
  100. TCS3472_CHANNEL(CLEAR, 0, TCS3472_CDATA),
  101. TCS3472_CHANNEL(RED, 1, TCS3472_RDATA),
  102. TCS3472_CHANNEL(GREEN, 2, TCS3472_GDATA),
  103. TCS3472_CHANNEL(BLUE, 3, TCS3472_BDATA),
  104. IIO_CHAN_SOFT_TIMESTAMP(4),
  105. };
  106. static int tcs3472_req_data(struct tcs3472_data *data)
  107. {
  108. int tries = 50;
  109. int ret;
  110. while (tries--) {
  111. ret = i2c_smbus_read_byte_data(data->client, TCS3472_STATUS);
  112. if (ret < 0)
  113. return ret;
  114. if (ret & TCS3472_STATUS_AVALID)
  115. break;
  116. msleep(20);
  117. }
  118. if (tries < 0) {
  119. dev_err(&data->client->dev, "data not ready\n");
  120. return -EIO;
  121. }
  122. return 0;
  123. }
  124. static int tcs3472_read_raw(struct iio_dev *indio_dev,
  125. struct iio_chan_spec const *chan,
  126. int *val, int *val2, long mask)
  127. {
  128. struct tcs3472_data *data = iio_priv(indio_dev);
  129. int ret;
  130. switch (mask) {
  131. case IIO_CHAN_INFO_RAW:
  132. ret = iio_device_claim_direct_mode(indio_dev);
  133. if (ret)
  134. return ret;
  135. ret = tcs3472_req_data(data);
  136. if (ret < 0) {
  137. iio_device_release_direct_mode(indio_dev);
  138. return ret;
  139. }
  140. ret = i2c_smbus_read_word_data(data->client, chan->address);
  141. iio_device_release_direct_mode(indio_dev);
  142. if (ret < 0)
  143. return ret;
  144. *val = ret;
  145. return IIO_VAL_INT;
  146. case IIO_CHAN_INFO_CALIBSCALE:
  147. *val = tcs3472_agains[data->control &
  148. TCS3472_CONTROL_AGAIN_MASK];
  149. return IIO_VAL_INT;
  150. case IIO_CHAN_INFO_INT_TIME:
  151. *val = 0;
  152. *val2 = (256 - data->atime) * 2400;
  153. return IIO_VAL_INT_PLUS_MICRO;
  154. }
  155. return -EINVAL;
  156. }
  157. static int tcs3472_write_raw(struct iio_dev *indio_dev,
  158. struct iio_chan_spec const *chan,
  159. int val, int val2, long mask)
  160. {
  161. struct tcs3472_data *data = iio_priv(indio_dev);
  162. int i;
  163. switch (mask) {
  164. case IIO_CHAN_INFO_CALIBSCALE:
  165. if (val2 != 0)
  166. return -EINVAL;
  167. for (i = 0; i < ARRAY_SIZE(tcs3472_agains); i++) {
  168. if (val == tcs3472_agains[i]) {
  169. data->control &= ~TCS3472_CONTROL_AGAIN_MASK;
  170. data->control |= i;
  171. return i2c_smbus_write_byte_data(
  172. data->client, TCS3472_CONTROL,
  173. data->control);
  174. }
  175. }
  176. return -EINVAL;
  177. case IIO_CHAN_INFO_INT_TIME:
  178. if (val != 0)
  179. return -EINVAL;
  180. for (i = 0; i < 256; i++) {
  181. if (val2 == (256 - i) * 2400) {
  182. data->atime = i;
  183. return i2c_smbus_write_byte_data(
  184. data->client, TCS3472_ATIME,
  185. data->atime);
  186. }
  187. }
  188. return -EINVAL;
  189. }
  190. return -EINVAL;
  191. }
  192. /*
  193. * Translation from APERS field value to the number of consecutive out-of-range
  194. * clear channel values before an interrupt is generated
  195. */
  196. static const int tcs3472_intr_pers[] = {
  197. 0, 1, 2, 3, 5, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60
  198. };
  199. static int tcs3472_read_event(struct iio_dev *indio_dev,
  200. const struct iio_chan_spec *chan, enum iio_event_type type,
  201. enum iio_event_direction dir, enum iio_event_info info, int *val,
  202. int *val2)
  203. {
  204. struct tcs3472_data *data = iio_priv(indio_dev);
  205. int ret;
  206. unsigned int period;
  207. mutex_lock(&data->lock);
  208. switch (info) {
  209. case IIO_EV_INFO_VALUE:
  210. *val = (dir == IIO_EV_DIR_RISING) ?
  211. data->high_thresh : data->low_thresh;
  212. ret = IIO_VAL_INT;
  213. break;
  214. case IIO_EV_INFO_PERIOD:
  215. period = (256 - data->atime) * 2400 *
  216. tcs3472_intr_pers[data->apers];
  217. *val = period / USEC_PER_SEC;
  218. *val2 = period % USEC_PER_SEC;
  219. ret = IIO_VAL_INT_PLUS_MICRO;
  220. break;
  221. default:
  222. ret = -EINVAL;
  223. break;
  224. }
  225. mutex_unlock(&data->lock);
  226. return ret;
  227. }
  228. static int tcs3472_write_event(struct iio_dev *indio_dev,
  229. const struct iio_chan_spec *chan, enum iio_event_type type,
  230. enum iio_event_direction dir, enum iio_event_info info, int val,
  231. int val2)
  232. {
  233. struct tcs3472_data *data = iio_priv(indio_dev);
  234. int ret;
  235. u8 command;
  236. int period;
  237. int i;
  238. mutex_lock(&data->lock);
  239. switch (info) {
  240. case IIO_EV_INFO_VALUE:
  241. switch (dir) {
  242. case IIO_EV_DIR_RISING:
  243. command = TCS3472_AIHT;
  244. break;
  245. case IIO_EV_DIR_FALLING:
  246. command = TCS3472_AILT;
  247. break;
  248. default:
  249. ret = -EINVAL;
  250. goto error;
  251. }
  252. ret = i2c_smbus_write_word_data(data->client, command, val);
  253. if (ret)
  254. goto error;
  255. if (dir == IIO_EV_DIR_RISING)
  256. data->high_thresh = val;
  257. else
  258. data->low_thresh = val;
  259. break;
  260. case IIO_EV_INFO_PERIOD:
  261. period = val * USEC_PER_SEC + val2;
  262. for (i = 1; i < ARRAY_SIZE(tcs3472_intr_pers) - 1; i++) {
  263. if (period <= (256 - data->atime) * 2400 *
  264. tcs3472_intr_pers[i])
  265. break;
  266. }
  267. ret = i2c_smbus_write_byte_data(data->client, TCS3472_PERS, i);
  268. if (ret)
  269. goto error;
  270. data->apers = i;
  271. break;
  272. default:
  273. ret = -EINVAL;
  274. break;
  275. }
  276. error:
  277. mutex_unlock(&data->lock);
  278. return ret;
  279. }
  280. static int tcs3472_read_event_config(struct iio_dev *indio_dev,
  281. const struct iio_chan_spec *chan, enum iio_event_type type,
  282. enum iio_event_direction dir)
  283. {
  284. struct tcs3472_data *data = iio_priv(indio_dev);
  285. int ret;
  286. mutex_lock(&data->lock);
  287. ret = !!(data->enable & TCS3472_ENABLE_AIEN);
  288. mutex_unlock(&data->lock);
  289. return ret;
  290. }
  291. static int tcs3472_write_event_config(struct iio_dev *indio_dev,
  292. const struct iio_chan_spec *chan, enum iio_event_type type,
  293. enum iio_event_direction dir, int state)
  294. {
  295. struct tcs3472_data *data = iio_priv(indio_dev);
  296. int ret = 0;
  297. u8 enable_old;
  298. mutex_lock(&data->lock);
  299. enable_old = data->enable;
  300. if (state)
  301. data->enable |= TCS3472_ENABLE_AIEN;
  302. else
  303. data->enable &= ~TCS3472_ENABLE_AIEN;
  304. if (enable_old != data->enable) {
  305. ret = i2c_smbus_write_byte_data(data->client, TCS3472_ENABLE,
  306. data->enable);
  307. if (ret)
  308. data->enable = enable_old;
  309. }
  310. mutex_unlock(&data->lock);
  311. return ret;
  312. }
  313. static irqreturn_t tcs3472_event_handler(int irq, void *priv)
  314. {
  315. struct iio_dev *indio_dev = priv;
  316. struct tcs3472_data *data = iio_priv(indio_dev);
  317. int ret;
  318. ret = i2c_smbus_read_byte_data(data->client, TCS3472_STATUS);
  319. if (ret >= 0 && (ret & TCS3472_STATUS_AINT)) {
  320. iio_push_event(indio_dev, IIO_UNMOD_EVENT_CODE(IIO_INTENSITY, 0,
  321. IIO_EV_TYPE_THRESH,
  322. IIO_EV_DIR_EITHER),
  323. iio_get_time_ns(indio_dev));
  324. i2c_smbus_read_byte_data(data->client, TCS3472_INTR_CLEAR);
  325. }
  326. return IRQ_HANDLED;
  327. }
  328. static irqreturn_t tcs3472_trigger_handler(int irq, void *p)
  329. {
  330. struct iio_poll_func *pf = p;
  331. struct iio_dev *indio_dev = pf->indio_dev;
  332. struct tcs3472_data *data = iio_priv(indio_dev);
  333. int i, j = 0;
  334. int ret = tcs3472_req_data(data);
  335. if (ret < 0)
  336. goto done;
  337. for_each_set_bit(i, indio_dev->active_scan_mask,
  338. indio_dev->masklength) {
  339. ret = i2c_smbus_read_word_data(data->client,
  340. TCS3472_CDATA + 2*i);
  341. if (ret < 0)
  342. goto done;
  343. data->buffer[j++] = ret;
  344. }
  345. iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
  346. iio_get_time_ns(indio_dev));
  347. done:
  348. iio_trigger_notify_done(indio_dev->trig);
  349. return IRQ_HANDLED;
  350. }
  351. static ssize_t tcs3472_show_int_time_available(struct device *dev,
  352. struct device_attribute *attr,
  353. char *buf)
  354. {
  355. size_t len = 0;
  356. int i;
  357. for (i = 1; i <= 256; i++)
  358. len += scnprintf(buf + len, PAGE_SIZE - len, "0.%06d ",
  359. 2400 * i);
  360. /* replace trailing space by newline */
  361. buf[len - 1] = '\n';
  362. return len;
  363. }
  364. static IIO_CONST_ATTR(calibscale_available, "1 4 16 60");
  365. static IIO_DEV_ATTR_INT_TIME_AVAIL(tcs3472_show_int_time_available);
  366. static struct attribute *tcs3472_attributes[] = {
  367. &iio_const_attr_calibscale_available.dev_attr.attr,
  368. &iio_dev_attr_integration_time_available.dev_attr.attr,
  369. NULL
  370. };
  371. static const struct attribute_group tcs3472_attribute_group = {
  372. .attrs = tcs3472_attributes,
  373. };
  374. static const struct iio_info tcs3472_info = {
  375. .read_raw = tcs3472_read_raw,
  376. .write_raw = tcs3472_write_raw,
  377. .read_event_value = tcs3472_read_event,
  378. .write_event_value = tcs3472_write_event,
  379. .read_event_config = tcs3472_read_event_config,
  380. .write_event_config = tcs3472_write_event_config,
  381. .attrs = &tcs3472_attribute_group,
  382. };
  383. static int tcs3472_probe(struct i2c_client *client,
  384. const struct i2c_device_id *id)
  385. {
  386. struct tcs3472_data *data;
  387. struct iio_dev *indio_dev;
  388. int ret;
  389. indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
  390. if (indio_dev == NULL)
  391. return -ENOMEM;
  392. data = iio_priv(indio_dev);
  393. i2c_set_clientdata(client, indio_dev);
  394. data->client = client;
  395. mutex_init(&data->lock);
  396. indio_dev->dev.parent = &client->dev;
  397. indio_dev->info = &tcs3472_info;
  398. indio_dev->name = TCS3472_DRV_NAME;
  399. indio_dev->channels = tcs3472_channels;
  400. indio_dev->num_channels = ARRAY_SIZE(tcs3472_channels);
  401. indio_dev->modes = INDIO_DIRECT_MODE;
  402. ret = i2c_smbus_read_byte_data(data->client, TCS3472_ID);
  403. if (ret < 0)
  404. return ret;
  405. if (ret == 0x44)
  406. dev_info(&client->dev, "TCS34721/34725 found\n");
  407. else if (ret == 0x4d)
  408. dev_info(&client->dev, "TCS34723/34727 found\n");
  409. else
  410. return -ENODEV;
  411. ret = i2c_smbus_read_byte_data(data->client, TCS3472_CONTROL);
  412. if (ret < 0)
  413. return ret;
  414. data->control = ret;
  415. ret = i2c_smbus_read_byte_data(data->client, TCS3472_ATIME);
  416. if (ret < 0)
  417. return ret;
  418. data->atime = ret;
  419. ret = i2c_smbus_read_word_data(data->client, TCS3472_AILT);
  420. if (ret < 0)
  421. return ret;
  422. data->low_thresh = ret;
  423. ret = i2c_smbus_read_word_data(data->client, TCS3472_AIHT);
  424. if (ret < 0)
  425. return ret;
  426. data->high_thresh = ret;
  427. data->apers = 1;
  428. ret = i2c_smbus_write_byte_data(data->client, TCS3472_PERS,
  429. data->apers);
  430. if (ret < 0)
  431. return ret;
  432. ret = i2c_smbus_read_byte_data(data->client, TCS3472_ENABLE);
  433. if (ret < 0)
  434. return ret;
  435. /* enable device */
  436. data->enable = ret | TCS3472_ENABLE_PON | TCS3472_ENABLE_AEN;
  437. data->enable &= ~TCS3472_ENABLE_AIEN;
  438. ret = i2c_smbus_write_byte_data(data->client, TCS3472_ENABLE,
  439. data->enable);
  440. if (ret < 0)
  441. return ret;
  442. ret = iio_triggered_buffer_setup(indio_dev, NULL,
  443. tcs3472_trigger_handler, NULL);
  444. if (ret < 0)
  445. return ret;
  446. if (client->irq) {
  447. ret = request_threaded_irq(client->irq, NULL,
  448. tcs3472_event_handler,
  449. IRQF_TRIGGER_FALLING | IRQF_SHARED |
  450. IRQF_ONESHOT,
  451. client->name, indio_dev);
  452. if (ret)
  453. goto buffer_cleanup;
  454. }
  455. ret = iio_device_register(indio_dev);
  456. if (ret < 0)
  457. goto free_irq;
  458. return 0;
  459. free_irq:
  460. free_irq(client->irq, indio_dev);
  461. buffer_cleanup:
  462. iio_triggered_buffer_cleanup(indio_dev);
  463. return ret;
  464. }
  465. static int tcs3472_powerdown(struct tcs3472_data *data)
  466. {
  467. int ret;
  468. u8 enable_mask = TCS3472_ENABLE_AEN | TCS3472_ENABLE_PON;
  469. mutex_lock(&data->lock);
  470. ret = i2c_smbus_write_byte_data(data->client, TCS3472_ENABLE,
  471. data->enable & ~enable_mask);
  472. if (!ret)
  473. data->enable &= ~enable_mask;
  474. mutex_unlock(&data->lock);
  475. return ret;
  476. }
  477. static int tcs3472_remove(struct i2c_client *client)
  478. {
  479. struct iio_dev *indio_dev = i2c_get_clientdata(client);
  480. iio_device_unregister(indio_dev);
  481. free_irq(client->irq, indio_dev);
  482. iio_triggered_buffer_cleanup(indio_dev);
  483. tcs3472_powerdown(iio_priv(indio_dev));
  484. return 0;
  485. }
  486. #ifdef CONFIG_PM_SLEEP
  487. static int tcs3472_suspend(struct device *dev)
  488. {
  489. struct tcs3472_data *data = iio_priv(i2c_get_clientdata(
  490. to_i2c_client(dev)));
  491. return tcs3472_powerdown(data);
  492. }
  493. static int tcs3472_resume(struct device *dev)
  494. {
  495. struct tcs3472_data *data = iio_priv(i2c_get_clientdata(
  496. to_i2c_client(dev)));
  497. int ret;
  498. u8 enable_mask = TCS3472_ENABLE_AEN | TCS3472_ENABLE_PON;
  499. mutex_lock(&data->lock);
  500. ret = i2c_smbus_write_byte_data(data->client, TCS3472_ENABLE,
  501. data->enable | enable_mask);
  502. if (!ret)
  503. data->enable |= enable_mask;
  504. mutex_unlock(&data->lock);
  505. return ret;
  506. }
  507. #endif
  508. static SIMPLE_DEV_PM_OPS(tcs3472_pm_ops, tcs3472_suspend, tcs3472_resume);
  509. static const struct i2c_device_id tcs3472_id[] = {
  510. { "tcs3472", 0 },
  511. { }
  512. };
  513. MODULE_DEVICE_TABLE(i2c, tcs3472_id);
  514. static struct i2c_driver tcs3472_driver = {
  515. .driver = {
  516. .name = TCS3472_DRV_NAME,
  517. .pm = &tcs3472_pm_ops,
  518. },
  519. .probe = tcs3472_probe,
  520. .remove = tcs3472_remove,
  521. .id_table = tcs3472_id,
  522. };
  523. module_i2c_driver(tcs3472_driver);
  524. MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>");
  525. MODULE_DESCRIPTION("TCS3472 color light sensors driver");
  526. MODULE_LICENSE("GPL");