opt3001.c 20 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864
  1. /**
  2. * opt3001.c - Texas Instruments OPT3001 Light Sensor
  3. *
  4. * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
  5. *
  6. * Author: Andreas Dannenberg <dannenberg@ti.com>
  7. * Based on previous work from: Felipe Balbi <balbi@ti.com>
  8. *
  9. * This program is free software: you can redistribute it and/or modify it
  10. * under the terms of the GNU General Public License version 2 of the License
  11. * as published by the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful, but WITHOUT
  14. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  16. * more details.
  17. */
  18. #include <linux/bitops.h>
  19. #include <linux/delay.h>
  20. #include <linux/device.h>
  21. #include <linux/i2c.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/irq.h>
  24. #include <linux/kernel.h>
  25. #include <linux/module.h>
  26. #include <linux/mutex.h>
  27. #include <linux/slab.h>
  28. #include <linux/types.h>
  29. #include <linux/iio/events.h>
  30. #include <linux/iio/iio.h>
  31. #include <linux/iio/sysfs.h>
  32. #define OPT3001_RESULT 0x00
  33. #define OPT3001_CONFIGURATION 0x01
  34. #define OPT3001_LOW_LIMIT 0x02
  35. #define OPT3001_HIGH_LIMIT 0x03
  36. #define OPT3001_MANUFACTURER_ID 0x7e
  37. #define OPT3001_DEVICE_ID 0x7f
  38. #define OPT3001_CONFIGURATION_RN_MASK (0xf << 12)
  39. #define OPT3001_CONFIGURATION_RN_AUTO (0xc << 12)
  40. #define OPT3001_CONFIGURATION_CT BIT(11)
  41. #define OPT3001_CONFIGURATION_M_MASK (3 << 9)
  42. #define OPT3001_CONFIGURATION_M_SHUTDOWN (0 << 9)
  43. #define OPT3001_CONFIGURATION_M_SINGLE (1 << 9)
  44. #define OPT3001_CONFIGURATION_M_CONTINUOUS (2 << 9) /* also 3 << 9 */
  45. #define OPT3001_CONFIGURATION_OVF BIT(8)
  46. #define OPT3001_CONFIGURATION_CRF BIT(7)
  47. #define OPT3001_CONFIGURATION_FH BIT(6)
  48. #define OPT3001_CONFIGURATION_FL BIT(5)
  49. #define OPT3001_CONFIGURATION_L BIT(4)
  50. #define OPT3001_CONFIGURATION_POL BIT(3)
  51. #define OPT3001_CONFIGURATION_ME BIT(2)
  52. #define OPT3001_CONFIGURATION_FC_MASK (3 << 0)
  53. /* The end-of-conversion enable is located in the low-limit register */
  54. #define OPT3001_LOW_LIMIT_EOC_ENABLE 0xc000
  55. #define OPT3001_REG_EXPONENT(n) ((n) >> 12)
  56. #define OPT3001_REG_MANTISSA(n) ((n) & 0xfff)
  57. #define OPT3001_INT_TIME_LONG 800000
  58. #define OPT3001_INT_TIME_SHORT 100000
  59. /*
  60. * Time to wait for conversion result to be ready. The device datasheet
  61. * sect. 6.5 states results are ready after total integration time plus 3ms.
  62. * This results in worst-case max values of 113ms or 883ms, respectively.
  63. * Add some slack to be on the safe side.
  64. */
  65. #define OPT3001_RESULT_READY_SHORT 150
  66. #define OPT3001_RESULT_READY_LONG 1000
  67. struct opt3001 {
  68. struct i2c_client *client;
  69. struct device *dev;
  70. struct mutex lock;
  71. bool ok_to_ignore_lock;
  72. bool result_ready;
  73. wait_queue_head_t result_ready_queue;
  74. u16 result;
  75. u32 int_time;
  76. u32 mode;
  77. u16 high_thresh_mantissa;
  78. u16 low_thresh_mantissa;
  79. u8 high_thresh_exp;
  80. u8 low_thresh_exp;
  81. bool use_irq;
  82. };
  83. struct opt3001_scale {
  84. int val;
  85. int val2;
  86. };
  87. static const struct opt3001_scale opt3001_scales[] = {
  88. {
  89. .val = 40,
  90. .val2 = 950000,
  91. },
  92. {
  93. .val = 81,
  94. .val2 = 900000,
  95. },
  96. {
  97. .val = 163,
  98. .val2 = 800000,
  99. },
  100. {
  101. .val = 327,
  102. .val2 = 600000,
  103. },
  104. {
  105. .val = 655,
  106. .val2 = 200000,
  107. },
  108. {
  109. .val = 1310,
  110. .val2 = 400000,
  111. },
  112. {
  113. .val = 2620,
  114. .val2 = 800000,
  115. },
  116. {
  117. .val = 5241,
  118. .val2 = 600000,
  119. },
  120. {
  121. .val = 10483,
  122. .val2 = 200000,
  123. },
  124. {
  125. .val = 20966,
  126. .val2 = 400000,
  127. },
  128. {
  129. .val = 83865,
  130. .val2 = 600000,
  131. },
  132. };
  133. static int opt3001_find_scale(const struct opt3001 *opt, int val,
  134. int val2, u8 *exponent)
  135. {
  136. int i;
  137. for (i = 0; i < ARRAY_SIZE(opt3001_scales); i++) {
  138. const struct opt3001_scale *scale = &opt3001_scales[i];
  139. /*
  140. * Combine the integer and micro parts for comparison
  141. * purposes. Use milli lux precision to avoid 32-bit integer
  142. * overflows.
  143. */
  144. if ((val * 1000 + val2 / 1000) <=
  145. (scale->val * 1000 + scale->val2 / 1000)) {
  146. *exponent = i;
  147. return 0;
  148. }
  149. }
  150. return -EINVAL;
  151. }
  152. static void opt3001_to_iio_ret(struct opt3001 *opt, u8 exponent,
  153. u16 mantissa, int *val, int *val2)
  154. {
  155. int lux;
  156. lux = 10 * (mantissa << exponent);
  157. *val = lux / 1000;
  158. *val2 = (lux - (*val * 1000)) * 1000;
  159. }
  160. static void opt3001_set_mode(struct opt3001 *opt, u16 *reg, u16 mode)
  161. {
  162. *reg &= ~OPT3001_CONFIGURATION_M_MASK;
  163. *reg |= mode;
  164. opt->mode = mode;
  165. }
  166. static IIO_CONST_ATTR_INT_TIME_AVAIL("0.1 0.8");
  167. static struct attribute *opt3001_attributes[] = {
  168. &iio_const_attr_integration_time_available.dev_attr.attr,
  169. NULL
  170. };
  171. static const struct attribute_group opt3001_attribute_group = {
  172. .attrs = opt3001_attributes,
  173. };
  174. static const struct iio_event_spec opt3001_event_spec[] = {
  175. {
  176. .type = IIO_EV_TYPE_THRESH,
  177. .dir = IIO_EV_DIR_RISING,
  178. .mask_separate = BIT(IIO_EV_INFO_VALUE) |
  179. BIT(IIO_EV_INFO_ENABLE),
  180. },
  181. {
  182. .type = IIO_EV_TYPE_THRESH,
  183. .dir = IIO_EV_DIR_FALLING,
  184. .mask_separate = BIT(IIO_EV_INFO_VALUE) |
  185. BIT(IIO_EV_INFO_ENABLE),
  186. },
  187. };
  188. static const struct iio_chan_spec opt3001_channels[] = {
  189. {
  190. .type = IIO_LIGHT,
  191. .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) |
  192. BIT(IIO_CHAN_INFO_INT_TIME),
  193. .event_spec = opt3001_event_spec,
  194. .num_event_specs = ARRAY_SIZE(opt3001_event_spec),
  195. },
  196. IIO_CHAN_SOFT_TIMESTAMP(1),
  197. };
  198. static int opt3001_get_lux(struct opt3001 *opt, int *val, int *val2)
  199. {
  200. int ret;
  201. u16 mantissa;
  202. u16 reg;
  203. u8 exponent;
  204. u16 value;
  205. long timeout;
  206. if (opt->use_irq) {
  207. /*
  208. * Enable the end-of-conversion interrupt mechanism. Note that
  209. * doing so will overwrite the low-level limit value however we
  210. * will restore this value later on.
  211. */
  212. ret = i2c_smbus_write_word_swapped(opt->client,
  213. OPT3001_LOW_LIMIT,
  214. OPT3001_LOW_LIMIT_EOC_ENABLE);
  215. if (ret < 0) {
  216. dev_err(opt->dev, "failed to write register %02x\n",
  217. OPT3001_LOW_LIMIT);
  218. return ret;
  219. }
  220. /* Allow IRQ to access the device despite lock being set */
  221. opt->ok_to_ignore_lock = true;
  222. }
  223. /* Reset data-ready indicator flag */
  224. opt->result_ready = false;
  225. /* Configure for single-conversion mode and start a new conversion */
  226. ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_CONFIGURATION);
  227. if (ret < 0) {
  228. dev_err(opt->dev, "failed to read register %02x\n",
  229. OPT3001_CONFIGURATION);
  230. goto err;
  231. }
  232. reg = ret;
  233. opt3001_set_mode(opt, &reg, OPT3001_CONFIGURATION_M_SINGLE);
  234. ret = i2c_smbus_write_word_swapped(opt->client, OPT3001_CONFIGURATION,
  235. reg);
  236. if (ret < 0) {
  237. dev_err(opt->dev, "failed to write register %02x\n",
  238. OPT3001_CONFIGURATION);
  239. goto err;
  240. }
  241. if (opt->use_irq) {
  242. /* Wait for the IRQ to indicate the conversion is complete */
  243. ret = wait_event_timeout(opt->result_ready_queue,
  244. opt->result_ready,
  245. msecs_to_jiffies(OPT3001_RESULT_READY_LONG));
  246. } else {
  247. /* Sleep for result ready time */
  248. timeout = (opt->int_time == OPT3001_INT_TIME_SHORT) ?
  249. OPT3001_RESULT_READY_SHORT : OPT3001_RESULT_READY_LONG;
  250. msleep(timeout);
  251. /* Check result ready flag */
  252. ret = i2c_smbus_read_word_swapped(opt->client,
  253. OPT3001_CONFIGURATION);
  254. if (ret < 0) {
  255. dev_err(opt->dev, "failed to read register %02x\n",
  256. OPT3001_CONFIGURATION);
  257. goto err;
  258. }
  259. if (!(ret & OPT3001_CONFIGURATION_CRF)) {
  260. ret = -ETIMEDOUT;
  261. goto err;
  262. }
  263. /* Obtain value */
  264. ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_RESULT);
  265. if (ret < 0) {
  266. dev_err(opt->dev, "failed to read register %02x\n",
  267. OPT3001_RESULT);
  268. goto err;
  269. }
  270. opt->result = ret;
  271. opt->result_ready = true;
  272. }
  273. err:
  274. if (opt->use_irq)
  275. /* Disallow IRQ to access the device while lock is active */
  276. opt->ok_to_ignore_lock = false;
  277. if (ret == 0)
  278. return -ETIMEDOUT;
  279. else if (ret < 0)
  280. return ret;
  281. if (opt->use_irq) {
  282. /*
  283. * Disable the end-of-conversion interrupt mechanism by
  284. * restoring the low-level limit value (clearing
  285. * OPT3001_LOW_LIMIT_EOC_ENABLE). Note that selectively clearing
  286. * those enable bits would affect the actual limit value due to
  287. * bit-overlap and therefore can't be done.
  288. */
  289. value = (opt->low_thresh_exp << 12) | opt->low_thresh_mantissa;
  290. ret = i2c_smbus_write_word_swapped(opt->client,
  291. OPT3001_LOW_LIMIT,
  292. value);
  293. if (ret < 0) {
  294. dev_err(opt->dev, "failed to write register %02x\n",
  295. OPT3001_LOW_LIMIT);
  296. return ret;
  297. }
  298. }
  299. exponent = OPT3001_REG_EXPONENT(opt->result);
  300. mantissa = OPT3001_REG_MANTISSA(opt->result);
  301. opt3001_to_iio_ret(opt, exponent, mantissa, val, val2);
  302. return IIO_VAL_INT_PLUS_MICRO;
  303. }
  304. static int opt3001_get_int_time(struct opt3001 *opt, int *val, int *val2)
  305. {
  306. *val = 0;
  307. *val2 = opt->int_time;
  308. return IIO_VAL_INT_PLUS_MICRO;
  309. }
  310. static int opt3001_set_int_time(struct opt3001 *opt, int time)
  311. {
  312. int ret;
  313. u16 reg;
  314. ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_CONFIGURATION);
  315. if (ret < 0) {
  316. dev_err(opt->dev, "failed to read register %02x\n",
  317. OPT3001_CONFIGURATION);
  318. return ret;
  319. }
  320. reg = ret;
  321. switch (time) {
  322. case OPT3001_INT_TIME_SHORT:
  323. reg &= ~OPT3001_CONFIGURATION_CT;
  324. opt->int_time = OPT3001_INT_TIME_SHORT;
  325. break;
  326. case OPT3001_INT_TIME_LONG:
  327. reg |= OPT3001_CONFIGURATION_CT;
  328. opt->int_time = OPT3001_INT_TIME_LONG;
  329. break;
  330. default:
  331. return -EINVAL;
  332. }
  333. return i2c_smbus_write_word_swapped(opt->client, OPT3001_CONFIGURATION,
  334. reg);
  335. }
  336. static int opt3001_read_raw(struct iio_dev *iio,
  337. struct iio_chan_spec const *chan, int *val, int *val2,
  338. long mask)
  339. {
  340. struct opt3001 *opt = iio_priv(iio);
  341. int ret;
  342. if (opt->mode == OPT3001_CONFIGURATION_M_CONTINUOUS)
  343. return -EBUSY;
  344. if (chan->type != IIO_LIGHT)
  345. return -EINVAL;
  346. mutex_lock(&opt->lock);
  347. switch (mask) {
  348. case IIO_CHAN_INFO_PROCESSED:
  349. ret = opt3001_get_lux(opt, val, val2);
  350. break;
  351. case IIO_CHAN_INFO_INT_TIME:
  352. ret = opt3001_get_int_time(opt, val, val2);
  353. break;
  354. default:
  355. ret = -EINVAL;
  356. }
  357. mutex_unlock(&opt->lock);
  358. return ret;
  359. }
  360. static int opt3001_write_raw(struct iio_dev *iio,
  361. struct iio_chan_spec const *chan, int val, int val2,
  362. long mask)
  363. {
  364. struct opt3001 *opt = iio_priv(iio);
  365. int ret;
  366. if (opt->mode == OPT3001_CONFIGURATION_M_CONTINUOUS)
  367. return -EBUSY;
  368. if (chan->type != IIO_LIGHT)
  369. return -EINVAL;
  370. if (mask != IIO_CHAN_INFO_INT_TIME)
  371. return -EINVAL;
  372. if (val != 0)
  373. return -EINVAL;
  374. mutex_lock(&opt->lock);
  375. ret = opt3001_set_int_time(opt, val2);
  376. mutex_unlock(&opt->lock);
  377. return ret;
  378. }
  379. static int opt3001_read_event_value(struct iio_dev *iio,
  380. const struct iio_chan_spec *chan, enum iio_event_type type,
  381. enum iio_event_direction dir, enum iio_event_info info,
  382. int *val, int *val2)
  383. {
  384. struct opt3001 *opt = iio_priv(iio);
  385. int ret = IIO_VAL_INT_PLUS_MICRO;
  386. mutex_lock(&opt->lock);
  387. switch (dir) {
  388. case IIO_EV_DIR_RISING:
  389. opt3001_to_iio_ret(opt, opt->high_thresh_exp,
  390. opt->high_thresh_mantissa, val, val2);
  391. break;
  392. case IIO_EV_DIR_FALLING:
  393. opt3001_to_iio_ret(opt, opt->low_thresh_exp,
  394. opt->low_thresh_mantissa, val, val2);
  395. break;
  396. default:
  397. ret = -EINVAL;
  398. }
  399. mutex_unlock(&opt->lock);
  400. return ret;
  401. }
  402. static int opt3001_write_event_value(struct iio_dev *iio,
  403. const struct iio_chan_spec *chan, enum iio_event_type type,
  404. enum iio_event_direction dir, enum iio_event_info info,
  405. int val, int val2)
  406. {
  407. struct opt3001 *opt = iio_priv(iio);
  408. int ret;
  409. u16 mantissa;
  410. u16 value;
  411. u16 reg;
  412. u8 exponent;
  413. if (val < 0)
  414. return -EINVAL;
  415. mutex_lock(&opt->lock);
  416. ret = opt3001_find_scale(opt, val, val2, &exponent);
  417. if (ret < 0) {
  418. dev_err(opt->dev, "can't find scale for %d.%06u\n", val, val2);
  419. goto err;
  420. }
  421. mantissa = (((val * 1000) + (val2 / 1000)) / 10) >> exponent;
  422. value = (exponent << 12) | mantissa;
  423. switch (dir) {
  424. case IIO_EV_DIR_RISING:
  425. reg = OPT3001_HIGH_LIMIT;
  426. opt->high_thresh_mantissa = mantissa;
  427. opt->high_thresh_exp = exponent;
  428. break;
  429. case IIO_EV_DIR_FALLING:
  430. reg = OPT3001_LOW_LIMIT;
  431. opt->low_thresh_mantissa = mantissa;
  432. opt->low_thresh_exp = exponent;
  433. break;
  434. default:
  435. ret = -EINVAL;
  436. goto err;
  437. }
  438. ret = i2c_smbus_write_word_swapped(opt->client, reg, value);
  439. if (ret < 0) {
  440. dev_err(opt->dev, "failed to write register %02x\n", reg);
  441. goto err;
  442. }
  443. err:
  444. mutex_unlock(&opt->lock);
  445. return ret;
  446. }
  447. static int opt3001_read_event_config(struct iio_dev *iio,
  448. const struct iio_chan_spec *chan, enum iio_event_type type,
  449. enum iio_event_direction dir)
  450. {
  451. struct opt3001 *opt = iio_priv(iio);
  452. return opt->mode == OPT3001_CONFIGURATION_M_CONTINUOUS;
  453. }
  454. static int opt3001_write_event_config(struct iio_dev *iio,
  455. const struct iio_chan_spec *chan, enum iio_event_type type,
  456. enum iio_event_direction dir, int state)
  457. {
  458. struct opt3001 *opt = iio_priv(iio);
  459. int ret;
  460. u16 mode;
  461. u16 reg;
  462. if (state && opt->mode == OPT3001_CONFIGURATION_M_CONTINUOUS)
  463. return 0;
  464. if (!state && opt->mode == OPT3001_CONFIGURATION_M_SHUTDOWN)
  465. return 0;
  466. mutex_lock(&opt->lock);
  467. mode = state ? OPT3001_CONFIGURATION_M_CONTINUOUS
  468. : OPT3001_CONFIGURATION_M_SHUTDOWN;
  469. ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_CONFIGURATION);
  470. if (ret < 0) {
  471. dev_err(opt->dev, "failed to read register %02x\n",
  472. OPT3001_CONFIGURATION);
  473. goto err;
  474. }
  475. reg = ret;
  476. opt3001_set_mode(opt, &reg, mode);
  477. ret = i2c_smbus_write_word_swapped(opt->client, OPT3001_CONFIGURATION,
  478. reg);
  479. if (ret < 0) {
  480. dev_err(opt->dev, "failed to write register %02x\n",
  481. OPT3001_CONFIGURATION);
  482. goto err;
  483. }
  484. err:
  485. mutex_unlock(&opt->lock);
  486. return ret;
  487. }
  488. static const struct iio_info opt3001_info = {
  489. .attrs = &opt3001_attribute_group,
  490. .read_raw = opt3001_read_raw,
  491. .write_raw = opt3001_write_raw,
  492. .read_event_value = opt3001_read_event_value,
  493. .write_event_value = opt3001_write_event_value,
  494. .read_event_config = opt3001_read_event_config,
  495. .write_event_config = opt3001_write_event_config,
  496. };
  497. static int opt3001_read_id(struct opt3001 *opt)
  498. {
  499. char manufacturer[2];
  500. u16 device_id;
  501. int ret;
  502. ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_MANUFACTURER_ID);
  503. if (ret < 0) {
  504. dev_err(opt->dev, "failed to read register %02x\n",
  505. OPT3001_MANUFACTURER_ID);
  506. return ret;
  507. }
  508. manufacturer[0] = ret >> 8;
  509. manufacturer[1] = ret & 0xff;
  510. ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_DEVICE_ID);
  511. if (ret < 0) {
  512. dev_err(opt->dev, "failed to read register %02x\n",
  513. OPT3001_DEVICE_ID);
  514. return ret;
  515. }
  516. device_id = ret;
  517. dev_info(opt->dev, "Found %c%c OPT%04x\n", manufacturer[0],
  518. manufacturer[1], device_id);
  519. return 0;
  520. }
  521. static int opt3001_configure(struct opt3001 *opt)
  522. {
  523. int ret;
  524. u16 reg;
  525. ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_CONFIGURATION);
  526. if (ret < 0) {
  527. dev_err(opt->dev, "failed to read register %02x\n",
  528. OPT3001_CONFIGURATION);
  529. return ret;
  530. }
  531. reg = ret;
  532. /* Enable automatic full-scale setting mode */
  533. reg &= ~OPT3001_CONFIGURATION_RN_MASK;
  534. reg |= OPT3001_CONFIGURATION_RN_AUTO;
  535. /* Reflect status of the device's integration time setting */
  536. if (reg & OPT3001_CONFIGURATION_CT)
  537. opt->int_time = OPT3001_INT_TIME_LONG;
  538. else
  539. opt->int_time = OPT3001_INT_TIME_SHORT;
  540. /* Ensure device is in shutdown initially */
  541. opt3001_set_mode(opt, &reg, OPT3001_CONFIGURATION_M_SHUTDOWN);
  542. /* Configure for latched window-style comparison operation */
  543. reg |= OPT3001_CONFIGURATION_L;
  544. reg &= ~OPT3001_CONFIGURATION_POL;
  545. reg &= ~OPT3001_CONFIGURATION_ME;
  546. reg &= ~OPT3001_CONFIGURATION_FC_MASK;
  547. ret = i2c_smbus_write_word_swapped(opt->client, OPT3001_CONFIGURATION,
  548. reg);
  549. if (ret < 0) {
  550. dev_err(opt->dev, "failed to write register %02x\n",
  551. OPT3001_CONFIGURATION);
  552. return ret;
  553. }
  554. ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_LOW_LIMIT);
  555. if (ret < 0) {
  556. dev_err(opt->dev, "failed to read register %02x\n",
  557. OPT3001_LOW_LIMIT);
  558. return ret;
  559. }
  560. opt->low_thresh_mantissa = OPT3001_REG_MANTISSA(ret);
  561. opt->low_thresh_exp = OPT3001_REG_EXPONENT(ret);
  562. ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_HIGH_LIMIT);
  563. if (ret < 0) {
  564. dev_err(opt->dev, "failed to read register %02x\n",
  565. OPT3001_HIGH_LIMIT);
  566. return ret;
  567. }
  568. opt->high_thresh_mantissa = OPT3001_REG_MANTISSA(ret);
  569. opt->high_thresh_exp = OPT3001_REG_EXPONENT(ret);
  570. return 0;
  571. }
  572. static irqreturn_t opt3001_irq(int irq, void *_iio)
  573. {
  574. struct iio_dev *iio = _iio;
  575. struct opt3001 *opt = iio_priv(iio);
  576. int ret;
  577. bool wake_result_ready_queue = false;
  578. if (!opt->ok_to_ignore_lock)
  579. mutex_lock(&opt->lock);
  580. ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_CONFIGURATION);
  581. if (ret < 0) {
  582. dev_err(opt->dev, "failed to read register %02x\n",
  583. OPT3001_CONFIGURATION);
  584. goto out;
  585. }
  586. if ((ret & OPT3001_CONFIGURATION_M_MASK) ==
  587. OPT3001_CONFIGURATION_M_CONTINUOUS) {
  588. if (ret & OPT3001_CONFIGURATION_FH)
  589. iio_push_event(iio,
  590. IIO_UNMOD_EVENT_CODE(IIO_LIGHT, 0,
  591. IIO_EV_TYPE_THRESH,
  592. IIO_EV_DIR_RISING),
  593. iio_get_time_ns(iio));
  594. if (ret & OPT3001_CONFIGURATION_FL)
  595. iio_push_event(iio,
  596. IIO_UNMOD_EVENT_CODE(IIO_LIGHT, 0,
  597. IIO_EV_TYPE_THRESH,
  598. IIO_EV_DIR_FALLING),
  599. iio_get_time_ns(iio));
  600. } else if (ret & OPT3001_CONFIGURATION_CRF) {
  601. ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_RESULT);
  602. if (ret < 0) {
  603. dev_err(opt->dev, "failed to read register %02x\n",
  604. OPT3001_RESULT);
  605. goto out;
  606. }
  607. opt->result = ret;
  608. opt->result_ready = true;
  609. wake_result_ready_queue = true;
  610. }
  611. out:
  612. if (!opt->ok_to_ignore_lock)
  613. mutex_unlock(&opt->lock);
  614. if (wake_result_ready_queue)
  615. wake_up(&opt->result_ready_queue);
  616. return IRQ_HANDLED;
  617. }
  618. static int opt3001_probe(struct i2c_client *client,
  619. const struct i2c_device_id *id)
  620. {
  621. struct device *dev = &client->dev;
  622. struct iio_dev *iio;
  623. struct opt3001 *opt;
  624. int irq = client->irq;
  625. int ret;
  626. iio = devm_iio_device_alloc(dev, sizeof(*opt));
  627. if (!iio)
  628. return -ENOMEM;
  629. opt = iio_priv(iio);
  630. opt->client = client;
  631. opt->dev = dev;
  632. mutex_init(&opt->lock);
  633. init_waitqueue_head(&opt->result_ready_queue);
  634. i2c_set_clientdata(client, iio);
  635. ret = opt3001_read_id(opt);
  636. if (ret)
  637. return ret;
  638. ret = opt3001_configure(opt);
  639. if (ret)
  640. return ret;
  641. iio->name = client->name;
  642. iio->channels = opt3001_channels;
  643. iio->num_channels = ARRAY_SIZE(opt3001_channels);
  644. iio->dev.parent = dev;
  645. iio->modes = INDIO_DIRECT_MODE;
  646. iio->info = &opt3001_info;
  647. ret = devm_iio_device_register(dev, iio);
  648. if (ret) {
  649. dev_err(dev, "failed to register IIO device\n");
  650. return ret;
  651. }
  652. /* Make use of INT pin only if valid IRQ no. is given */
  653. if (irq > 0) {
  654. ret = request_threaded_irq(irq, NULL, opt3001_irq,
  655. IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
  656. "opt3001", iio);
  657. if (ret) {
  658. dev_err(dev, "failed to request IRQ #%d\n", irq);
  659. return ret;
  660. }
  661. opt->use_irq = true;
  662. } else {
  663. dev_dbg(opt->dev, "enabling interrupt-less operation\n");
  664. }
  665. return 0;
  666. }
  667. static int opt3001_remove(struct i2c_client *client)
  668. {
  669. struct iio_dev *iio = i2c_get_clientdata(client);
  670. struct opt3001 *opt = iio_priv(iio);
  671. int ret;
  672. u16 reg;
  673. if (opt->use_irq)
  674. free_irq(client->irq, iio);
  675. ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_CONFIGURATION);
  676. if (ret < 0) {
  677. dev_err(opt->dev, "failed to read register %02x\n",
  678. OPT3001_CONFIGURATION);
  679. return ret;
  680. }
  681. reg = ret;
  682. opt3001_set_mode(opt, &reg, OPT3001_CONFIGURATION_M_SHUTDOWN);
  683. ret = i2c_smbus_write_word_swapped(opt->client, OPT3001_CONFIGURATION,
  684. reg);
  685. if (ret < 0) {
  686. dev_err(opt->dev, "failed to write register %02x\n",
  687. OPT3001_CONFIGURATION);
  688. return ret;
  689. }
  690. return 0;
  691. }
  692. static const struct i2c_device_id opt3001_id[] = {
  693. { "opt3001", 0 },
  694. { } /* Terminating Entry */
  695. };
  696. MODULE_DEVICE_TABLE(i2c, opt3001_id);
  697. static const struct of_device_id opt3001_of_match[] = {
  698. { .compatible = "ti,opt3001" },
  699. { }
  700. };
  701. MODULE_DEVICE_TABLE(of, opt3001_of_match);
  702. static struct i2c_driver opt3001_driver = {
  703. .probe = opt3001_probe,
  704. .remove = opt3001_remove,
  705. .id_table = opt3001_id,
  706. .driver = {
  707. .name = "opt3001",
  708. .of_match_table = of_match_ptr(opt3001_of_match),
  709. },
  710. };
  711. module_i2c_driver(opt3001_driver);
  712. MODULE_LICENSE("GPL v2");
  713. MODULE_AUTHOR("Andreas Dannenberg <dannenberg@ti.com>");
  714. MODULE_DESCRIPTION("Texas Instruments OPT3001 Light Sensor Driver");