industrialio-buffer-dmaengine.c 5.9 KB

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  1. /*
  2. * Copyright 2014-2015 Analog Devices Inc.
  3. * Author: Lars-Peter Clausen <lars@metafoo.de>
  4. *
  5. * Licensed under the GPL-2 or later.
  6. */
  7. #include <linux/slab.h>
  8. #include <linux/kernel.h>
  9. #include <linux/dmaengine.h>
  10. #include <linux/dma-mapping.h>
  11. #include <linux/spinlock.h>
  12. #include <linux/err.h>
  13. #include <linux/iio/iio.h>
  14. #include <linux/iio/buffer.h>
  15. #include <linux/iio/buffer_impl.h>
  16. #include <linux/iio/buffer-dma.h>
  17. #include <linux/iio/buffer-dmaengine.h>
  18. /*
  19. * The IIO DMAengine buffer combines the generic IIO DMA buffer infrastructure
  20. * with the DMAengine framework. The generic IIO DMA buffer infrastructure is
  21. * used to manage the buffer memory and implement the IIO buffer operations
  22. * while the DMAengine framework is used to perform the DMA transfers. Combined
  23. * this results in a device independent fully functional DMA buffer
  24. * implementation that can be used by device drivers for peripherals which are
  25. * connected to a DMA controller which has a DMAengine driver implementation.
  26. */
  27. struct dmaengine_buffer {
  28. struct iio_dma_buffer_queue queue;
  29. struct dma_chan *chan;
  30. struct list_head active;
  31. size_t align;
  32. size_t max_size;
  33. };
  34. static struct dmaengine_buffer *iio_buffer_to_dmaengine_buffer(
  35. struct iio_buffer *buffer)
  36. {
  37. return container_of(buffer, struct dmaengine_buffer, queue.buffer);
  38. }
  39. static void iio_dmaengine_buffer_block_done(void *data)
  40. {
  41. struct iio_dma_buffer_block *block = data;
  42. unsigned long flags;
  43. spin_lock_irqsave(&block->queue->list_lock, flags);
  44. list_del(&block->head);
  45. spin_unlock_irqrestore(&block->queue->list_lock, flags);
  46. iio_dma_buffer_block_done(block);
  47. }
  48. static int iio_dmaengine_buffer_submit_block(struct iio_dma_buffer_queue *queue,
  49. struct iio_dma_buffer_block *block)
  50. {
  51. struct dmaengine_buffer *dmaengine_buffer =
  52. iio_buffer_to_dmaengine_buffer(&queue->buffer);
  53. struct dma_async_tx_descriptor *desc;
  54. dma_cookie_t cookie;
  55. block->bytes_used = min(block->size, dmaengine_buffer->max_size);
  56. block->bytes_used = rounddown(block->bytes_used,
  57. dmaengine_buffer->align);
  58. desc = dmaengine_prep_slave_single(dmaengine_buffer->chan,
  59. block->phys_addr, block->bytes_used, DMA_DEV_TO_MEM,
  60. DMA_PREP_INTERRUPT);
  61. if (!desc)
  62. return -ENOMEM;
  63. desc->callback = iio_dmaengine_buffer_block_done;
  64. desc->callback_param = block;
  65. cookie = dmaengine_submit(desc);
  66. if (dma_submit_error(cookie))
  67. return dma_submit_error(cookie);
  68. spin_lock_irq(&dmaengine_buffer->queue.list_lock);
  69. list_add_tail(&block->head, &dmaengine_buffer->active);
  70. spin_unlock_irq(&dmaengine_buffer->queue.list_lock);
  71. dma_async_issue_pending(dmaengine_buffer->chan);
  72. return 0;
  73. }
  74. static void iio_dmaengine_buffer_abort(struct iio_dma_buffer_queue *queue)
  75. {
  76. struct dmaengine_buffer *dmaengine_buffer =
  77. iio_buffer_to_dmaengine_buffer(&queue->buffer);
  78. dmaengine_terminate_sync(dmaengine_buffer->chan);
  79. iio_dma_buffer_block_list_abort(queue, &dmaengine_buffer->active);
  80. }
  81. static void iio_dmaengine_buffer_release(struct iio_buffer *buf)
  82. {
  83. struct dmaengine_buffer *dmaengine_buffer =
  84. iio_buffer_to_dmaengine_buffer(buf);
  85. iio_dma_buffer_release(&dmaengine_buffer->queue);
  86. kfree(dmaengine_buffer);
  87. }
  88. static const struct iio_buffer_access_funcs iio_dmaengine_buffer_ops = {
  89. .read_first_n = iio_dma_buffer_read,
  90. .set_bytes_per_datum = iio_dma_buffer_set_bytes_per_datum,
  91. .set_length = iio_dma_buffer_set_length,
  92. .request_update = iio_dma_buffer_request_update,
  93. .enable = iio_dma_buffer_enable,
  94. .disable = iio_dma_buffer_disable,
  95. .data_available = iio_dma_buffer_data_available,
  96. .release = iio_dmaengine_buffer_release,
  97. .modes = INDIO_BUFFER_HARDWARE,
  98. .flags = INDIO_BUFFER_FLAG_FIXED_WATERMARK,
  99. };
  100. static const struct iio_dma_buffer_ops iio_dmaengine_default_ops = {
  101. .submit = iio_dmaengine_buffer_submit_block,
  102. .abort = iio_dmaengine_buffer_abort,
  103. };
  104. /**
  105. * iio_dmaengine_buffer_alloc() - Allocate new buffer which uses DMAengine
  106. * @dev: Parent device for the buffer
  107. * @channel: DMA channel name, typically "rx".
  108. *
  109. * This allocates a new IIO buffer which internally uses the DMAengine framework
  110. * to perform its transfers. The parent device will be used to request the DMA
  111. * channel.
  112. *
  113. * Once done using the buffer iio_dmaengine_buffer_free() should be used to
  114. * release it.
  115. */
  116. struct iio_buffer *iio_dmaengine_buffer_alloc(struct device *dev,
  117. const char *channel)
  118. {
  119. struct dmaengine_buffer *dmaengine_buffer;
  120. unsigned int width, src_width, dest_width;
  121. struct dma_slave_caps caps;
  122. struct dma_chan *chan;
  123. int ret;
  124. dmaengine_buffer = kzalloc(sizeof(*dmaengine_buffer), GFP_KERNEL);
  125. if (!dmaengine_buffer)
  126. return ERR_PTR(-ENOMEM);
  127. chan = dma_request_slave_channel_reason(dev, channel);
  128. if (IS_ERR(chan)) {
  129. ret = PTR_ERR(chan);
  130. goto err_free;
  131. }
  132. ret = dma_get_slave_caps(chan, &caps);
  133. if (ret < 0)
  134. goto err_free;
  135. /* Needs to be aligned to the maximum of the minimums */
  136. if (caps.src_addr_widths)
  137. src_width = __ffs(caps.src_addr_widths);
  138. else
  139. src_width = 1;
  140. if (caps.dst_addr_widths)
  141. dest_width = __ffs(caps.dst_addr_widths);
  142. else
  143. dest_width = 1;
  144. width = max(src_width, dest_width);
  145. INIT_LIST_HEAD(&dmaengine_buffer->active);
  146. dmaengine_buffer->chan = chan;
  147. dmaengine_buffer->align = width;
  148. dmaengine_buffer->max_size = dma_get_max_seg_size(chan->device->dev);
  149. iio_dma_buffer_init(&dmaengine_buffer->queue, chan->device->dev,
  150. &iio_dmaengine_default_ops);
  151. dmaengine_buffer->queue.buffer.access = &iio_dmaengine_buffer_ops;
  152. return &dmaengine_buffer->queue.buffer;
  153. err_free:
  154. kfree(dmaengine_buffer);
  155. return ERR_PTR(ret);
  156. }
  157. EXPORT_SYMBOL(iio_dmaengine_buffer_alloc);
  158. /**
  159. * iio_dmaengine_buffer_free() - Free dmaengine buffer
  160. * @buffer: Buffer to free
  161. *
  162. * Frees a buffer previously allocated with iio_dmaengine_buffer_alloc().
  163. */
  164. void iio_dmaengine_buffer_free(struct iio_buffer *buffer)
  165. {
  166. struct dmaengine_buffer *dmaengine_buffer =
  167. iio_buffer_to_dmaengine_buffer(buffer);
  168. iio_dma_buffer_exit(&dmaengine_buffer->queue);
  169. dma_release_channel(dmaengine_buffer->chan);
  170. iio_buffer_put(buffer);
  171. }
  172. EXPORT_SYMBOL_GPL(iio_dmaengine_buffer_free);