ti-adc12138.c 13 KB

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  1. /*
  2. * ADC12130/ADC12132/ADC12138 12-bit plus sign ADC driver
  3. *
  4. * Copyright (c) 2016 Akinobu Mita <akinobu.mita@gmail.com>
  5. *
  6. * This file is subject to the terms and conditions of version 2 of
  7. * the GNU General Public License. See the file COPYING in the main
  8. * directory of this archive for more details.
  9. *
  10. * Datasheet: http://www.ti.com/lit/ds/symlink/adc12138.pdf
  11. */
  12. #include <linux/module.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/completion.h>
  15. #include <linux/clk.h>
  16. #include <linux/spi/spi.h>
  17. #include <linux/iio/iio.h>
  18. #include <linux/iio/buffer.h>
  19. #include <linux/iio/trigger.h>
  20. #include <linux/iio/triggered_buffer.h>
  21. #include <linux/iio/trigger_consumer.h>
  22. #include <linux/regulator/consumer.h>
  23. #define ADC12138_MODE_AUTO_CAL 0x08
  24. #define ADC12138_MODE_READ_STATUS 0x0c
  25. #define ADC12138_MODE_ACQUISITION_TIME_6 0x0e
  26. #define ADC12138_MODE_ACQUISITION_TIME_10 0x4e
  27. #define ADC12138_MODE_ACQUISITION_TIME_18 0x8e
  28. #define ADC12138_MODE_ACQUISITION_TIME_34 0xce
  29. #define ADC12138_STATUS_CAL BIT(6)
  30. enum {
  31. adc12130,
  32. adc12132,
  33. adc12138,
  34. };
  35. struct adc12138 {
  36. struct spi_device *spi;
  37. unsigned int id;
  38. /* conversion clock */
  39. struct clk *cclk;
  40. /* positive analog voltage reference */
  41. struct regulator *vref_p;
  42. /* negative analog voltage reference */
  43. struct regulator *vref_n;
  44. struct mutex lock;
  45. struct completion complete;
  46. /* The number of cclk periods for the S/H's acquisition time */
  47. unsigned int acquisition_time;
  48. u8 tx_buf[2] ____cacheline_aligned;
  49. u8 rx_buf[2];
  50. };
  51. #define ADC12138_VOLTAGE_CHANNEL(chan) \
  52. { \
  53. .type = IIO_VOLTAGE, \
  54. .indexed = 1, \
  55. .channel = chan, \
  56. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  57. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \
  58. | BIT(IIO_CHAN_INFO_OFFSET), \
  59. .scan_index = chan, \
  60. .scan_type = { \
  61. .sign = 's', \
  62. .realbits = 13, \
  63. .storagebits = 16, \
  64. .shift = 3, \
  65. .endianness = IIO_BE, \
  66. }, \
  67. }
  68. #define ADC12138_VOLTAGE_CHANNEL_DIFF(chan1, chan2, si) \
  69. { \
  70. .type = IIO_VOLTAGE, \
  71. .indexed = 1, \
  72. .channel = (chan1), \
  73. .channel2 = (chan2), \
  74. .differential = 1, \
  75. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  76. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \
  77. | BIT(IIO_CHAN_INFO_OFFSET), \
  78. .scan_index = si, \
  79. .scan_type = { \
  80. .sign = 's', \
  81. .realbits = 13, \
  82. .storagebits = 16, \
  83. .shift = 3, \
  84. .endianness = IIO_BE, \
  85. }, \
  86. }
  87. static const struct iio_chan_spec adc12132_channels[] = {
  88. ADC12138_VOLTAGE_CHANNEL(0),
  89. ADC12138_VOLTAGE_CHANNEL(1),
  90. ADC12138_VOLTAGE_CHANNEL_DIFF(0, 1, 2),
  91. ADC12138_VOLTAGE_CHANNEL_DIFF(1, 0, 3),
  92. IIO_CHAN_SOFT_TIMESTAMP(4),
  93. };
  94. static const struct iio_chan_spec adc12138_channels[] = {
  95. ADC12138_VOLTAGE_CHANNEL(0),
  96. ADC12138_VOLTAGE_CHANNEL(1),
  97. ADC12138_VOLTAGE_CHANNEL(2),
  98. ADC12138_VOLTAGE_CHANNEL(3),
  99. ADC12138_VOLTAGE_CHANNEL(4),
  100. ADC12138_VOLTAGE_CHANNEL(5),
  101. ADC12138_VOLTAGE_CHANNEL(6),
  102. ADC12138_VOLTAGE_CHANNEL(7),
  103. ADC12138_VOLTAGE_CHANNEL_DIFF(0, 1, 8),
  104. ADC12138_VOLTAGE_CHANNEL_DIFF(1, 0, 9),
  105. ADC12138_VOLTAGE_CHANNEL_DIFF(2, 3, 10),
  106. ADC12138_VOLTAGE_CHANNEL_DIFF(3, 2, 11),
  107. ADC12138_VOLTAGE_CHANNEL_DIFF(4, 5, 12),
  108. ADC12138_VOLTAGE_CHANNEL_DIFF(5, 4, 13),
  109. ADC12138_VOLTAGE_CHANNEL_DIFF(6, 7, 14),
  110. ADC12138_VOLTAGE_CHANNEL_DIFF(7, 6, 15),
  111. IIO_CHAN_SOFT_TIMESTAMP(16),
  112. };
  113. static int adc12138_mode_programming(struct adc12138 *adc, u8 mode,
  114. void *rx_buf, int len)
  115. {
  116. struct spi_transfer xfer = {
  117. .tx_buf = adc->tx_buf,
  118. .rx_buf = adc->rx_buf,
  119. .len = len,
  120. };
  121. int ret;
  122. /* Skip unused bits for ADC12130 and ADC12132 */
  123. if (adc->id != adc12138)
  124. mode = (mode & 0xc0) | ((mode & 0x0f) << 2);
  125. adc->tx_buf[0] = mode;
  126. ret = spi_sync_transfer(adc->spi, &xfer, 1);
  127. if (ret)
  128. return ret;
  129. memcpy(rx_buf, adc->rx_buf, len);
  130. return 0;
  131. }
  132. static int adc12138_read_status(struct adc12138 *adc)
  133. {
  134. u8 rx_buf[2];
  135. int ret;
  136. ret = adc12138_mode_programming(adc, ADC12138_MODE_READ_STATUS,
  137. rx_buf, 2);
  138. if (ret)
  139. return ret;
  140. return (rx_buf[0] << 1) | (rx_buf[1] >> 7);
  141. }
  142. static int __adc12138_start_conv(struct adc12138 *adc,
  143. struct iio_chan_spec const *channel,
  144. void *data, int len)
  145. {
  146. static const u8 ch_to_mux[] = { 0, 4, 1, 5, 2, 6, 3, 7 };
  147. u8 mode = (ch_to_mux[channel->channel] << 4) |
  148. (channel->differential ? 0 : 0x80);
  149. return adc12138_mode_programming(adc, mode, data, len);
  150. }
  151. static int adc12138_start_conv(struct adc12138 *adc,
  152. struct iio_chan_spec const *channel)
  153. {
  154. u8 trash;
  155. return __adc12138_start_conv(adc, channel, &trash, 1);
  156. }
  157. static int adc12138_start_and_read_conv(struct adc12138 *adc,
  158. struct iio_chan_spec const *channel,
  159. __be16 *data)
  160. {
  161. return __adc12138_start_conv(adc, channel, data, 2);
  162. }
  163. static int adc12138_read_conv_data(struct adc12138 *adc, __be16 *value)
  164. {
  165. /* Issue a read status instruction and read previous conversion data */
  166. return adc12138_mode_programming(adc, ADC12138_MODE_READ_STATUS,
  167. value, sizeof(*value));
  168. }
  169. static int adc12138_wait_eoc(struct adc12138 *adc, unsigned long timeout)
  170. {
  171. if (!wait_for_completion_timeout(&adc->complete, timeout))
  172. return -ETIMEDOUT;
  173. return 0;
  174. }
  175. static int adc12138_adc_conversion(struct adc12138 *adc,
  176. struct iio_chan_spec const *channel,
  177. __be16 *value)
  178. {
  179. int ret;
  180. reinit_completion(&adc->complete);
  181. ret = adc12138_start_conv(adc, channel);
  182. if (ret)
  183. return ret;
  184. ret = adc12138_wait_eoc(adc, msecs_to_jiffies(100));
  185. if (ret)
  186. return ret;
  187. return adc12138_read_conv_data(adc, value);
  188. }
  189. static int adc12138_read_raw(struct iio_dev *iio,
  190. struct iio_chan_spec const *channel, int *value,
  191. int *shift, long mask)
  192. {
  193. struct adc12138 *adc = iio_priv(iio);
  194. int ret;
  195. __be16 data;
  196. switch (mask) {
  197. case IIO_CHAN_INFO_RAW:
  198. mutex_lock(&adc->lock);
  199. ret = adc12138_adc_conversion(adc, channel, &data);
  200. mutex_unlock(&adc->lock);
  201. if (ret)
  202. return ret;
  203. *value = sign_extend32(be16_to_cpu(data) >> 3, 12);
  204. return IIO_VAL_INT;
  205. case IIO_CHAN_INFO_SCALE:
  206. ret = regulator_get_voltage(adc->vref_p);
  207. if (ret < 0)
  208. return ret;
  209. *value = ret;
  210. if (!IS_ERR(adc->vref_n)) {
  211. ret = regulator_get_voltage(adc->vref_n);
  212. if (ret < 0)
  213. return ret;
  214. *value -= ret;
  215. }
  216. /* convert regulator output voltage to mV */
  217. *value /= 1000;
  218. *shift = channel->scan_type.realbits - 1;
  219. return IIO_VAL_FRACTIONAL_LOG2;
  220. case IIO_CHAN_INFO_OFFSET:
  221. if (!IS_ERR(adc->vref_n)) {
  222. *value = regulator_get_voltage(adc->vref_n);
  223. if (*value < 0)
  224. return *value;
  225. } else {
  226. *value = 0;
  227. }
  228. /* convert regulator output voltage to mV */
  229. *value /= 1000;
  230. return IIO_VAL_INT;
  231. }
  232. return -EINVAL;
  233. }
  234. static const struct iio_info adc12138_info = {
  235. .read_raw = adc12138_read_raw,
  236. };
  237. static int adc12138_init(struct adc12138 *adc)
  238. {
  239. int ret;
  240. int status;
  241. u8 mode;
  242. u8 trash;
  243. reinit_completion(&adc->complete);
  244. ret = adc12138_mode_programming(adc, ADC12138_MODE_AUTO_CAL, &trash, 1);
  245. if (ret)
  246. return ret;
  247. /* data output at this time has no significance */
  248. status = adc12138_read_status(adc);
  249. if (status < 0)
  250. return status;
  251. adc12138_wait_eoc(adc, msecs_to_jiffies(100));
  252. status = adc12138_read_status(adc);
  253. if (status & ADC12138_STATUS_CAL) {
  254. dev_warn(&adc->spi->dev,
  255. "Auto Cal sequence is still in progress: %#x\n",
  256. status);
  257. return -EIO;
  258. }
  259. switch (adc->acquisition_time) {
  260. case 6:
  261. mode = ADC12138_MODE_ACQUISITION_TIME_6;
  262. break;
  263. case 10:
  264. mode = ADC12138_MODE_ACQUISITION_TIME_10;
  265. break;
  266. case 18:
  267. mode = ADC12138_MODE_ACQUISITION_TIME_18;
  268. break;
  269. case 34:
  270. mode = ADC12138_MODE_ACQUISITION_TIME_34;
  271. break;
  272. default:
  273. return -EINVAL;
  274. }
  275. return adc12138_mode_programming(adc, mode, &trash, 1);
  276. }
  277. static irqreturn_t adc12138_trigger_handler(int irq, void *p)
  278. {
  279. struct iio_poll_func *pf = p;
  280. struct iio_dev *indio_dev = pf->indio_dev;
  281. struct adc12138 *adc = iio_priv(indio_dev);
  282. __be16 data[20] = { }; /* 16x 2 bytes ADC data + 8 bytes timestamp */
  283. __be16 trash;
  284. int ret;
  285. int scan_index;
  286. int i = 0;
  287. mutex_lock(&adc->lock);
  288. for_each_set_bit(scan_index, indio_dev->active_scan_mask,
  289. indio_dev->masklength) {
  290. const struct iio_chan_spec *scan_chan =
  291. &indio_dev->channels[scan_index];
  292. reinit_completion(&adc->complete);
  293. ret = adc12138_start_and_read_conv(adc, scan_chan,
  294. i ? &data[i - 1] : &trash);
  295. if (ret) {
  296. dev_warn(&adc->spi->dev,
  297. "failed to start conversion\n");
  298. goto out;
  299. }
  300. ret = adc12138_wait_eoc(adc, msecs_to_jiffies(100));
  301. if (ret) {
  302. dev_warn(&adc->spi->dev, "wait eoc timeout\n");
  303. goto out;
  304. }
  305. i++;
  306. }
  307. if (i) {
  308. ret = adc12138_read_conv_data(adc, &data[i - 1]);
  309. if (ret) {
  310. dev_warn(&adc->spi->dev,
  311. "failed to get conversion data\n");
  312. goto out;
  313. }
  314. }
  315. iio_push_to_buffers_with_timestamp(indio_dev, data,
  316. iio_get_time_ns(indio_dev));
  317. out:
  318. mutex_unlock(&adc->lock);
  319. iio_trigger_notify_done(indio_dev->trig);
  320. return IRQ_HANDLED;
  321. }
  322. static irqreturn_t adc12138_eoc_handler(int irq, void *p)
  323. {
  324. struct iio_dev *indio_dev = p;
  325. struct adc12138 *adc = iio_priv(indio_dev);
  326. complete(&adc->complete);
  327. return IRQ_HANDLED;
  328. }
  329. static int adc12138_probe(struct spi_device *spi)
  330. {
  331. struct iio_dev *indio_dev;
  332. struct adc12138 *adc;
  333. int ret;
  334. indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc));
  335. if (!indio_dev)
  336. return -ENOMEM;
  337. adc = iio_priv(indio_dev);
  338. adc->spi = spi;
  339. adc->id = spi_get_device_id(spi)->driver_data;
  340. mutex_init(&adc->lock);
  341. init_completion(&adc->complete);
  342. indio_dev->name = spi_get_device_id(spi)->name;
  343. indio_dev->dev.parent = &spi->dev;
  344. indio_dev->info = &adc12138_info;
  345. indio_dev->modes = INDIO_DIRECT_MODE;
  346. switch (adc->id) {
  347. case adc12130:
  348. case adc12132:
  349. indio_dev->channels = adc12132_channels;
  350. indio_dev->num_channels = ARRAY_SIZE(adc12132_channels);
  351. break;
  352. case adc12138:
  353. indio_dev->channels = adc12138_channels;
  354. indio_dev->num_channels = ARRAY_SIZE(adc12138_channels);
  355. break;
  356. default:
  357. return -EINVAL;
  358. }
  359. ret = of_property_read_u32(spi->dev.of_node, "ti,acquisition-time",
  360. &adc->acquisition_time);
  361. if (ret)
  362. adc->acquisition_time = 10;
  363. adc->cclk = devm_clk_get(&spi->dev, NULL);
  364. if (IS_ERR(adc->cclk))
  365. return PTR_ERR(adc->cclk);
  366. adc->vref_p = devm_regulator_get(&spi->dev, "vref-p");
  367. if (IS_ERR(adc->vref_p))
  368. return PTR_ERR(adc->vref_p);
  369. adc->vref_n = devm_regulator_get_optional(&spi->dev, "vref-n");
  370. if (IS_ERR(adc->vref_n)) {
  371. /*
  372. * Assume vref_n is 0V if an optional regulator is not
  373. * specified, otherwise return the error code.
  374. */
  375. ret = PTR_ERR(adc->vref_n);
  376. if (ret != -ENODEV)
  377. return ret;
  378. }
  379. ret = devm_request_irq(&spi->dev, spi->irq, adc12138_eoc_handler,
  380. IRQF_TRIGGER_RISING, indio_dev->name, indio_dev);
  381. if (ret)
  382. return ret;
  383. ret = clk_prepare_enable(adc->cclk);
  384. if (ret)
  385. return ret;
  386. ret = regulator_enable(adc->vref_p);
  387. if (ret)
  388. goto err_clk_disable;
  389. if (!IS_ERR(adc->vref_n)) {
  390. ret = regulator_enable(adc->vref_n);
  391. if (ret)
  392. goto err_vref_p_disable;
  393. }
  394. ret = adc12138_init(adc);
  395. if (ret)
  396. goto err_vref_n_disable;
  397. spi_set_drvdata(spi, indio_dev);
  398. ret = iio_triggered_buffer_setup(indio_dev, NULL,
  399. adc12138_trigger_handler, NULL);
  400. if (ret)
  401. goto err_vref_n_disable;
  402. ret = iio_device_register(indio_dev);
  403. if (ret)
  404. goto err_buffer_cleanup;
  405. return 0;
  406. err_buffer_cleanup:
  407. iio_triggered_buffer_cleanup(indio_dev);
  408. err_vref_n_disable:
  409. if (!IS_ERR(adc->vref_n))
  410. regulator_disable(adc->vref_n);
  411. err_vref_p_disable:
  412. regulator_disable(adc->vref_p);
  413. err_clk_disable:
  414. clk_disable_unprepare(adc->cclk);
  415. return ret;
  416. }
  417. static int adc12138_remove(struct spi_device *spi)
  418. {
  419. struct iio_dev *indio_dev = spi_get_drvdata(spi);
  420. struct adc12138 *adc = iio_priv(indio_dev);
  421. iio_device_unregister(indio_dev);
  422. iio_triggered_buffer_cleanup(indio_dev);
  423. if (!IS_ERR(adc->vref_n))
  424. regulator_disable(adc->vref_n);
  425. regulator_disable(adc->vref_p);
  426. clk_disable_unprepare(adc->cclk);
  427. return 0;
  428. }
  429. #ifdef CONFIG_OF
  430. static const struct of_device_id adc12138_dt_ids[] = {
  431. { .compatible = "ti,adc12130", },
  432. { .compatible = "ti,adc12132", },
  433. { .compatible = "ti,adc12138", },
  434. {}
  435. };
  436. MODULE_DEVICE_TABLE(of, adc12138_dt_ids);
  437. #endif
  438. static const struct spi_device_id adc12138_id[] = {
  439. { "adc12130", adc12130 },
  440. { "adc12132", adc12132 },
  441. { "adc12138", adc12138 },
  442. {}
  443. };
  444. MODULE_DEVICE_TABLE(spi, adc12138_id);
  445. static struct spi_driver adc12138_driver = {
  446. .driver = {
  447. .name = "adc12138",
  448. .of_match_table = of_match_ptr(adc12138_dt_ids),
  449. },
  450. .probe = adc12138_probe,
  451. .remove = adc12138_remove,
  452. .id_table = adc12138_id,
  453. };
  454. module_spi_driver(adc12138_driver);
  455. MODULE_AUTHOR("Akinobu Mita <akinobu.mita@gmail.com>");
  456. MODULE_DESCRIPTION("ADC12130/ADC12132/ADC12138 driver");
  457. MODULE_LICENSE("GPL v2");