r600_dpm.c 43 KB

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  1. /*
  2. * Copyright 2011 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Alex Deucher
  23. */
  24. #include <drm/drmP.h>
  25. #include "radeon.h"
  26. #include "radeon_asic.h"
  27. #include "r600d.h"
  28. #include "r600_dpm.h"
  29. #include "atom.h"
  30. const u32 r600_utc[R600_PM_NUMBER_OF_TC] =
  31. {
  32. R600_UTC_DFLT_00,
  33. R600_UTC_DFLT_01,
  34. R600_UTC_DFLT_02,
  35. R600_UTC_DFLT_03,
  36. R600_UTC_DFLT_04,
  37. R600_UTC_DFLT_05,
  38. R600_UTC_DFLT_06,
  39. R600_UTC_DFLT_07,
  40. R600_UTC_DFLT_08,
  41. R600_UTC_DFLT_09,
  42. R600_UTC_DFLT_10,
  43. R600_UTC_DFLT_11,
  44. R600_UTC_DFLT_12,
  45. R600_UTC_DFLT_13,
  46. R600_UTC_DFLT_14,
  47. };
  48. const u32 r600_dtc[R600_PM_NUMBER_OF_TC] =
  49. {
  50. R600_DTC_DFLT_00,
  51. R600_DTC_DFLT_01,
  52. R600_DTC_DFLT_02,
  53. R600_DTC_DFLT_03,
  54. R600_DTC_DFLT_04,
  55. R600_DTC_DFLT_05,
  56. R600_DTC_DFLT_06,
  57. R600_DTC_DFLT_07,
  58. R600_DTC_DFLT_08,
  59. R600_DTC_DFLT_09,
  60. R600_DTC_DFLT_10,
  61. R600_DTC_DFLT_11,
  62. R600_DTC_DFLT_12,
  63. R600_DTC_DFLT_13,
  64. R600_DTC_DFLT_14,
  65. };
  66. void r600_dpm_print_class_info(u32 class, u32 class2)
  67. {
  68. const char *s;
  69. switch (class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
  70. case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
  71. default:
  72. s = "none";
  73. break;
  74. case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
  75. s = "battery";
  76. break;
  77. case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
  78. s = "balanced";
  79. break;
  80. case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
  81. s = "performance";
  82. break;
  83. }
  84. printk("\tui class: %s\n", s);
  85. printk("\tinternal class:");
  86. if (((class & ~ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 0) &&
  87. (class2 == 0))
  88. pr_cont(" none");
  89. else {
  90. if (class & ATOM_PPLIB_CLASSIFICATION_BOOT)
  91. pr_cont(" boot");
  92. if (class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
  93. pr_cont(" thermal");
  94. if (class & ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE)
  95. pr_cont(" limited_pwr");
  96. if (class & ATOM_PPLIB_CLASSIFICATION_REST)
  97. pr_cont(" rest");
  98. if (class & ATOM_PPLIB_CLASSIFICATION_FORCED)
  99. pr_cont(" forced");
  100. if (class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
  101. pr_cont(" 3d_perf");
  102. if (class & ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE)
  103. pr_cont(" ovrdrv");
  104. if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
  105. pr_cont(" uvd");
  106. if (class & ATOM_PPLIB_CLASSIFICATION_3DLOW)
  107. pr_cont(" 3d_low");
  108. if (class & ATOM_PPLIB_CLASSIFICATION_ACPI)
  109. pr_cont(" acpi");
  110. if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
  111. pr_cont(" uvd_hd2");
  112. if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
  113. pr_cont(" uvd_hd");
  114. if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
  115. pr_cont(" uvd_sd");
  116. if (class2 & ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2)
  117. pr_cont(" limited_pwr2");
  118. if (class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
  119. pr_cont(" ulv");
  120. if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
  121. pr_cont(" uvd_mvc");
  122. }
  123. pr_cont("\n");
  124. }
  125. void r600_dpm_print_cap_info(u32 caps)
  126. {
  127. printk("\tcaps:");
  128. if (caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
  129. pr_cont(" single_disp");
  130. if (caps & ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK)
  131. pr_cont(" video");
  132. if (caps & ATOM_PPLIB_DISALLOW_ON_DC)
  133. pr_cont(" no_dc");
  134. pr_cont("\n");
  135. }
  136. void r600_dpm_print_ps_status(struct radeon_device *rdev,
  137. struct radeon_ps *rps)
  138. {
  139. printk("\tstatus:");
  140. if (rps == rdev->pm.dpm.current_ps)
  141. pr_cont(" c");
  142. if (rps == rdev->pm.dpm.requested_ps)
  143. pr_cont(" r");
  144. if (rps == rdev->pm.dpm.boot_ps)
  145. pr_cont(" b");
  146. pr_cont("\n");
  147. }
  148. u32 r600_dpm_get_vblank_time(struct radeon_device *rdev)
  149. {
  150. struct drm_device *dev = rdev->ddev;
  151. struct drm_crtc *crtc;
  152. struct radeon_crtc *radeon_crtc;
  153. u32 vblank_in_pixels;
  154. u32 vblank_time_us = 0xffffffff; /* if the displays are off, vblank time is max */
  155. if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
  156. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  157. radeon_crtc = to_radeon_crtc(crtc);
  158. if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) {
  159. vblank_in_pixels =
  160. radeon_crtc->hw_mode.crtc_htotal *
  161. (radeon_crtc->hw_mode.crtc_vblank_end -
  162. radeon_crtc->hw_mode.crtc_vdisplay +
  163. (radeon_crtc->v_border * 2));
  164. vblank_time_us = vblank_in_pixels * 1000 / radeon_crtc->hw_mode.clock;
  165. break;
  166. }
  167. }
  168. }
  169. return vblank_time_us;
  170. }
  171. u32 r600_dpm_get_vrefresh(struct radeon_device *rdev)
  172. {
  173. struct drm_device *dev = rdev->ddev;
  174. struct drm_crtc *crtc;
  175. struct radeon_crtc *radeon_crtc;
  176. u32 vrefresh = 0;
  177. if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
  178. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  179. radeon_crtc = to_radeon_crtc(crtc);
  180. if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) {
  181. vrefresh = drm_mode_vrefresh(&radeon_crtc->hw_mode);
  182. break;
  183. }
  184. }
  185. }
  186. return vrefresh;
  187. }
  188. void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
  189. u32 *p, u32 *u)
  190. {
  191. u32 b_c = 0;
  192. u32 i_c;
  193. u32 tmp;
  194. i_c = (i * r_c) / 100;
  195. tmp = i_c >> p_b;
  196. while (tmp) {
  197. b_c++;
  198. tmp >>= 1;
  199. }
  200. *u = (b_c + 1) / 2;
  201. *p = i_c / (1 << (2 * (*u)));
  202. }
  203. int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th)
  204. {
  205. u32 k, a, ah, al;
  206. u32 t1;
  207. if ((fl == 0) || (fh == 0) || (fl > fh))
  208. return -EINVAL;
  209. k = (100 * fh) / fl;
  210. t1 = (t * (k - 100));
  211. a = (1000 * (100 * h + t1)) / (10000 + (t1 / 100));
  212. a = (a + 5) / 10;
  213. ah = ((a * t) + 5000) / 10000;
  214. al = a - ah;
  215. *th = t - ah;
  216. *tl = t + al;
  217. return 0;
  218. }
  219. void r600_gfx_clockgating_enable(struct radeon_device *rdev, bool enable)
  220. {
  221. int i;
  222. if (enable) {
  223. WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
  224. } else {
  225. WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
  226. WREG32(CG_RLC_REQ_AND_RSP, 0x2);
  227. for (i = 0; i < rdev->usec_timeout; i++) {
  228. if (((RREG32(CG_RLC_REQ_AND_RSP) & CG_RLC_RSP_TYPE_MASK) >> CG_RLC_RSP_TYPE_SHIFT) == 1)
  229. break;
  230. udelay(1);
  231. }
  232. WREG32(CG_RLC_REQ_AND_RSP, 0x0);
  233. WREG32(GRBM_PWR_CNTL, 0x1);
  234. RREG32(GRBM_PWR_CNTL);
  235. }
  236. }
  237. void r600_dynamicpm_enable(struct radeon_device *rdev, bool enable)
  238. {
  239. if (enable)
  240. WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
  241. else
  242. WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
  243. }
  244. void r600_enable_thermal_protection(struct radeon_device *rdev, bool enable)
  245. {
  246. if (enable)
  247. WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
  248. else
  249. WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
  250. }
  251. void r600_enable_acpi_pm(struct radeon_device *rdev)
  252. {
  253. WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
  254. }
  255. void r600_enable_dynamic_pcie_gen2(struct radeon_device *rdev, bool enable)
  256. {
  257. if (enable)
  258. WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE);
  259. else
  260. WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE);
  261. }
  262. bool r600_dynamicpm_enabled(struct radeon_device *rdev)
  263. {
  264. if (RREG32(GENERAL_PWRMGT) & GLOBAL_PWRMGT_EN)
  265. return true;
  266. else
  267. return false;
  268. }
  269. void r600_enable_sclk_control(struct radeon_device *rdev, bool enable)
  270. {
  271. if (enable)
  272. WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
  273. else
  274. WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
  275. }
  276. void r600_enable_mclk_control(struct radeon_device *rdev, bool enable)
  277. {
  278. if (enable)
  279. WREG32_P(MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF);
  280. else
  281. WREG32_P(MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF);
  282. }
  283. void r600_enable_spll_bypass(struct radeon_device *rdev, bool enable)
  284. {
  285. if (enable)
  286. WREG32_P(CG_SPLL_FUNC_CNTL, SPLL_BYPASS_EN, ~SPLL_BYPASS_EN);
  287. else
  288. WREG32_P(CG_SPLL_FUNC_CNTL, 0, ~SPLL_BYPASS_EN);
  289. }
  290. void r600_wait_for_spll_change(struct radeon_device *rdev)
  291. {
  292. int i;
  293. for (i = 0; i < rdev->usec_timeout; i++) {
  294. if (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_CHG_STATUS)
  295. break;
  296. udelay(1);
  297. }
  298. }
  299. void r600_set_bsp(struct radeon_device *rdev, u32 u, u32 p)
  300. {
  301. WREG32(CG_BSP, BSP(p) | BSU(u));
  302. }
  303. void r600_set_at(struct radeon_device *rdev,
  304. u32 l_to_m, u32 m_to_h,
  305. u32 h_to_m, u32 m_to_l)
  306. {
  307. WREG32(CG_RT, FLS(l_to_m) | FMS(m_to_h));
  308. WREG32(CG_LT, FHS(h_to_m) | FMS(m_to_l));
  309. }
  310. void r600_set_tc(struct radeon_device *rdev,
  311. u32 index, u32 u_t, u32 d_t)
  312. {
  313. WREG32(CG_FFCT_0 + (index * 4), UTC_0(u_t) | DTC_0(d_t));
  314. }
  315. void r600_select_td(struct radeon_device *rdev,
  316. enum r600_td td)
  317. {
  318. if (td == R600_TD_AUTO)
  319. WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
  320. else
  321. WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
  322. if (td == R600_TD_UP)
  323. WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
  324. if (td == R600_TD_DOWN)
  325. WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
  326. }
  327. void r600_set_vrc(struct radeon_device *rdev, u32 vrv)
  328. {
  329. WREG32(CG_FTV, vrv);
  330. }
  331. void r600_set_tpu(struct radeon_device *rdev, u32 u)
  332. {
  333. WREG32_P(CG_TPC, TPU(u), ~TPU_MASK);
  334. }
  335. void r600_set_tpc(struct radeon_device *rdev, u32 c)
  336. {
  337. WREG32_P(CG_TPC, TPCC(c), ~TPCC_MASK);
  338. }
  339. void r600_set_sstu(struct radeon_device *rdev, u32 u)
  340. {
  341. WREG32_P(CG_SSP, CG_SSTU(u), ~CG_SSTU_MASK);
  342. }
  343. void r600_set_sst(struct radeon_device *rdev, u32 t)
  344. {
  345. WREG32_P(CG_SSP, CG_SST(t), ~CG_SST_MASK);
  346. }
  347. void r600_set_git(struct radeon_device *rdev, u32 t)
  348. {
  349. WREG32_P(CG_GIT, CG_GICST(t), ~CG_GICST_MASK);
  350. }
  351. void r600_set_fctu(struct radeon_device *rdev, u32 u)
  352. {
  353. WREG32_P(CG_FC_T, FC_TU(u), ~FC_TU_MASK);
  354. }
  355. void r600_set_fct(struct radeon_device *rdev, u32 t)
  356. {
  357. WREG32_P(CG_FC_T, FC_T(t), ~FC_T_MASK);
  358. }
  359. void r600_set_ctxcgtt3d_rphc(struct radeon_device *rdev, u32 p)
  360. {
  361. WREG32_P(CG_CTX_CGTT3D_R, PHC(p), ~PHC_MASK);
  362. }
  363. void r600_set_ctxcgtt3d_rsdc(struct radeon_device *rdev, u32 s)
  364. {
  365. WREG32_P(CG_CTX_CGTT3D_R, SDC(s), ~SDC_MASK);
  366. }
  367. void r600_set_vddc3d_oorsu(struct radeon_device *rdev, u32 u)
  368. {
  369. WREG32_P(CG_VDDC3D_OOR, SU(u), ~SU_MASK);
  370. }
  371. void r600_set_vddc3d_oorphc(struct radeon_device *rdev, u32 p)
  372. {
  373. WREG32_P(CG_VDDC3D_OOR, PHC(p), ~PHC_MASK);
  374. }
  375. void r600_set_vddc3d_oorsdc(struct radeon_device *rdev, u32 s)
  376. {
  377. WREG32_P(CG_VDDC3D_OOR, SDC(s), ~SDC_MASK);
  378. }
  379. void r600_set_mpll_lock_time(struct radeon_device *rdev, u32 lock_time)
  380. {
  381. WREG32_P(MPLL_TIME, MPLL_LOCK_TIME(lock_time), ~MPLL_LOCK_TIME_MASK);
  382. }
  383. void r600_set_mpll_reset_time(struct radeon_device *rdev, u32 reset_time)
  384. {
  385. WREG32_P(MPLL_TIME, MPLL_RESET_TIME(reset_time), ~MPLL_RESET_TIME_MASK);
  386. }
  387. void r600_engine_clock_entry_enable(struct radeon_device *rdev,
  388. u32 index, bool enable)
  389. {
  390. if (enable)
  391. WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),
  392. STEP_0_SPLL_ENTRY_VALID, ~STEP_0_SPLL_ENTRY_VALID);
  393. else
  394. WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),
  395. 0, ~STEP_0_SPLL_ENTRY_VALID);
  396. }
  397. void r600_engine_clock_entry_enable_pulse_skipping(struct radeon_device *rdev,
  398. u32 index, bool enable)
  399. {
  400. if (enable)
  401. WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),
  402. STEP_0_SPLL_STEP_ENABLE, ~STEP_0_SPLL_STEP_ENABLE);
  403. else
  404. WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),
  405. 0, ~STEP_0_SPLL_STEP_ENABLE);
  406. }
  407. void r600_engine_clock_entry_enable_post_divider(struct radeon_device *rdev,
  408. u32 index, bool enable)
  409. {
  410. if (enable)
  411. WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),
  412. STEP_0_POST_DIV_EN, ~STEP_0_POST_DIV_EN);
  413. else
  414. WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),
  415. 0, ~STEP_0_POST_DIV_EN);
  416. }
  417. void r600_engine_clock_entry_set_post_divider(struct radeon_device *rdev,
  418. u32 index, u32 divider)
  419. {
  420. WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2),
  421. STEP_0_SPLL_POST_DIV(divider), ~STEP_0_SPLL_POST_DIV_MASK);
  422. }
  423. void r600_engine_clock_entry_set_reference_divider(struct radeon_device *rdev,
  424. u32 index, u32 divider)
  425. {
  426. WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2),
  427. STEP_0_SPLL_REF_DIV(divider), ~STEP_0_SPLL_REF_DIV_MASK);
  428. }
  429. void r600_engine_clock_entry_set_feedback_divider(struct radeon_device *rdev,
  430. u32 index, u32 divider)
  431. {
  432. WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2),
  433. STEP_0_SPLL_FB_DIV(divider), ~STEP_0_SPLL_FB_DIV_MASK);
  434. }
  435. void r600_engine_clock_entry_set_step_time(struct radeon_device *rdev,
  436. u32 index, u32 step_time)
  437. {
  438. WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2),
  439. STEP_0_SPLL_STEP_TIME(step_time), ~STEP_0_SPLL_STEP_TIME_MASK);
  440. }
  441. void r600_vid_rt_set_ssu(struct radeon_device *rdev, u32 u)
  442. {
  443. WREG32_P(VID_RT, SSTU(u), ~SSTU_MASK);
  444. }
  445. void r600_vid_rt_set_vru(struct radeon_device *rdev, u32 u)
  446. {
  447. WREG32_P(VID_RT, VID_CRTU(u), ~VID_CRTU_MASK);
  448. }
  449. void r600_vid_rt_set_vrt(struct radeon_device *rdev, u32 rt)
  450. {
  451. WREG32_P(VID_RT, VID_CRT(rt), ~VID_CRT_MASK);
  452. }
  453. void r600_voltage_control_enable_pins(struct radeon_device *rdev,
  454. u64 mask)
  455. {
  456. WREG32(LOWER_GPIO_ENABLE, mask & 0xffffffff);
  457. WREG32(UPPER_GPIO_ENABLE, upper_32_bits(mask));
  458. }
  459. void r600_voltage_control_program_voltages(struct radeon_device *rdev,
  460. enum r600_power_level index, u64 pins)
  461. {
  462. u32 tmp, mask;
  463. u32 ix = 3 - (3 & index);
  464. WREG32(CTXSW_VID_LOWER_GPIO_CNTL + (ix * 4), pins & 0xffffffff);
  465. mask = 7 << (3 * ix);
  466. tmp = RREG32(VID_UPPER_GPIO_CNTL);
  467. tmp = (tmp & ~mask) | ((pins >> (32 - (3 * ix))) & mask);
  468. WREG32(VID_UPPER_GPIO_CNTL, tmp);
  469. }
  470. void r600_voltage_control_deactivate_static_control(struct radeon_device *rdev,
  471. u64 mask)
  472. {
  473. u32 gpio;
  474. gpio = RREG32(GPIOPAD_MASK);
  475. gpio &= ~mask;
  476. WREG32(GPIOPAD_MASK, gpio);
  477. gpio = RREG32(GPIOPAD_EN);
  478. gpio &= ~mask;
  479. WREG32(GPIOPAD_EN, gpio);
  480. gpio = RREG32(GPIOPAD_A);
  481. gpio &= ~mask;
  482. WREG32(GPIOPAD_A, gpio);
  483. }
  484. void r600_power_level_enable(struct radeon_device *rdev,
  485. enum r600_power_level index, bool enable)
  486. {
  487. u32 ix = 3 - (3 & index);
  488. if (enable)
  489. WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), CTXSW_FREQ_STATE_ENABLE,
  490. ~CTXSW_FREQ_STATE_ENABLE);
  491. else
  492. WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), 0,
  493. ~CTXSW_FREQ_STATE_ENABLE);
  494. }
  495. void r600_power_level_set_voltage_index(struct radeon_device *rdev,
  496. enum r600_power_level index, u32 voltage_index)
  497. {
  498. u32 ix = 3 - (3 & index);
  499. WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4),
  500. CTXSW_FREQ_VIDS_CFG_INDEX(voltage_index), ~CTXSW_FREQ_VIDS_CFG_INDEX_MASK);
  501. }
  502. void r600_power_level_set_mem_clock_index(struct radeon_device *rdev,
  503. enum r600_power_level index, u32 mem_clock_index)
  504. {
  505. u32 ix = 3 - (3 & index);
  506. WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4),
  507. CTXSW_FREQ_MCLK_CFG_INDEX(mem_clock_index), ~CTXSW_FREQ_MCLK_CFG_INDEX_MASK);
  508. }
  509. void r600_power_level_set_eng_clock_index(struct radeon_device *rdev,
  510. enum r600_power_level index, u32 eng_clock_index)
  511. {
  512. u32 ix = 3 - (3 & index);
  513. WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4),
  514. CTXSW_FREQ_SCLK_CFG_INDEX(eng_clock_index), ~CTXSW_FREQ_SCLK_CFG_INDEX_MASK);
  515. }
  516. void r600_power_level_set_watermark_id(struct radeon_device *rdev,
  517. enum r600_power_level index,
  518. enum r600_display_watermark watermark_id)
  519. {
  520. u32 ix = 3 - (3 & index);
  521. u32 tmp = 0;
  522. if (watermark_id == R600_DISPLAY_WATERMARK_HIGH)
  523. tmp = CTXSW_FREQ_DISPLAY_WATERMARK;
  524. WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), tmp, ~CTXSW_FREQ_DISPLAY_WATERMARK);
  525. }
  526. void r600_power_level_set_pcie_gen2(struct radeon_device *rdev,
  527. enum r600_power_level index, bool compatible)
  528. {
  529. u32 ix = 3 - (3 & index);
  530. u32 tmp = 0;
  531. if (compatible)
  532. tmp = CTXSW_FREQ_GEN2PCIE_VOLT;
  533. WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), tmp, ~CTXSW_FREQ_GEN2PCIE_VOLT);
  534. }
  535. enum r600_power_level r600_power_level_get_current_index(struct radeon_device *rdev)
  536. {
  537. u32 tmp;
  538. tmp = RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK;
  539. tmp >>= CURRENT_PROFILE_INDEX_SHIFT;
  540. return tmp;
  541. }
  542. enum r600_power_level r600_power_level_get_target_index(struct radeon_device *rdev)
  543. {
  544. u32 tmp;
  545. tmp = RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & TARGET_PROFILE_INDEX_MASK;
  546. tmp >>= TARGET_PROFILE_INDEX_SHIFT;
  547. return tmp;
  548. }
  549. void r600_power_level_set_enter_index(struct radeon_device *rdev,
  550. enum r600_power_level index)
  551. {
  552. WREG32_P(TARGET_AND_CURRENT_PROFILE_INDEX, DYN_PWR_ENTER_INDEX(index),
  553. ~DYN_PWR_ENTER_INDEX_MASK);
  554. }
  555. void r600_wait_for_power_level_unequal(struct radeon_device *rdev,
  556. enum r600_power_level index)
  557. {
  558. int i;
  559. for (i = 0; i < rdev->usec_timeout; i++) {
  560. if (r600_power_level_get_target_index(rdev) != index)
  561. break;
  562. udelay(1);
  563. }
  564. for (i = 0; i < rdev->usec_timeout; i++) {
  565. if (r600_power_level_get_current_index(rdev) != index)
  566. break;
  567. udelay(1);
  568. }
  569. }
  570. void r600_wait_for_power_level(struct radeon_device *rdev,
  571. enum r600_power_level index)
  572. {
  573. int i;
  574. for (i = 0; i < rdev->usec_timeout; i++) {
  575. if (r600_power_level_get_target_index(rdev) == index)
  576. break;
  577. udelay(1);
  578. }
  579. for (i = 0; i < rdev->usec_timeout; i++) {
  580. if (r600_power_level_get_current_index(rdev) == index)
  581. break;
  582. udelay(1);
  583. }
  584. }
  585. void r600_start_dpm(struct radeon_device *rdev)
  586. {
  587. r600_enable_sclk_control(rdev, false);
  588. r600_enable_mclk_control(rdev, false);
  589. r600_dynamicpm_enable(rdev, true);
  590. radeon_wait_for_vblank(rdev, 0);
  591. radeon_wait_for_vblank(rdev, 1);
  592. r600_enable_spll_bypass(rdev, true);
  593. r600_wait_for_spll_change(rdev);
  594. r600_enable_spll_bypass(rdev, false);
  595. r600_wait_for_spll_change(rdev);
  596. r600_enable_spll_bypass(rdev, true);
  597. r600_wait_for_spll_change(rdev);
  598. r600_enable_spll_bypass(rdev, false);
  599. r600_wait_for_spll_change(rdev);
  600. r600_enable_sclk_control(rdev, true);
  601. r600_enable_mclk_control(rdev, true);
  602. }
  603. void r600_stop_dpm(struct radeon_device *rdev)
  604. {
  605. r600_dynamicpm_enable(rdev, false);
  606. }
  607. int r600_dpm_pre_set_power_state(struct radeon_device *rdev)
  608. {
  609. return 0;
  610. }
  611. void r600_dpm_post_set_power_state(struct radeon_device *rdev)
  612. {
  613. }
  614. bool r600_is_uvd_state(u32 class, u32 class2)
  615. {
  616. if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
  617. return true;
  618. if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
  619. return true;
  620. if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
  621. return true;
  622. if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
  623. return true;
  624. if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
  625. return true;
  626. return false;
  627. }
  628. static int r600_set_thermal_temperature_range(struct radeon_device *rdev,
  629. int min_temp, int max_temp)
  630. {
  631. int low_temp = 0 * 1000;
  632. int high_temp = 255 * 1000;
  633. if (low_temp < min_temp)
  634. low_temp = min_temp;
  635. if (high_temp > max_temp)
  636. high_temp = max_temp;
  637. if (high_temp < low_temp) {
  638. DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
  639. return -EINVAL;
  640. }
  641. WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
  642. WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
  643. WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
  644. rdev->pm.dpm.thermal.min_temp = low_temp;
  645. rdev->pm.dpm.thermal.max_temp = high_temp;
  646. return 0;
  647. }
  648. bool r600_is_internal_thermal_sensor(enum radeon_int_thermal_type sensor)
  649. {
  650. switch (sensor) {
  651. case THERMAL_TYPE_RV6XX:
  652. case THERMAL_TYPE_RV770:
  653. case THERMAL_TYPE_EVERGREEN:
  654. case THERMAL_TYPE_SUMO:
  655. case THERMAL_TYPE_NI:
  656. case THERMAL_TYPE_SI:
  657. case THERMAL_TYPE_CI:
  658. case THERMAL_TYPE_KV:
  659. return true;
  660. case THERMAL_TYPE_ADT7473_WITH_INTERNAL:
  661. case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
  662. return false; /* need special handling */
  663. case THERMAL_TYPE_NONE:
  664. case THERMAL_TYPE_EXTERNAL:
  665. case THERMAL_TYPE_EXTERNAL_GPIO:
  666. default:
  667. return false;
  668. }
  669. }
  670. int r600_dpm_late_enable(struct radeon_device *rdev)
  671. {
  672. int ret;
  673. if (rdev->irq.installed &&
  674. r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
  675. ret = r600_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
  676. if (ret)
  677. return ret;
  678. rdev->irq.dpm_thermal = true;
  679. radeon_irq_set(rdev);
  680. }
  681. return 0;
  682. }
  683. union power_info {
  684. struct _ATOM_POWERPLAY_INFO info;
  685. struct _ATOM_POWERPLAY_INFO_V2 info_2;
  686. struct _ATOM_POWERPLAY_INFO_V3 info_3;
  687. struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
  688. struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
  689. struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
  690. struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4;
  691. struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5;
  692. };
  693. union fan_info {
  694. struct _ATOM_PPLIB_FANTABLE fan;
  695. struct _ATOM_PPLIB_FANTABLE2 fan2;
  696. struct _ATOM_PPLIB_FANTABLE3 fan3;
  697. };
  698. static int r600_parse_clk_voltage_dep_table(struct radeon_clock_voltage_dependency_table *radeon_table,
  699. ATOM_PPLIB_Clock_Voltage_Dependency_Table *atom_table)
  700. {
  701. u32 size = atom_table->ucNumEntries *
  702. sizeof(struct radeon_clock_voltage_dependency_entry);
  703. int i;
  704. ATOM_PPLIB_Clock_Voltage_Dependency_Record *entry;
  705. radeon_table->entries = kzalloc(size, GFP_KERNEL);
  706. if (!radeon_table->entries)
  707. return -ENOMEM;
  708. entry = &atom_table->entries[0];
  709. for (i = 0; i < atom_table->ucNumEntries; i++) {
  710. radeon_table->entries[i].clk = le16_to_cpu(entry->usClockLow) |
  711. (entry->ucClockHigh << 16);
  712. radeon_table->entries[i].v = le16_to_cpu(entry->usVoltage);
  713. entry = (ATOM_PPLIB_Clock_Voltage_Dependency_Record *)
  714. ((u8 *)entry + sizeof(ATOM_PPLIB_Clock_Voltage_Dependency_Record));
  715. }
  716. radeon_table->count = atom_table->ucNumEntries;
  717. return 0;
  718. }
  719. int r600_get_platform_caps(struct radeon_device *rdev)
  720. {
  721. struct radeon_mode_info *mode_info = &rdev->mode_info;
  722. union power_info *power_info;
  723. int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
  724. u16 data_offset;
  725. u8 frev, crev;
  726. if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
  727. &frev, &crev, &data_offset))
  728. return -EINVAL;
  729. power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
  730. rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps);
  731. rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
  732. rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime);
  733. return 0;
  734. }
  735. /* sizeof(ATOM_PPLIB_EXTENDEDHEADER) */
  736. #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 12
  737. #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 14
  738. #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 16
  739. #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 18
  740. #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 20
  741. #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 22
  742. int r600_parse_extended_power_table(struct radeon_device *rdev)
  743. {
  744. struct radeon_mode_info *mode_info = &rdev->mode_info;
  745. union power_info *power_info;
  746. union fan_info *fan_info;
  747. ATOM_PPLIB_Clock_Voltage_Dependency_Table *dep_table;
  748. int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
  749. u16 data_offset;
  750. u8 frev, crev;
  751. int ret, i;
  752. if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
  753. &frev, &crev, &data_offset))
  754. return -EINVAL;
  755. power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
  756. /* fan table */
  757. if (le16_to_cpu(power_info->pplib.usTableSize) >=
  758. sizeof(struct _ATOM_PPLIB_POWERPLAYTABLE3)) {
  759. if (power_info->pplib3.usFanTableOffset) {
  760. fan_info = (union fan_info *)(mode_info->atom_context->bios + data_offset +
  761. le16_to_cpu(power_info->pplib3.usFanTableOffset));
  762. rdev->pm.dpm.fan.t_hyst = fan_info->fan.ucTHyst;
  763. rdev->pm.dpm.fan.t_min = le16_to_cpu(fan_info->fan.usTMin);
  764. rdev->pm.dpm.fan.t_med = le16_to_cpu(fan_info->fan.usTMed);
  765. rdev->pm.dpm.fan.t_high = le16_to_cpu(fan_info->fan.usTHigh);
  766. rdev->pm.dpm.fan.pwm_min = le16_to_cpu(fan_info->fan.usPWMMin);
  767. rdev->pm.dpm.fan.pwm_med = le16_to_cpu(fan_info->fan.usPWMMed);
  768. rdev->pm.dpm.fan.pwm_high = le16_to_cpu(fan_info->fan.usPWMHigh);
  769. if (fan_info->fan.ucFanTableFormat >= 2)
  770. rdev->pm.dpm.fan.t_max = le16_to_cpu(fan_info->fan2.usTMax);
  771. else
  772. rdev->pm.dpm.fan.t_max = 10900;
  773. rdev->pm.dpm.fan.cycle_delay = 100000;
  774. if (fan_info->fan.ucFanTableFormat >= 3) {
  775. rdev->pm.dpm.fan.control_mode = fan_info->fan3.ucFanControlMode;
  776. rdev->pm.dpm.fan.default_max_fan_pwm =
  777. le16_to_cpu(fan_info->fan3.usFanPWMMax);
  778. rdev->pm.dpm.fan.default_fan_output_sensitivity = 4836;
  779. rdev->pm.dpm.fan.fan_output_sensitivity =
  780. le16_to_cpu(fan_info->fan3.usFanOutputSensitivity);
  781. }
  782. rdev->pm.dpm.fan.ucode_fan_control = true;
  783. }
  784. }
  785. /* clock dependancy tables, shedding tables */
  786. if (le16_to_cpu(power_info->pplib.usTableSize) >=
  787. sizeof(struct _ATOM_PPLIB_POWERPLAYTABLE4)) {
  788. if (power_info->pplib4.usVddcDependencyOnSCLKOffset) {
  789. dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)
  790. (mode_info->atom_context->bios + data_offset +
  791. le16_to_cpu(power_info->pplib4.usVddcDependencyOnSCLKOffset));
  792. ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
  793. dep_table);
  794. if (ret)
  795. return ret;
  796. }
  797. if (power_info->pplib4.usVddciDependencyOnMCLKOffset) {
  798. dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)
  799. (mode_info->atom_context->bios + data_offset +
  800. le16_to_cpu(power_info->pplib4.usVddciDependencyOnMCLKOffset));
  801. ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
  802. dep_table);
  803. if (ret) {
  804. kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries);
  805. return ret;
  806. }
  807. }
  808. if (power_info->pplib4.usVddcDependencyOnMCLKOffset) {
  809. dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)
  810. (mode_info->atom_context->bios + data_offset +
  811. le16_to_cpu(power_info->pplib4.usVddcDependencyOnMCLKOffset));
  812. ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
  813. dep_table);
  814. if (ret) {
  815. kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries);
  816. kfree(rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries);
  817. return ret;
  818. }
  819. }
  820. if (power_info->pplib4.usMvddDependencyOnMCLKOffset) {
  821. dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)
  822. (mode_info->atom_context->bios + data_offset +
  823. le16_to_cpu(power_info->pplib4.usMvddDependencyOnMCLKOffset));
  824. ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
  825. dep_table);
  826. if (ret) {
  827. kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries);
  828. kfree(rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries);
  829. kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries);
  830. return ret;
  831. }
  832. }
  833. if (power_info->pplib4.usMaxClockVoltageOnDCOffset) {
  834. ATOM_PPLIB_Clock_Voltage_Limit_Table *clk_v =
  835. (ATOM_PPLIB_Clock_Voltage_Limit_Table *)
  836. (mode_info->atom_context->bios + data_offset +
  837. le16_to_cpu(power_info->pplib4.usMaxClockVoltageOnDCOffset));
  838. if (clk_v->ucNumEntries) {
  839. rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk =
  840. le16_to_cpu(clk_v->entries[0].usSclkLow) |
  841. (clk_v->entries[0].ucSclkHigh << 16);
  842. rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk =
  843. le16_to_cpu(clk_v->entries[0].usMclkLow) |
  844. (clk_v->entries[0].ucMclkHigh << 16);
  845. rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc =
  846. le16_to_cpu(clk_v->entries[0].usVddc);
  847. rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddci =
  848. le16_to_cpu(clk_v->entries[0].usVddci);
  849. }
  850. }
  851. if (power_info->pplib4.usVddcPhaseShedLimitsTableOffset) {
  852. ATOM_PPLIB_PhaseSheddingLimits_Table *psl =
  853. (ATOM_PPLIB_PhaseSheddingLimits_Table *)
  854. (mode_info->atom_context->bios + data_offset +
  855. le16_to_cpu(power_info->pplib4.usVddcPhaseShedLimitsTableOffset));
  856. ATOM_PPLIB_PhaseSheddingLimits_Record *entry;
  857. rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries =
  858. kcalloc(psl->ucNumEntries,
  859. sizeof(struct radeon_phase_shedding_limits_entry),
  860. GFP_KERNEL);
  861. if (!rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries) {
  862. r600_free_extended_power_table(rdev);
  863. return -ENOMEM;
  864. }
  865. entry = &psl->entries[0];
  866. for (i = 0; i < psl->ucNumEntries; i++) {
  867. rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].sclk =
  868. le16_to_cpu(entry->usSclkLow) | (entry->ucSclkHigh << 16);
  869. rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].mclk =
  870. le16_to_cpu(entry->usMclkLow) | (entry->ucMclkHigh << 16);
  871. rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].voltage =
  872. le16_to_cpu(entry->usVoltage);
  873. entry = (ATOM_PPLIB_PhaseSheddingLimits_Record *)
  874. ((u8 *)entry + sizeof(ATOM_PPLIB_PhaseSheddingLimits_Record));
  875. }
  876. rdev->pm.dpm.dyn_state.phase_shedding_limits_table.count =
  877. psl->ucNumEntries;
  878. }
  879. }
  880. /* cac data */
  881. if (le16_to_cpu(power_info->pplib.usTableSize) >=
  882. sizeof(struct _ATOM_PPLIB_POWERPLAYTABLE5)) {
  883. rdev->pm.dpm.tdp_limit = le32_to_cpu(power_info->pplib5.ulTDPLimit);
  884. rdev->pm.dpm.near_tdp_limit = le32_to_cpu(power_info->pplib5.ulNearTDPLimit);
  885. rdev->pm.dpm.near_tdp_limit_adjusted = rdev->pm.dpm.near_tdp_limit;
  886. rdev->pm.dpm.tdp_od_limit = le16_to_cpu(power_info->pplib5.usTDPODLimit);
  887. if (rdev->pm.dpm.tdp_od_limit)
  888. rdev->pm.dpm.power_control = true;
  889. else
  890. rdev->pm.dpm.power_control = false;
  891. rdev->pm.dpm.tdp_adjustment = 0;
  892. rdev->pm.dpm.sq_ramping_threshold = le32_to_cpu(power_info->pplib5.ulSQRampingThreshold);
  893. rdev->pm.dpm.cac_leakage = le32_to_cpu(power_info->pplib5.ulCACLeakage);
  894. rdev->pm.dpm.load_line_slope = le16_to_cpu(power_info->pplib5.usLoadLineSlope);
  895. if (power_info->pplib5.usCACLeakageTableOffset) {
  896. ATOM_PPLIB_CAC_Leakage_Table *cac_table =
  897. (ATOM_PPLIB_CAC_Leakage_Table *)
  898. (mode_info->atom_context->bios + data_offset +
  899. le16_to_cpu(power_info->pplib5.usCACLeakageTableOffset));
  900. ATOM_PPLIB_CAC_Leakage_Record *entry;
  901. u32 size = cac_table->ucNumEntries * sizeof(struct radeon_cac_leakage_table);
  902. rdev->pm.dpm.dyn_state.cac_leakage_table.entries = kzalloc(size, GFP_KERNEL);
  903. if (!rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
  904. r600_free_extended_power_table(rdev);
  905. return -ENOMEM;
  906. }
  907. entry = &cac_table->entries[0];
  908. for (i = 0; i < cac_table->ucNumEntries; i++) {
  909. if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
  910. rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1 =
  911. le16_to_cpu(entry->usVddc1);
  912. rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2 =
  913. le16_to_cpu(entry->usVddc2);
  914. rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3 =
  915. le16_to_cpu(entry->usVddc3);
  916. } else {
  917. rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc =
  918. le16_to_cpu(entry->usVddc);
  919. rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage =
  920. le32_to_cpu(entry->ulLeakageValue);
  921. }
  922. entry = (ATOM_PPLIB_CAC_Leakage_Record *)
  923. ((u8 *)entry + sizeof(ATOM_PPLIB_CAC_Leakage_Record));
  924. }
  925. rdev->pm.dpm.dyn_state.cac_leakage_table.count = cac_table->ucNumEntries;
  926. }
  927. }
  928. /* ext tables */
  929. if (le16_to_cpu(power_info->pplib.usTableSize) >=
  930. sizeof(struct _ATOM_PPLIB_POWERPLAYTABLE3)) {
  931. ATOM_PPLIB_EXTENDEDHEADER *ext_hdr = (ATOM_PPLIB_EXTENDEDHEADER *)
  932. (mode_info->atom_context->bios + data_offset +
  933. le16_to_cpu(power_info->pplib3.usExtendendedHeaderOffset));
  934. if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2) &&
  935. ext_hdr->usVCETableOffset) {
  936. VCEClockInfoArray *array = (VCEClockInfoArray *)
  937. (mode_info->atom_context->bios + data_offset +
  938. le16_to_cpu(ext_hdr->usVCETableOffset) + 1);
  939. ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *limits =
  940. (ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *)
  941. (mode_info->atom_context->bios + data_offset +
  942. le16_to_cpu(ext_hdr->usVCETableOffset) + 1 +
  943. 1 + array->ucNumEntries * sizeof(VCEClockInfo));
  944. ATOM_PPLIB_VCE_State_Table *states =
  945. (ATOM_PPLIB_VCE_State_Table *)
  946. (mode_info->atom_context->bios + data_offset +
  947. le16_to_cpu(ext_hdr->usVCETableOffset) + 1 +
  948. 1 + (array->ucNumEntries * sizeof (VCEClockInfo)) +
  949. 1 + (limits->numEntries * sizeof(ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record)));
  950. ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record *entry;
  951. ATOM_PPLIB_VCE_State_Record *state_entry;
  952. VCEClockInfo *vce_clk;
  953. u32 size = limits->numEntries *
  954. sizeof(struct radeon_vce_clock_voltage_dependency_entry);
  955. rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries =
  956. kzalloc(size, GFP_KERNEL);
  957. if (!rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries) {
  958. r600_free_extended_power_table(rdev);
  959. return -ENOMEM;
  960. }
  961. rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count =
  962. limits->numEntries;
  963. entry = &limits->entries[0];
  964. state_entry = &states->entries[0];
  965. for (i = 0; i < limits->numEntries; i++) {
  966. vce_clk = (VCEClockInfo *)
  967. ((u8 *)&array->entries[0] +
  968. (entry->ucVCEClockInfoIndex * sizeof(VCEClockInfo)));
  969. rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].evclk =
  970. le16_to_cpu(vce_clk->usEVClkLow) | (vce_clk->ucEVClkHigh << 16);
  971. rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].ecclk =
  972. le16_to_cpu(vce_clk->usECClkLow) | (vce_clk->ucECClkHigh << 16);
  973. rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v =
  974. le16_to_cpu(entry->usVoltage);
  975. entry = (ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record *)
  976. ((u8 *)entry + sizeof(ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record));
  977. }
  978. for (i = 0; i < states->numEntries; i++) {
  979. if (i >= RADEON_MAX_VCE_LEVELS)
  980. break;
  981. vce_clk = (VCEClockInfo *)
  982. ((u8 *)&array->entries[0] +
  983. (state_entry->ucVCEClockInfoIndex * sizeof(VCEClockInfo)));
  984. rdev->pm.dpm.vce_states[i].evclk =
  985. le16_to_cpu(vce_clk->usEVClkLow) | (vce_clk->ucEVClkHigh << 16);
  986. rdev->pm.dpm.vce_states[i].ecclk =
  987. le16_to_cpu(vce_clk->usECClkLow) | (vce_clk->ucECClkHigh << 16);
  988. rdev->pm.dpm.vce_states[i].clk_idx =
  989. state_entry->ucClockInfoIndex & 0x3f;
  990. rdev->pm.dpm.vce_states[i].pstate =
  991. (state_entry->ucClockInfoIndex & 0xc0) >> 6;
  992. state_entry = (ATOM_PPLIB_VCE_State_Record *)
  993. ((u8 *)state_entry + sizeof(ATOM_PPLIB_VCE_State_Record));
  994. }
  995. }
  996. if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3) &&
  997. ext_hdr->usUVDTableOffset) {
  998. UVDClockInfoArray *array = (UVDClockInfoArray *)
  999. (mode_info->atom_context->bios + data_offset +
  1000. le16_to_cpu(ext_hdr->usUVDTableOffset) + 1);
  1001. ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table *limits =
  1002. (ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table *)
  1003. (mode_info->atom_context->bios + data_offset +
  1004. le16_to_cpu(ext_hdr->usUVDTableOffset) + 1 +
  1005. 1 + (array->ucNumEntries * sizeof (UVDClockInfo)));
  1006. ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record *entry;
  1007. u32 size = limits->numEntries *
  1008. sizeof(struct radeon_uvd_clock_voltage_dependency_entry);
  1009. rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries =
  1010. kzalloc(size, GFP_KERNEL);
  1011. if (!rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries) {
  1012. r600_free_extended_power_table(rdev);
  1013. return -ENOMEM;
  1014. }
  1015. rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count =
  1016. limits->numEntries;
  1017. entry = &limits->entries[0];
  1018. for (i = 0; i < limits->numEntries; i++) {
  1019. UVDClockInfo *uvd_clk = (UVDClockInfo *)
  1020. ((u8 *)&array->entries[0] +
  1021. (entry->ucUVDClockInfoIndex * sizeof(UVDClockInfo)));
  1022. rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].vclk =
  1023. le16_to_cpu(uvd_clk->usVClkLow) | (uvd_clk->ucVClkHigh << 16);
  1024. rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].dclk =
  1025. le16_to_cpu(uvd_clk->usDClkLow) | (uvd_clk->ucDClkHigh << 16);
  1026. rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v =
  1027. le16_to_cpu(entry->usVoltage);
  1028. entry = (ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record *)
  1029. ((u8 *)entry + sizeof(ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record));
  1030. }
  1031. }
  1032. if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4) &&
  1033. ext_hdr->usSAMUTableOffset) {
  1034. ATOM_PPLIB_SAMClk_Voltage_Limit_Table *limits =
  1035. (ATOM_PPLIB_SAMClk_Voltage_Limit_Table *)
  1036. (mode_info->atom_context->bios + data_offset +
  1037. le16_to_cpu(ext_hdr->usSAMUTableOffset) + 1);
  1038. ATOM_PPLIB_SAMClk_Voltage_Limit_Record *entry;
  1039. u32 size = limits->numEntries *
  1040. sizeof(struct radeon_clock_voltage_dependency_entry);
  1041. rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries =
  1042. kzalloc(size, GFP_KERNEL);
  1043. if (!rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries) {
  1044. r600_free_extended_power_table(rdev);
  1045. return -ENOMEM;
  1046. }
  1047. rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count =
  1048. limits->numEntries;
  1049. entry = &limits->entries[0];
  1050. for (i = 0; i < limits->numEntries; i++) {
  1051. rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].clk =
  1052. le16_to_cpu(entry->usSAMClockLow) | (entry->ucSAMClockHigh << 16);
  1053. rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v =
  1054. le16_to_cpu(entry->usVoltage);
  1055. entry = (ATOM_PPLIB_SAMClk_Voltage_Limit_Record *)
  1056. ((u8 *)entry + sizeof(ATOM_PPLIB_SAMClk_Voltage_Limit_Record));
  1057. }
  1058. }
  1059. if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5) &&
  1060. ext_hdr->usPPMTableOffset) {
  1061. ATOM_PPLIB_PPM_Table *ppm = (ATOM_PPLIB_PPM_Table *)
  1062. (mode_info->atom_context->bios + data_offset +
  1063. le16_to_cpu(ext_hdr->usPPMTableOffset));
  1064. rdev->pm.dpm.dyn_state.ppm_table =
  1065. kzalloc(sizeof(struct radeon_ppm_table), GFP_KERNEL);
  1066. if (!rdev->pm.dpm.dyn_state.ppm_table) {
  1067. r600_free_extended_power_table(rdev);
  1068. return -ENOMEM;
  1069. }
  1070. rdev->pm.dpm.dyn_state.ppm_table->ppm_design = ppm->ucPpmDesign;
  1071. rdev->pm.dpm.dyn_state.ppm_table->cpu_core_number =
  1072. le16_to_cpu(ppm->usCpuCoreNumber);
  1073. rdev->pm.dpm.dyn_state.ppm_table->platform_tdp =
  1074. le32_to_cpu(ppm->ulPlatformTDP);
  1075. rdev->pm.dpm.dyn_state.ppm_table->small_ac_platform_tdp =
  1076. le32_to_cpu(ppm->ulSmallACPlatformTDP);
  1077. rdev->pm.dpm.dyn_state.ppm_table->platform_tdc =
  1078. le32_to_cpu(ppm->ulPlatformTDC);
  1079. rdev->pm.dpm.dyn_state.ppm_table->small_ac_platform_tdc =
  1080. le32_to_cpu(ppm->ulSmallACPlatformTDC);
  1081. rdev->pm.dpm.dyn_state.ppm_table->apu_tdp =
  1082. le32_to_cpu(ppm->ulApuTDP);
  1083. rdev->pm.dpm.dyn_state.ppm_table->dgpu_tdp =
  1084. le32_to_cpu(ppm->ulDGpuTDP);
  1085. rdev->pm.dpm.dyn_state.ppm_table->dgpu_ulv_power =
  1086. le32_to_cpu(ppm->ulDGpuUlvPower);
  1087. rdev->pm.dpm.dyn_state.ppm_table->tj_max =
  1088. le32_to_cpu(ppm->ulTjmax);
  1089. }
  1090. if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6) &&
  1091. ext_hdr->usACPTableOffset) {
  1092. ATOM_PPLIB_ACPClk_Voltage_Limit_Table *limits =
  1093. (ATOM_PPLIB_ACPClk_Voltage_Limit_Table *)
  1094. (mode_info->atom_context->bios + data_offset +
  1095. le16_to_cpu(ext_hdr->usACPTableOffset) + 1);
  1096. ATOM_PPLIB_ACPClk_Voltage_Limit_Record *entry;
  1097. u32 size = limits->numEntries *
  1098. sizeof(struct radeon_clock_voltage_dependency_entry);
  1099. rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries =
  1100. kzalloc(size, GFP_KERNEL);
  1101. if (!rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries) {
  1102. r600_free_extended_power_table(rdev);
  1103. return -ENOMEM;
  1104. }
  1105. rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count =
  1106. limits->numEntries;
  1107. entry = &limits->entries[0];
  1108. for (i = 0; i < limits->numEntries; i++) {
  1109. rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].clk =
  1110. le16_to_cpu(entry->usACPClockLow) | (entry->ucACPClockHigh << 16);
  1111. rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v =
  1112. le16_to_cpu(entry->usVoltage);
  1113. entry = (ATOM_PPLIB_ACPClk_Voltage_Limit_Record *)
  1114. ((u8 *)entry + sizeof(ATOM_PPLIB_ACPClk_Voltage_Limit_Record));
  1115. }
  1116. }
  1117. if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7) &&
  1118. ext_hdr->usPowerTuneTableOffset) {
  1119. u8 rev = *(u8 *)(mode_info->atom_context->bios + data_offset +
  1120. le16_to_cpu(ext_hdr->usPowerTuneTableOffset));
  1121. ATOM_PowerTune_Table *pt;
  1122. rdev->pm.dpm.dyn_state.cac_tdp_table =
  1123. kzalloc(sizeof(struct radeon_cac_tdp_table), GFP_KERNEL);
  1124. if (!rdev->pm.dpm.dyn_state.cac_tdp_table) {
  1125. r600_free_extended_power_table(rdev);
  1126. return -ENOMEM;
  1127. }
  1128. if (rev > 0) {
  1129. ATOM_PPLIB_POWERTUNE_Table_V1 *ppt = (ATOM_PPLIB_POWERTUNE_Table_V1 *)
  1130. (mode_info->atom_context->bios + data_offset +
  1131. le16_to_cpu(ext_hdr->usPowerTuneTableOffset));
  1132. rdev->pm.dpm.dyn_state.cac_tdp_table->maximum_power_delivery_limit =
  1133. le16_to_cpu(ppt->usMaximumPowerDeliveryLimit);
  1134. pt = &ppt->power_tune_table;
  1135. } else {
  1136. ATOM_PPLIB_POWERTUNE_Table *ppt = (ATOM_PPLIB_POWERTUNE_Table *)
  1137. (mode_info->atom_context->bios + data_offset +
  1138. le16_to_cpu(ext_hdr->usPowerTuneTableOffset));
  1139. rdev->pm.dpm.dyn_state.cac_tdp_table->maximum_power_delivery_limit = 255;
  1140. pt = &ppt->power_tune_table;
  1141. }
  1142. rdev->pm.dpm.dyn_state.cac_tdp_table->tdp = le16_to_cpu(pt->usTDP);
  1143. rdev->pm.dpm.dyn_state.cac_tdp_table->configurable_tdp =
  1144. le16_to_cpu(pt->usConfigurableTDP);
  1145. rdev->pm.dpm.dyn_state.cac_tdp_table->tdc = le16_to_cpu(pt->usTDC);
  1146. rdev->pm.dpm.dyn_state.cac_tdp_table->battery_power_limit =
  1147. le16_to_cpu(pt->usBatteryPowerLimit);
  1148. rdev->pm.dpm.dyn_state.cac_tdp_table->small_power_limit =
  1149. le16_to_cpu(pt->usSmallPowerLimit);
  1150. rdev->pm.dpm.dyn_state.cac_tdp_table->low_cac_leakage =
  1151. le16_to_cpu(pt->usLowCACLeakage);
  1152. rdev->pm.dpm.dyn_state.cac_tdp_table->high_cac_leakage =
  1153. le16_to_cpu(pt->usHighCACLeakage);
  1154. }
  1155. }
  1156. return 0;
  1157. }
  1158. void r600_free_extended_power_table(struct radeon_device *rdev)
  1159. {
  1160. struct radeon_dpm_dynamic_state *dyn_state = &rdev->pm.dpm.dyn_state;
  1161. kfree(dyn_state->vddc_dependency_on_sclk.entries);
  1162. kfree(dyn_state->vddci_dependency_on_mclk.entries);
  1163. kfree(dyn_state->vddc_dependency_on_mclk.entries);
  1164. kfree(dyn_state->mvdd_dependency_on_mclk.entries);
  1165. kfree(dyn_state->cac_leakage_table.entries);
  1166. kfree(dyn_state->phase_shedding_limits_table.entries);
  1167. kfree(dyn_state->ppm_table);
  1168. kfree(dyn_state->cac_tdp_table);
  1169. kfree(dyn_state->vce_clock_voltage_dependency_table.entries);
  1170. kfree(dyn_state->uvd_clock_voltage_dependency_table.entries);
  1171. kfree(dyn_state->samu_clock_voltage_dependency_table.entries);
  1172. kfree(dyn_state->acp_clock_voltage_dependency_table.entries);
  1173. }
  1174. enum radeon_pcie_gen r600_get_pcie_gen_support(struct radeon_device *rdev,
  1175. u32 sys_mask,
  1176. enum radeon_pcie_gen asic_gen,
  1177. enum radeon_pcie_gen default_gen)
  1178. {
  1179. switch (asic_gen) {
  1180. case RADEON_PCIE_GEN1:
  1181. return RADEON_PCIE_GEN1;
  1182. case RADEON_PCIE_GEN2:
  1183. return RADEON_PCIE_GEN2;
  1184. case RADEON_PCIE_GEN3:
  1185. return RADEON_PCIE_GEN3;
  1186. default:
  1187. if ((sys_mask & RADEON_PCIE_SPEED_80) && (default_gen == RADEON_PCIE_GEN3))
  1188. return RADEON_PCIE_GEN3;
  1189. else if ((sys_mask & RADEON_PCIE_SPEED_50) && (default_gen == RADEON_PCIE_GEN2))
  1190. return RADEON_PCIE_GEN2;
  1191. else
  1192. return RADEON_PCIE_GEN1;
  1193. }
  1194. return RADEON_PCIE_GEN1;
  1195. }
  1196. u16 r600_get_pcie_lane_support(struct radeon_device *rdev,
  1197. u16 asic_lanes,
  1198. u16 default_lanes)
  1199. {
  1200. switch (asic_lanes) {
  1201. case 0:
  1202. default:
  1203. return default_lanes;
  1204. case 1:
  1205. return 1;
  1206. case 2:
  1207. return 2;
  1208. case 4:
  1209. return 4;
  1210. case 8:
  1211. return 8;
  1212. case 12:
  1213. return 12;
  1214. case 16:
  1215. return 16;
  1216. }
  1217. }
  1218. u8 r600_encode_pci_lane_width(u32 lanes)
  1219. {
  1220. u8 encoded_lanes[] = { 0, 1, 2, 0, 3, 0, 0, 0, 4, 0, 0, 0, 5, 0, 0, 0, 6 };
  1221. if (lanes > 16)
  1222. return 0;
  1223. return encoded_lanes[lanes];
  1224. }