nv84_fence.c 6.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224
  1. /*
  2. * Copyright 2012 Red Hat Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Ben Skeggs
  23. */
  24. #include "nouveau_drv.h"
  25. #include "nouveau_dma.h"
  26. #include "nouveau_fence.h"
  27. #include "nouveau_vmm.h"
  28. #include "nv50_display.h"
  29. static int
  30. nv84_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
  31. {
  32. int ret = RING_SPACE(chan, 8);
  33. if (ret == 0) {
  34. BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
  35. OUT_RING (chan, chan->vram.handle);
  36. BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 5);
  37. OUT_RING (chan, upper_32_bits(virtual));
  38. OUT_RING (chan, lower_32_bits(virtual));
  39. OUT_RING (chan, sequence);
  40. OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
  41. OUT_RING (chan, 0x00000000);
  42. FIRE_RING (chan);
  43. }
  44. return ret;
  45. }
  46. static int
  47. nv84_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
  48. {
  49. int ret = RING_SPACE(chan, 7);
  50. if (ret == 0) {
  51. BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
  52. OUT_RING (chan, chan->vram.handle);
  53. BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
  54. OUT_RING (chan, upper_32_bits(virtual));
  55. OUT_RING (chan, lower_32_bits(virtual));
  56. OUT_RING (chan, sequence);
  57. OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL);
  58. FIRE_RING (chan);
  59. }
  60. return ret;
  61. }
  62. static int
  63. nv84_fence_emit(struct nouveau_fence *fence)
  64. {
  65. struct nouveau_channel *chan = fence->channel;
  66. struct nv84_fence_chan *fctx = chan->fence;
  67. u64 addr = fctx->vma->addr + chan->chid * 16;
  68. return fctx->base.emit32(chan, addr, fence->base.seqno);
  69. }
  70. static int
  71. nv84_fence_sync(struct nouveau_fence *fence,
  72. struct nouveau_channel *prev, struct nouveau_channel *chan)
  73. {
  74. struct nv84_fence_chan *fctx = chan->fence;
  75. u64 addr = fctx->vma->addr + prev->chid * 16;
  76. return fctx->base.sync32(chan, addr, fence->base.seqno);
  77. }
  78. static u32
  79. nv84_fence_read(struct nouveau_channel *chan)
  80. {
  81. struct nv84_fence_priv *priv = chan->drm->fence;
  82. return nouveau_bo_rd32(priv->bo, chan->chid * 16/4);
  83. }
  84. static void
  85. nv84_fence_context_del(struct nouveau_channel *chan)
  86. {
  87. struct nv84_fence_priv *priv = chan->drm->fence;
  88. struct nv84_fence_chan *fctx = chan->fence;
  89. nouveau_bo_wr32(priv->bo, chan->chid * 16 / 4, fctx->base.sequence);
  90. mutex_lock(&priv->mutex);
  91. nouveau_vma_del(&fctx->vma);
  92. mutex_unlock(&priv->mutex);
  93. nouveau_fence_context_del(&fctx->base);
  94. chan->fence = NULL;
  95. nouveau_fence_context_free(&fctx->base);
  96. }
  97. int
  98. nv84_fence_context_new(struct nouveau_channel *chan)
  99. {
  100. struct nouveau_cli *cli = (void *)chan->user.client;
  101. struct nv84_fence_priv *priv = chan->drm->fence;
  102. struct nv84_fence_chan *fctx;
  103. int ret;
  104. fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
  105. if (!fctx)
  106. return -ENOMEM;
  107. nouveau_fence_context_new(chan, &fctx->base);
  108. fctx->base.emit = nv84_fence_emit;
  109. fctx->base.sync = nv84_fence_sync;
  110. fctx->base.read = nv84_fence_read;
  111. fctx->base.emit32 = nv84_fence_emit32;
  112. fctx->base.sync32 = nv84_fence_sync32;
  113. fctx->base.sequence = nv84_fence_read(chan);
  114. mutex_lock(&priv->mutex);
  115. ret = nouveau_vma_new(priv->bo, &cli->vmm, &fctx->vma);
  116. mutex_unlock(&priv->mutex);
  117. if (ret)
  118. nv84_fence_context_del(chan);
  119. return ret;
  120. }
  121. static bool
  122. nv84_fence_suspend(struct nouveau_drm *drm)
  123. {
  124. struct nv84_fence_priv *priv = drm->fence;
  125. int i;
  126. priv->suspend = vmalloc(array_size(sizeof(u32), drm->chan.nr));
  127. if (priv->suspend) {
  128. for (i = 0; i < drm->chan.nr; i++)
  129. priv->suspend[i] = nouveau_bo_rd32(priv->bo, i*4);
  130. }
  131. return priv->suspend != NULL;
  132. }
  133. static void
  134. nv84_fence_resume(struct nouveau_drm *drm)
  135. {
  136. struct nv84_fence_priv *priv = drm->fence;
  137. int i;
  138. if (priv->suspend) {
  139. for (i = 0; i < drm->chan.nr; i++)
  140. nouveau_bo_wr32(priv->bo, i*4, priv->suspend[i]);
  141. vfree(priv->suspend);
  142. priv->suspend = NULL;
  143. }
  144. }
  145. static void
  146. nv84_fence_destroy(struct nouveau_drm *drm)
  147. {
  148. struct nv84_fence_priv *priv = drm->fence;
  149. nouveau_bo_unmap(priv->bo);
  150. if (priv->bo)
  151. nouveau_bo_unpin(priv->bo);
  152. nouveau_bo_ref(NULL, &priv->bo);
  153. drm->fence = NULL;
  154. kfree(priv);
  155. }
  156. int
  157. nv84_fence_create(struct nouveau_drm *drm)
  158. {
  159. struct nv84_fence_priv *priv;
  160. u32 domain;
  161. int ret;
  162. priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
  163. if (!priv)
  164. return -ENOMEM;
  165. priv->base.dtor = nv84_fence_destroy;
  166. priv->base.suspend = nv84_fence_suspend;
  167. priv->base.resume = nv84_fence_resume;
  168. priv->base.context_new = nv84_fence_context_new;
  169. priv->base.context_del = nv84_fence_context_del;
  170. priv->base.uevent = true;
  171. mutex_init(&priv->mutex);
  172. /* Use VRAM if there is any ; otherwise fallback to system memory */
  173. domain = drm->client.device.info.ram_size != 0 ? TTM_PL_FLAG_VRAM :
  174. /*
  175. * fences created in sysmem must be non-cached or we
  176. * will lose CPU/GPU coherency!
  177. */
  178. TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED;
  179. ret = nouveau_bo_new(&drm->client, 16 * drm->chan.nr, 0,
  180. domain, 0, 0, NULL, NULL, &priv->bo);
  181. if (ret == 0) {
  182. ret = nouveau_bo_pin(priv->bo, domain, false);
  183. if (ret == 0) {
  184. ret = nouveau_bo_map(priv->bo);
  185. if (ret)
  186. nouveau_bo_unpin(priv->bo);
  187. }
  188. if (ret)
  189. nouveau_bo_ref(NULL, &priv->bo);
  190. }
  191. if (ret)
  192. nv84_fence_destroy(drm);
  193. return ret;
  194. }