atombios_i2c.c 4.9 KB

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  1. /*
  2. * Copyright 2011 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Alex Deucher
  23. *
  24. */
  25. #include <drm/drmP.h>
  26. #include <drm/amdgpu_drm.h>
  27. #include "amdgpu.h"
  28. #include "atom.h"
  29. #include "amdgpu_atombios.h"
  30. #include "atombios_i2c.h"
  31. #define TARGET_HW_I2C_CLOCK 50
  32. /* these are a limitation of ProcessI2cChannelTransaction not the hw */
  33. #define ATOM_MAX_HW_I2C_WRITE 3
  34. #define ATOM_MAX_HW_I2C_READ 255
  35. static int amdgpu_atombios_i2c_process_i2c_ch(struct amdgpu_i2c_chan *chan,
  36. u8 slave_addr, u8 flags,
  37. u8 *buf, u8 num)
  38. {
  39. struct drm_device *dev = chan->dev;
  40. struct amdgpu_device *adev = dev->dev_private;
  41. PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION args;
  42. int index = GetIndexIntoMasterTable(COMMAND, ProcessI2cChannelTransaction);
  43. unsigned char *base;
  44. u16 out = cpu_to_le16(0);
  45. int r = 0;
  46. memset(&args, 0, sizeof(args));
  47. mutex_lock(&chan->mutex);
  48. base = (unsigned char *)adev->mode_info.atom_context->scratch;
  49. if (flags & HW_I2C_WRITE) {
  50. if (num > ATOM_MAX_HW_I2C_WRITE) {
  51. DRM_ERROR("hw i2c: tried to write too many bytes (%d vs 3)\n", num);
  52. r = -EINVAL;
  53. goto done;
  54. }
  55. if (buf == NULL)
  56. args.ucRegIndex = 0;
  57. else
  58. args.ucRegIndex = buf[0];
  59. if (num)
  60. num--;
  61. if (num) {
  62. if (buf) {
  63. memcpy(&out, &buf[1], num);
  64. } else {
  65. DRM_ERROR("hw i2c: missing buf with num > 1\n");
  66. r = -EINVAL;
  67. goto done;
  68. }
  69. }
  70. args.lpI2CDataOut = cpu_to_le16(out);
  71. } else {
  72. if (num > ATOM_MAX_HW_I2C_READ) {
  73. DRM_ERROR("hw i2c: tried to read too many bytes (%d vs 255)\n", num);
  74. r = -EINVAL;
  75. goto done;
  76. }
  77. args.ucRegIndex = 0;
  78. args.lpI2CDataOut = 0;
  79. }
  80. args.ucFlag = flags;
  81. args.ucI2CSpeed = TARGET_HW_I2C_CLOCK;
  82. args.ucTransBytes = num;
  83. args.ucSlaveAddr = slave_addr << 1;
  84. args.ucLineNumber = chan->rec.i2c_id;
  85. amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
  86. /* error */
  87. if (args.ucStatus != HW_ASSISTED_I2C_STATUS_SUCCESS) {
  88. DRM_DEBUG_KMS("hw_i2c error\n");
  89. r = -EIO;
  90. goto done;
  91. }
  92. if (!(flags & HW_I2C_WRITE))
  93. amdgpu_atombios_copy_swap(buf, base, num, false);
  94. done:
  95. mutex_unlock(&chan->mutex);
  96. return r;
  97. }
  98. int amdgpu_atombios_i2c_xfer(struct i2c_adapter *i2c_adap,
  99. struct i2c_msg *msgs, int num)
  100. {
  101. struct amdgpu_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
  102. struct i2c_msg *p;
  103. int i, remaining, current_count, buffer_offset, max_bytes, ret;
  104. u8 flags;
  105. /* check for bus probe */
  106. p = &msgs[0];
  107. if ((num == 1) && (p->len == 0)) {
  108. ret = amdgpu_atombios_i2c_process_i2c_ch(i2c,
  109. p->addr, HW_I2C_WRITE,
  110. NULL, 0);
  111. if (ret)
  112. return ret;
  113. else
  114. return num;
  115. }
  116. for (i = 0; i < num; i++) {
  117. p = &msgs[i];
  118. remaining = p->len;
  119. buffer_offset = 0;
  120. /* max_bytes are a limitation of ProcessI2cChannelTransaction not the hw */
  121. if (p->flags & I2C_M_RD) {
  122. max_bytes = ATOM_MAX_HW_I2C_READ;
  123. flags = HW_I2C_READ;
  124. } else {
  125. max_bytes = ATOM_MAX_HW_I2C_WRITE;
  126. flags = HW_I2C_WRITE;
  127. }
  128. while (remaining) {
  129. if (remaining > max_bytes)
  130. current_count = max_bytes;
  131. else
  132. current_count = remaining;
  133. ret = amdgpu_atombios_i2c_process_i2c_ch(i2c,
  134. p->addr, flags,
  135. &p->buf[buffer_offset], current_count);
  136. if (ret)
  137. return ret;
  138. remaining -= current_count;
  139. buffer_offset += current_count;
  140. }
  141. }
  142. return num;
  143. }
  144. u32 amdgpu_atombios_i2c_func(struct i2c_adapter *adap)
  145. {
  146. return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
  147. }
  148. void amdgpu_atombios_i2c_channel_trans(struct amdgpu_device* adev, u8 slave_addr, u8 line_number, u8 offset, u8 data)
  149. {
  150. PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION args;
  151. int index = GetIndexIntoMasterTable(COMMAND, ProcessI2cChannelTransaction);
  152. args.ucRegIndex = offset;
  153. args.lpI2CDataOut = data;
  154. args.ucFlag = 1;
  155. args.ucI2CSpeed = TARGET_HW_I2C_CLOCK;
  156. args.ucTransBytes = 1;
  157. args.ucSlaveAddr = slave_addr;
  158. args.ucLineNumber = line_number;
  159. amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
  160. }