amdgpu_sync.c 9.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426
  1. /*
  2. * Copyright 2014 Advanced Micro Devices, Inc.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sub license, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20. *
  21. * The above copyright notice and this permission notice (including the
  22. * next paragraph) shall be included in all copies or substantial portions
  23. * of the Software.
  24. *
  25. */
  26. /*
  27. * Authors:
  28. * Christian König <christian.koenig@amd.com>
  29. */
  30. #include <drm/drmP.h>
  31. #include "amdgpu.h"
  32. #include "amdgpu_trace.h"
  33. #include "amdgpu_amdkfd.h"
  34. struct amdgpu_sync_entry {
  35. struct hlist_node node;
  36. struct dma_fence *fence;
  37. bool explicit;
  38. };
  39. static struct kmem_cache *amdgpu_sync_slab;
  40. /**
  41. * amdgpu_sync_create - zero init sync object
  42. *
  43. * @sync: sync object to initialize
  44. *
  45. * Just clear the sync object for now.
  46. */
  47. void amdgpu_sync_create(struct amdgpu_sync *sync)
  48. {
  49. hash_init(sync->fences);
  50. sync->last_vm_update = NULL;
  51. }
  52. /**
  53. * amdgpu_sync_same_dev - test if fence belong to us
  54. *
  55. * @adev: amdgpu device to use for the test
  56. * @f: fence to test
  57. *
  58. * Test if the fence was issued by us.
  59. */
  60. static bool amdgpu_sync_same_dev(struct amdgpu_device *adev,
  61. struct dma_fence *f)
  62. {
  63. struct drm_sched_fence *s_fence = to_drm_sched_fence(f);
  64. if (s_fence) {
  65. struct amdgpu_ring *ring;
  66. ring = container_of(s_fence->sched, struct amdgpu_ring, sched);
  67. return ring->adev == adev;
  68. }
  69. return false;
  70. }
  71. /**
  72. * amdgpu_sync_get_owner - extract the owner of a fence
  73. *
  74. * @fence: fence get the owner from
  75. *
  76. * Extract who originally created the fence.
  77. */
  78. static void *amdgpu_sync_get_owner(struct dma_fence *f)
  79. {
  80. struct drm_sched_fence *s_fence;
  81. struct amdgpu_amdkfd_fence *kfd_fence;
  82. if (!f)
  83. return AMDGPU_FENCE_OWNER_UNDEFINED;
  84. s_fence = to_drm_sched_fence(f);
  85. if (s_fence)
  86. return s_fence->owner;
  87. kfd_fence = to_amdgpu_amdkfd_fence(f);
  88. if (kfd_fence)
  89. return AMDGPU_FENCE_OWNER_KFD;
  90. return AMDGPU_FENCE_OWNER_UNDEFINED;
  91. }
  92. /**
  93. * amdgpu_sync_keep_later - Keep the later fence
  94. *
  95. * @keep: existing fence to test
  96. * @fence: new fence
  97. *
  98. * Either keep the existing fence or the new one, depending which one is later.
  99. */
  100. static void amdgpu_sync_keep_later(struct dma_fence **keep,
  101. struct dma_fence *fence)
  102. {
  103. if (*keep && dma_fence_is_later(*keep, fence))
  104. return;
  105. dma_fence_put(*keep);
  106. *keep = dma_fence_get(fence);
  107. }
  108. /**
  109. * amdgpu_sync_add_later - add the fence to the hash
  110. *
  111. * @sync: sync object to add the fence to
  112. * @f: fence to add
  113. *
  114. * Tries to add the fence to an existing hash entry. Returns true when an entry
  115. * was found, false otherwise.
  116. */
  117. static bool amdgpu_sync_add_later(struct amdgpu_sync *sync, struct dma_fence *f, bool explicit)
  118. {
  119. struct amdgpu_sync_entry *e;
  120. hash_for_each_possible(sync->fences, e, node, f->context) {
  121. if (unlikely(e->fence->context != f->context))
  122. continue;
  123. amdgpu_sync_keep_later(&e->fence, f);
  124. /* Preserve eplicit flag to not loose pipe line sync */
  125. e->explicit |= explicit;
  126. return true;
  127. }
  128. return false;
  129. }
  130. /**
  131. * amdgpu_sync_fence - remember to sync to this fence
  132. *
  133. * @sync: sync object to add fence to
  134. * @fence: fence to sync to
  135. *
  136. */
  137. int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
  138. struct dma_fence *f, bool explicit)
  139. {
  140. struct amdgpu_sync_entry *e;
  141. if (!f)
  142. return 0;
  143. if (amdgpu_sync_same_dev(adev, f) &&
  144. amdgpu_sync_get_owner(f) == AMDGPU_FENCE_OWNER_VM)
  145. amdgpu_sync_keep_later(&sync->last_vm_update, f);
  146. if (amdgpu_sync_add_later(sync, f, explicit))
  147. return 0;
  148. e = kmem_cache_alloc(amdgpu_sync_slab, GFP_KERNEL);
  149. if (!e)
  150. return -ENOMEM;
  151. e->explicit = explicit;
  152. hash_add(sync->fences, &e->node, f->context);
  153. e->fence = dma_fence_get(f);
  154. return 0;
  155. }
  156. /**
  157. * amdgpu_sync_resv - sync to a reservation object
  158. *
  159. * @sync: sync object to add fences from reservation object to
  160. * @resv: reservation object with embedded fence
  161. * @explicit_sync: true if we should only sync to the exclusive fence
  162. *
  163. * Sync to the fence
  164. */
  165. int amdgpu_sync_resv(struct amdgpu_device *adev,
  166. struct amdgpu_sync *sync,
  167. struct reservation_object *resv,
  168. void *owner, bool explicit_sync)
  169. {
  170. struct reservation_object_list *flist;
  171. struct dma_fence *f;
  172. void *fence_owner;
  173. unsigned i;
  174. int r = 0;
  175. if (resv == NULL)
  176. return -EINVAL;
  177. /* always sync to the exclusive fence */
  178. f = reservation_object_get_excl(resv);
  179. r = amdgpu_sync_fence(adev, sync, f, false);
  180. flist = reservation_object_get_list(resv);
  181. if (!flist || r)
  182. return r;
  183. for (i = 0; i < flist->shared_count; ++i) {
  184. f = rcu_dereference_protected(flist->shared[i],
  185. reservation_object_held(resv));
  186. /* We only want to trigger KFD eviction fences on
  187. * evict or move jobs. Skip KFD fences otherwise.
  188. */
  189. fence_owner = amdgpu_sync_get_owner(f);
  190. if (fence_owner == AMDGPU_FENCE_OWNER_KFD &&
  191. owner != AMDGPU_FENCE_OWNER_UNDEFINED)
  192. continue;
  193. if (amdgpu_sync_same_dev(adev, f)) {
  194. /* VM updates are only interesting
  195. * for other VM updates and moves.
  196. */
  197. if ((owner != AMDGPU_FENCE_OWNER_UNDEFINED) &&
  198. (fence_owner != AMDGPU_FENCE_OWNER_UNDEFINED) &&
  199. ((owner == AMDGPU_FENCE_OWNER_VM) !=
  200. (fence_owner == AMDGPU_FENCE_OWNER_VM)))
  201. continue;
  202. /* Ignore fence from the same owner and explicit one as
  203. * long as it isn't undefined.
  204. */
  205. if (owner != AMDGPU_FENCE_OWNER_UNDEFINED &&
  206. (fence_owner == owner || explicit_sync))
  207. continue;
  208. }
  209. r = amdgpu_sync_fence(adev, sync, f, false);
  210. if (r)
  211. break;
  212. }
  213. return r;
  214. }
  215. /**
  216. * amdgpu_sync_peek_fence - get the next fence not signaled yet
  217. *
  218. * @sync: the sync object
  219. * @ring: optional ring to use for test
  220. *
  221. * Returns the next fence not signaled yet without removing it from the sync
  222. * object.
  223. */
  224. struct dma_fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync,
  225. struct amdgpu_ring *ring)
  226. {
  227. struct amdgpu_sync_entry *e;
  228. struct hlist_node *tmp;
  229. int i;
  230. hash_for_each_safe(sync->fences, i, tmp, e, node) {
  231. struct dma_fence *f = e->fence;
  232. struct drm_sched_fence *s_fence = to_drm_sched_fence(f);
  233. if (dma_fence_is_signaled(f)) {
  234. hash_del(&e->node);
  235. dma_fence_put(f);
  236. kmem_cache_free(amdgpu_sync_slab, e);
  237. continue;
  238. }
  239. if (ring && s_fence) {
  240. /* For fences from the same ring it is sufficient
  241. * when they are scheduled.
  242. */
  243. if (s_fence->sched == &ring->sched) {
  244. if (dma_fence_is_signaled(&s_fence->scheduled))
  245. continue;
  246. return &s_fence->scheduled;
  247. }
  248. }
  249. return f;
  250. }
  251. return NULL;
  252. }
  253. /**
  254. * amdgpu_sync_get_fence - get the next fence from the sync object
  255. *
  256. * @sync: sync object to use
  257. * @explicit: true if the next fence is explicit
  258. *
  259. * Get and removes the next fence from the sync object not signaled yet.
  260. */
  261. struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync, bool *explicit)
  262. {
  263. struct amdgpu_sync_entry *e;
  264. struct hlist_node *tmp;
  265. struct dma_fence *f;
  266. int i;
  267. hash_for_each_safe(sync->fences, i, tmp, e, node) {
  268. f = e->fence;
  269. if (explicit)
  270. *explicit = e->explicit;
  271. hash_del(&e->node);
  272. kmem_cache_free(amdgpu_sync_slab, e);
  273. if (!dma_fence_is_signaled(f))
  274. return f;
  275. dma_fence_put(f);
  276. }
  277. return NULL;
  278. }
  279. /**
  280. * amdgpu_sync_clone - clone a sync object
  281. *
  282. * @source: sync object to clone
  283. * @clone: pointer to destination sync object
  284. *
  285. * Adds references to all unsignaled fences in @source to @clone. Also
  286. * removes signaled fences from @source while at it.
  287. */
  288. int amdgpu_sync_clone(struct amdgpu_sync *source, struct amdgpu_sync *clone)
  289. {
  290. struct amdgpu_sync_entry *e;
  291. struct hlist_node *tmp;
  292. struct dma_fence *f;
  293. int i, r;
  294. hash_for_each_safe(source->fences, i, tmp, e, node) {
  295. f = e->fence;
  296. if (!dma_fence_is_signaled(f)) {
  297. r = amdgpu_sync_fence(NULL, clone, f, e->explicit);
  298. if (r)
  299. return r;
  300. } else {
  301. hash_del(&e->node);
  302. dma_fence_put(f);
  303. kmem_cache_free(amdgpu_sync_slab, e);
  304. }
  305. }
  306. dma_fence_put(clone->last_vm_update);
  307. clone->last_vm_update = dma_fence_get(source->last_vm_update);
  308. return 0;
  309. }
  310. int amdgpu_sync_wait(struct amdgpu_sync *sync, bool intr)
  311. {
  312. struct amdgpu_sync_entry *e;
  313. struct hlist_node *tmp;
  314. int i, r;
  315. hash_for_each_safe(sync->fences, i, tmp, e, node) {
  316. r = dma_fence_wait(e->fence, intr);
  317. if (r)
  318. return r;
  319. hash_del(&e->node);
  320. dma_fence_put(e->fence);
  321. kmem_cache_free(amdgpu_sync_slab, e);
  322. }
  323. return 0;
  324. }
  325. /**
  326. * amdgpu_sync_free - free the sync object
  327. *
  328. * @sync: sync object to use
  329. *
  330. * Free the sync object.
  331. */
  332. void amdgpu_sync_free(struct amdgpu_sync *sync)
  333. {
  334. struct amdgpu_sync_entry *e;
  335. struct hlist_node *tmp;
  336. unsigned i;
  337. hash_for_each_safe(sync->fences, i, tmp, e, node) {
  338. hash_del(&e->node);
  339. dma_fence_put(e->fence);
  340. kmem_cache_free(amdgpu_sync_slab, e);
  341. }
  342. dma_fence_put(sync->last_vm_update);
  343. }
  344. /**
  345. * amdgpu_sync_init - init sync object subsystem
  346. *
  347. * Allocate the slab allocator.
  348. */
  349. int amdgpu_sync_init(void)
  350. {
  351. amdgpu_sync_slab = kmem_cache_create(
  352. "amdgpu_sync", sizeof(struct amdgpu_sync_entry), 0,
  353. SLAB_HWCACHE_ALIGN, NULL);
  354. if (!amdgpu_sync_slab)
  355. return -ENOMEM;
  356. return 0;
  357. }
  358. /**
  359. * amdgpu_sync_fini - fini sync object subsystem
  360. *
  361. * Free the slab allocator.
  362. */
  363. void amdgpu_sync_fini(void)
  364. {
  365. kmem_cache_destroy(amdgpu_sync_slab);
  366. }