amdgpu_fb.c 10 KB

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  1. /*
  2. * Copyright © 2007 David Airlie
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * David Airlie
  25. */
  26. #include <linux/module.h>
  27. #include <linux/slab.h>
  28. #include <linux/pm_runtime.h>
  29. #include <drm/drmP.h>
  30. #include <drm/drm_crtc.h>
  31. #include <drm/drm_crtc_helper.h>
  32. #include <drm/amdgpu_drm.h>
  33. #include "amdgpu.h"
  34. #include "cikd.h"
  35. #include <drm/drm_fb_helper.h>
  36. #include <linux/vga_switcheroo.h>
  37. #include "amdgpu_display.h"
  38. /* object hierarchy -
  39. this contains a helper + a amdgpu fb
  40. the helper contains a pointer to amdgpu framebuffer baseclass.
  41. */
  42. static int
  43. amdgpufb_open(struct fb_info *info, int user)
  44. {
  45. struct amdgpu_fbdev *rfbdev = info->par;
  46. struct amdgpu_device *adev = rfbdev->adev;
  47. int ret = pm_runtime_get_sync(adev->ddev->dev);
  48. if (ret < 0 && ret != -EACCES) {
  49. pm_runtime_mark_last_busy(adev->ddev->dev);
  50. pm_runtime_put_autosuspend(adev->ddev->dev);
  51. return ret;
  52. }
  53. return 0;
  54. }
  55. static int
  56. amdgpufb_release(struct fb_info *info, int user)
  57. {
  58. struct amdgpu_fbdev *rfbdev = info->par;
  59. struct amdgpu_device *adev = rfbdev->adev;
  60. pm_runtime_mark_last_busy(adev->ddev->dev);
  61. pm_runtime_put_autosuspend(adev->ddev->dev);
  62. return 0;
  63. }
  64. static struct fb_ops amdgpufb_ops = {
  65. .owner = THIS_MODULE,
  66. DRM_FB_HELPER_DEFAULT_OPS,
  67. .fb_open = amdgpufb_open,
  68. .fb_release = amdgpufb_release,
  69. .fb_fillrect = drm_fb_helper_cfb_fillrect,
  70. .fb_copyarea = drm_fb_helper_cfb_copyarea,
  71. .fb_imageblit = drm_fb_helper_cfb_imageblit,
  72. };
  73. int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int cpp, bool tiled)
  74. {
  75. int aligned = width;
  76. int pitch_mask = 0;
  77. switch (cpp) {
  78. case 1:
  79. pitch_mask = 255;
  80. break;
  81. case 2:
  82. pitch_mask = 127;
  83. break;
  84. case 3:
  85. case 4:
  86. pitch_mask = 63;
  87. break;
  88. }
  89. aligned += pitch_mask;
  90. aligned &= ~pitch_mask;
  91. return aligned * cpp;
  92. }
  93. static void amdgpufb_destroy_pinned_object(struct drm_gem_object *gobj)
  94. {
  95. struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
  96. int ret;
  97. ret = amdgpu_bo_reserve(abo, true);
  98. if (likely(ret == 0)) {
  99. amdgpu_bo_kunmap(abo);
  100. amdgpu_bo_unpin(abo);
  101. amdgpu_bo_unreserve(abo);
  102. }
  103. drm_gem_object_put_unlocked(gobj);
  104. }
  105. static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,
  106. struct drm_mode_fb_cmd2 *mode_cmd,
  107. struct drm_gem_object **gobj_p)
  108. {
  109. struct amdgpu_device *adev = rfbdev->adev;
  110. struct drm_gem_object *gobj = NULL;
  111. struct amdgpu_bo *abo = NULL;
  112. bool fb_tiled = false; /* useful for testing */
  113. u32 tiling_flags = 0, domain;
  114. int ret;
  115. int aligned_size, size;
  116. int height = mode_cmd->height;
  117. u32 cpp;
  118. cpp = drm_format_plane_cpp(mode_cmd->pixel_format, 0);
  119. /* need to align pitch with crtc limits */
  120. mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp,
  121. fb_tiled);
  122. domain = amdgpu_display_supported_domains(adev);
  123. height = ALIGN(mode_cmd->height, 8);
  124. size = mode_cmd->pitches[0] * height;
  125. aligned_size = ALIGN(size, PAGE_SIZE);
  126. ret = amdgpu_gem_object_create(adev, aligned_size, 0, domain,
  127. AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
  128. AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
  129. AMDGPU_GEM_CREATE_VRAM_CLEARED,
  130. ttm_bo_type_kernel, NULL, &gobj);
  131. if (ret) {
  132. pr_err("failed to allocate framebuffer (%d)\n", aligned_size);
  133. return -ENOMEM;
  134. }
  135. abo = gem_to_amdgpu_bo(gobj);
  136. if (fb_tiled)
  137. tiling_flags = AMDGPU_TILING_SET(ARRAY_MODE, GRPH_ARRAY_2D_TILED_THIN1);
  138. ret = amdgpu_bo_reserve(abo, false);
  139. if (unlikely(ret != 0))
  140. goto out_unref;
  141. if (tiling_flags) {
  142. ret = amdgpu_bo_set_tiling_flags(abo,
  143. tiling_flags);
  144. if (ret)
  145. dev_err(adev->dev, "FB failed to set tiling flags\n");
  146. }
  147. ret = amdgpu_bo_pin(abo, domain);
  148. if (ret) {
  149. amdgpu_bo_unreserve(abo);
  150. goto out_unref;
  151. }
  152. ret = amdgpu_ttm_alloc_gart(&abo->tbo);
  153. if (ret) {
  154. amdgpu_bo_unreserve(abo);
  155. dev_err(adev->dev, "%p bind failed\n", abo);
  156. goto out_unref;
  157. }
  158. ret = amdgpu_bo_kmap(abo, NULL);
  159. amdgpu_bo_unreserve(abo);
  160. if (ret) {
  161. goto out_unref;
  162. }
  163. *gobj_p = gobj;
  164. return 0;
  165. out_unref:
  166. amdgpufb_destroy_pinned_object(gobj);
  167. *gobj_p = NULL;
  168. return ret;
  169. }
  170. static int amdgpufb_create(struct drm_fb_helper *helper,
  171. struct drm_fb_helper_surface_size *sizes)
  172. {
  173. struct amdgpu_fbdev *rfbdev = (struct amdgpu_fbdev *)helper;
  174. struct amdgpu_device *adev = rfbdev->adev;
  175. struct fb_info *info;
  176. struct drm_framebuffer *fb = NULL;
  177. struct drm_mode_fb_cmd2 mode_cmd;
  178. struct drm_gem_object *gobj = NULL;
  179. struct amdgpu_bo *abo = NULL;
  180. int ret;
  181. unsigned long tmp;
  182. mode_cmd.width = sizes->surface_width;
  183. mode_cmd.height = sizes->surface_height;
  184. if (sizes->surface_bpp == 24)
  185. sizes->surface_bpp = 32;
  186. mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
  187. sizes->surface_depth);
  188. ret = amdgpufb_create_pinned_object(rfbdev, &mode_cmd, &gobj);
  189. if (ret) {
  190. DRM_ERROR("failed to create fbcon object %d\n", ret);
  191. return ret;
  192. }
  193. abo = gem_to_amdgpu_bo(gobj);
  194. /* okay we have an object now allocate the framebuffer */
  195. info = drm_fb_helper_alloc_fbi(helper);
  196. if (IS_ERR(info)) {
  197. ret = PTR_ERR(info);
  198. goto out;
  199. }
  200. info->par = rfbdev;
  201. info->skip_vt_switch = true;
  202. ret = amdgpu_display_framebuffer_init(adev->ddev, &rfbdev->rfb,
  203. &mode_cmd, gobj);
  204. if (ret) {
  205. DRM_ERROR("failed to initialize framebuffer %d\n", ret);
  206. goto out;
  207. }
  208. fb = &rfbdev->rfb.base;
  209. /* setup helper */
  210. rfbdev->helper.fb = fb;
  211. strcpy(info->fix.id, "amdgpudrmfb");
  212. drm_fb_helper_fill_fix(info, fb->pitches[0], fb->format->depth);
  213. info->fbops = &amdgpufb_ops;
  214. tmp = amdgpu_bo_gpu_offset(abo) - adev->gmc.vram_start;
  215. info->fix.smem_start = adev->gmc.aper_base + tmp;
  216. info->fix.smem_len = amdgpu_bo_size(abo);
  217. info->screen_base = amdgpu_bo_kptr(abo);
  218. info->screen_size = amdgpu_bo_size(abo);
  219. drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height);
  220. /* setup aperture base/size for vesafb takeover */
  221. info->apertures->ranges[0].base = adev->ddev->mode_config.fb_base;
  222. info->apertures->ranges[0].size = adev->gmc.aper_size;
  223. /* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */
  224. if (info->screen_base == NULL) {
  225. ret = -ENOSPC;
  226. goto out;
  227. }
  228. DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start);
  229. DRM_INFO("vram apper at 0x%lX\n", (unsigned long)adev->gmc.aper_base);
  230. DRM_INFO("size %lu\n", (unsigned long)amdgpu_bo_size(abo));
  231. DRM_INFO("fb depth is %d\n", fb->format->depth);
  232. DRM_INFO(" pitch is %d\n", fb->pitches[0]);
  233. vga_switcheroo_client_fb_set(adev->ddev->pdev, info);
  234. return 0;
  235. out:
  236. if (abo) {
  237. }
  238. if (fb && ret) {
  239. drm_gem_object_put_unlocked(gobj);
  240. drm_framebuffer_unregister_private(fb);
  241. drm_framebuffer_cleanup(fb);
  242. kfree(fb);
  243. }
  244. return ret;
  245. }
  246. static int amdgpu_fbdev_destroy(struct drm_device *dev, struct amdgpu_fbdev *rfbdev)
  247. {
  248. struct amdgpu_framebuffer *rfb = &rfbdev->rfb;
  249. drm_fb_helper_unregister_fbi(&rfbdev->helper);
  250. if (rfb->base.obj[0]) {
  251. amdgpufb_destroy_pinned_object(rfb->base.obj[0]);
  252. rfb->base.obj[0] = NULL;
  253. drm_framebuffer_unregister_private(&rfb->base);
  254. drm_framebuffer_cleanup(&rfb->base);
  255. }
  256. drm_fb_helper_fini(&rfbdev->helper);
  257. return 0;
  258. }
  259. static const struct drm_fb_helper_funcs amdgpu_fb_helper_funcs = {
  260. .fb_probe = amdgpufb_create,
  261. };
  262. int amdgpu_fbdev_init(struct amdgpu_device *adev)
  263. {
  264. struct amdgpu_fbdev *rfbdev;
  265. int bpp_sel = 32;
  266. int ret;
  267. /* don't init fbdev on hw without DCE */
  268. if (!adev->mode_info.mode_config_initialized)
  269. return 0;
  270. /* don't init fbdev if there are no connectors */
  271. if (list_empty(&adev->ddev->mode_config.connector_list))
  272. return 0;
  273. /* select 8 bpp console on low vram cards */
  274. if (adev->gmc.real_vram_size <= (32*1024*1024))
  275. bpp_sel = 8;
  276. rfbdev = kzalloc(sizeof(struct amdgpu_fbdev), GFP_KERNEL);
  277. if (!rfbdev)
  278. return -ENOMEM;
  279. rfbdev->adev = adev;
  280. adev->mode_info.rfbdev = rfbdev;
  281. drm_fb_helper_prepare(adev->ddev, &rfbdev->helper,
  282. &amdgpu_fb_helper_funcs);
  283. ret = drm_fb_helper_init(adev->ddev, &rfbdev->helper,
  284. AMDGPUFB_CONN_LIMIT);
  285. if (ret) {
  286. kfree(rfbdev);
  287. return ret;
  288. }
  289. drm_fb_helper_single_add_all_connectors(&rfbdev->helper);
  290. /* disable all the possible outputs/crtcs before entering KMS mode */
  291. if (!amdgpu_device_has_dc_support(adev))
  292. drm_helper_disable_unused_functions(adev->ddev);
  293. drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel);
  294. return 0;
  295. }
  296. void amdgpu_fbdev_fini(struct amdgpu_device *adev)
  297. {
  298. if (!adev->mode_info.rfbdev)
  299. return;
  300. amdgpu_fbdev_destroy(adev->ddev, adev->mode_info.rfbdev);
  301. kfree(adev->mode_info.rfbdev);
  302. adev->mode_info.rfbdev = NULL;
  303. }
  304. void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state)
  305. {
  306. if (adev->mode_info.rfbdev)
  307. drm_fb_helper_set_suspend_unlocked(&adev->mode_info.rfbdev->helper,
  308. state);
  309. }
  310. int amdgpu_fbdev_total_size(struct amdgpu_device *adev)
  311. {
  312. struct amdgpu_bo *robj;
  313. int size = 0;
  314. if (!adev->mode_info.rfbdev)
  315. return 0;
  316. robj = gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.base.obj[0]);
  317. size += amdgpu_bo_size(robj);
  318. return size;
  319. }
  320. bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj)
  321. {
  322. if (!adev->mode_info.rfbdev)
  323. return false;
  324. if (robj == gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.base.obj[0]))
  325. return true;
  326. return false;
  327. }