gpio-104-idio-16.c 8.2 KB

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  1. /*
  2. * GPIO driver for the ACCES 104-IDIO-16 family
  3. * Copyright (C) 2015 William Breathitt Gray
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License, version 2, as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but
  10. * WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  12. * General Public License for more details.
  13. *
  14. * This driver supports the following ACCES devices: 104-IDIO-16,
  15. * 104-IDIO-16E, 104-IDO-16, 104-IDIO-8, 104-IDIO-8E, and 104-IDO-8.
  16. */
  17. #include <linux/bitops.h>
  18. #include <linux/device.h>
  19. #include <linux/errno.h>
  20. #include <linux/gpio/driver.h>
  21. #include <linux/io.h>
  22. #include <linux/ioport.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/irqdesc.h>
  25. #include <linux/isa.h>
  26. #include <linux/kernel.h>
  27. #include <linux/module.h>
  28. #include <linux/moduleparam.h>
  29. #include <linux/spinlock.h>
  30. #define IDIO_16_EXTENT 8
  31. #define MAX_NUM_IDIO_16 max_num_isa_dev(IDIO_16_EXTENT)
  32. static unsigned int base[MAX_NUM_IDIO_16];
  33. static unsigned int num_idio_16;
  34. module_param_hw_array(base, uint, ioport, &num_idio_16, 0);
  35. MODULE_PARM_DESC(base, "ACCES 104-IDIO-16 base addresses");
  36. static unsigned int irq[MAX_NUM_IDIO_16];
  37. module_param_hw_array(irq, uint, irq, NULL, 0);
  38. MODULE_PARM_DESC(irq, "ACCES 104-IDIO-16 interrupt line numbers");
  39. /**
  40. * struct idio_16_gpio - GPIO device private data structure
  41. * @chip: instance of the gpio_chip
  42. * @lock: synchronization lock to prevent I/O race conditions
  43. * @irq_mask: I/O bits affected by interrupts
  44. * @base: base port address of the GPIO device
  45. * @out_state: output bits state
  46. */
  47. struct idio_16_gpio {
  48. struct gpio_chip chip;
  49. raw_spinlock_t lock;
  50. unsigned long irq_mask;
  51. unsigned base;
  52. unsigned out_state;
  53. };
  54. static int idio_16_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
  55. {
  56. if (offset > 15)
  57. return 1;
  58. return 0;
  59. }
  60. static int idio_16_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
  61. {
  62. return 0;
  63. }
  64. static int idio_16_gpio_direction_output(struct gpio_chip *chip,
  65. unsigned offset, int value)
  66. {
  67. chip->set(chip, offset, value);
  68. return 0;
  69. }
  70. static int idio_16_gpio_get(struct gpio_chip *chip, unsigned offset)
  71. {
  72. struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
  73. const unsigned mask = BIT(offset-16);
  74. if (offset < 16)
  75. return -EINVAL;
  76. if (offset < 24)
  77. return !!(inb(idio16gpio->base + 1) & mask);
  78. return !!(inb(idio16gpio->base + 5) & (mask>>8));
  79. }
  80. static int idio_16_gpio_get_multiple(struct gpio_chip *chip,
  81. unsigned long *mask, unsigned long *bits)
  82. {
  83. struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
  84. *bits = 0;
  85. if (*mask & GENMASK(23, 16))
  86. *bits |= (unsigned long)inb(idio16gpio->base + 1) << 16;
  87. if (*mask & GENMASK(31, 24))
  88. *bits |= (unsigned long)inb(idio16gpio->base + 5) << 24;
  89. return 0;
  90. }
  91. static void idio_16_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  92. {
  93. struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
  94. const unsigned mask = BIT(offset);
  95. unsigned long flags;
  96. if (offset > 15)
  97. return;
  98. raw_spin_lock_irqsave(&idio16gpio->lock, flags);
  99. if (value)
  100. idio16gpio->out_state |= mask;
  101. else
  102. idio16gpio->out_state &= ~mask;
  103. if (offset > 7)
  104. outb(idio16gpio->out_state >> 8, idio16gpio->base + 4);
  105. else
  106. outb(idio16gpio->out_state, idio16gpio->base);
  107. raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
  108. }
  109. static void idio_16_gpio_set_multiple(struct gpio_chip *chip,
  110. unsigned long *mask, unsigned long *bits)
  111. {
  112. struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
  113. unsigned long flags;
  114. raw_spin_lock_irqsave(&idio16gpio->lock, flags);
  115. idio16gpio->out_state &= ~*mask;
  116. idio16gpio->out_state |= *mask & *bits;
  117. if (*mask & 0xFF)
  118. outb(idio16gpio->out_state, idio16gpio->base);
  119. if ((*mask >> 8) & 0xFF)
  120. outb(idio16gpio->out_state >> 8, idio16gpio->base + 4);
  121. raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
  122. }
  123. static void idio_16_irq_ack(struct irq_data *data)
  124. {
  125. }
  126. static void idio_16_irq_mask(struct irq_data *data)
  127. {
  128. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  129. struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
  130. const unsigned long mask = BIT(irqd_to_hwirq(data));
  131. unsigned long flags;
  132. idio16gpio->irq_mask &= ~mask;
  133. if (!idio16gpio->irq_mask) {
  134. raw_spin_lock_irqsave(&idio16gpio->lock, flags);
  135. outb(0, idio16gpio->base + 2);
  136. raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
  137. }
  138. }
  139. static void idio_16_irq_unmask(struct irq_data *data)
  140. {
  141. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  142. struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
  143. const unsigned long mask = BIT(irqd_to_hwirq(data));
  144. const unsigned long prev_irq_mask = idio16gpio->irq_mask;
  145. unsigned long flags;
  146. idio16gpio->irq_mask |= mask;
  147. if (!prev_irq_mask) {
  148. raw_spin_lock_irqsave(&idio16gpio->lock, flags);
  149. inb(idio16gpio->base + 2);
  150. raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
  151. }
  152. }
  153. static int idio_16_irq_set_type(struct irq_data *data, unsigned flow_type)
  154. {
  155. /* The only valid irq types are none and both-edges */
  156. if (flow_type != IRQ_TYPE_NONE &&
  157. (flow_type & IRQ_TYPE_EDGE_BOTH) != IRQ_TYPE_EDGE_BOTH)
  158. return -EINVAL;
  159. return 0;
  160. }
  161. static struct irq_chip idio_16_irqchip = {
  162. .name = "104-idio-16",
  163. .irq_ack = idio_16_irq_ack,
  164. .irq_mask = idio_16_irq_mask,
  165. .irq_unmask = idio_16_irq_unmask,
  166. .irq_set_type = idio_16_irq_set_type
  167. };
  168. static irqreturn_t idio_16_irq_handler(int irq, void *dev_id)
  169. {
  170. struct idio_16_gpio *const idio16gpio = dev_id;
  171. struct gpio_chip *const chip = &idio16gpio->chip;
  172. int gpio;
  173. for_each_set_bit(gpio, &idio16gpio->irq_mask, chip->ngpio)
  174. generic_handle_irq(irq_find_mapping(chip->irq.domain, gpio));
  175. raw_spin_lock(&idio16gpio->lock);
  176. outb(0, idio16gpio->base + 1);
  177. raw_spin_unlock(&idio16gpio->lock);
  178. return IRQ_HANDLED;
  179. }
  180. #define IDIO_16_NGPIO 32
  181. static const char *idio_16_names[IDIO_16_NGPIO] = {
  182. "OUT0", "OUT1", "OUT2", "OUT3", "OUT4", "OUT5", "OUT6", "OUT7",
  183. "OUT8", "OUT9", "OUT10", "OUT11", "OUT12", "OUT13", "OUT14", "OUT15",
  184. "IIN0", "IIN1", "IIN2", "IIN3", "IIN4", "IIN5", "IIN6", "IIN7",
  185. "IIN8", "IIN9", "IIN10", "IIN11", "IIN12", "IIN13", "IIN14", "IIN15"
  186. };
  187. static int idio_16_probe(struct device *dev, unsigned int id)
  188. {
  189. struct idio_16_gpio *idio16gpio;
  190. const char *const name = dev_name(dev);
  191. int err;
  192. idio16gpio = devm_kzalloc(dev, sizeof(*idio16gpio), GFP_KERNEL);
  193. if (!idio16gpio)
  194. return -ENOMEM;
  195. if (!devm_request_region(dev, base[id], IDIO_16_EXTENT, name)) {
  196. dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
  197. base[id], base[id] + IDIO_16_EXTENT);
  198. return -EBUSY;
  199. }
  200. idio16gpio->chip.label = name;
  201. idio16gpio->chip.parent = dev;
  202. idio16gpio->chip.owner = THIS_MODULE;
  203. idio16gpio->chip.base = -1;
  204. idio16gpio->chip.ngpio = IDIO_16_NGPIO;
  205. idio16gpio->chip.names = idio_16_names;
  206. idio16gpio->chip.get_direction = idio_16_gpio_get_direction;
  207. idio16gpio->chip.direction_input = idio_16_gpio_direction_input;
  208. idio16gpio->chip.direction_output = idio_16_gpio_direction_output;
  209. idio16gpio->chip.get = idio_16_gpio_get;
  210. idio16gpio->chip.get_multiple = idio_16_gpio_get_multiple;
  211. idio16gpio->chip.set = idio_16_gpio_set;
  212. idio16gpio->chip.set_multiple = idio_16_gpio_set_multiple;
  213. idio16gpio->base = base[id];
  214. idio16gpio->out_state = 0xFFFF;
  215. raw_spin_lock_init(&idio16gpio->lock);
  216. err = devm_gpiochip_add_data(dev, &idio16gpio->chip, idio16gpio);
  217. if (err) {
  218. dev_err(dev, "GPIO registering failed (%d)\n", err);
  219. return err;
  220. }
  221. /* Disable IRQ by default */
  222. outb(0, base[id] + 2);
  223. outb(0, base[id] + 1);
  224. err = gpiochip_irqchip_add(&idio16gpio->chip, &idio_16_irqchip, 0,
  225. handle_edge_irq, IRQ_TYPE_NONE);
  226. if (err) {
  227. dev_err(dev, "Could not add irqchip (%d)\n", err);
  228. return err;
  229. }
  230. err = devm_request_irq(dev, irq[id], idio_16_irq_handler, 0, name,
  231. idio16gpio);
  232. if (err) {
  233. dev_err(dev, "IRQ handler registering failed (%d)\n", err);
  234. return err;
  235. }
  236. return 0;
  237. }
  238. static struct isa_driver idio_16_driver = {
  239. .probe = idio_16_probe,
  240. .driver = {
  241. .name = "104-idio-16"
  242. },
  243. };
  244. module_isa_driver(idio_16_driver, num_idio_16);
  245. MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
  246. MODULE_DESCRIPTION("ACCES 104-IDIO-16 GPIO driver");
  247. MODULE_LICENSE("GPL v2");