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cc_host_regs.h

cc_host_regs.h 7.2 KB
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  1. /* SPDX-License-Identifier: GPL-2.0 */
    2. 

  2. /* Copyright (C) 2012-2018 ARM Limited or its affiliates. */
    3. 

  3. 

  4. #ifndef __CC_HOST_H__
    5. 

  5. #define __CC_HOST_H__
    6. 

  6. 

  7. // --------------------------------------
    8. 

  8. // BLOCK: HOST_P
    9. 

  9. // --------------------------------------
    10. 

  10. #define CC_HOST_IRR_REG_OFFSET	0xA00UL
    11. 

  11. #define CC_HOST_IRR_DSCRPTR_COMPLETION_LOW_INT_BIT_SHIFT	0x2UL
    12. 

  12. #define CC_HOST_IRR_DSCRPTR_COMPLETION_LOW_INT_BIT_SIZE	0x1UL
    13. 

  13. #define CC_HOST_IRR_AXI_ERR_INT_BIT_SHIFT	0x8UL
    14. 

  14. #define CC_HOST_IRR_AXI_ERR_INT_BIT_SIZE	0x1UL
    15. 

  15. #define CC_HOST_IRR_GPR0_BIT_SHIFT	0xBUL
    16. 

  16. #define CC_HOST_IRR_GPR0_BIT_SIZE	0x1UL
    17. 

  17. #define CC_HOST_IRR_DSCRPTR_WATERMARK_INT_BIT_SHIFT	0x13UL
    18. 

  18. #define CC_HOST_IRR_DSCRPTR_WATERMARK_INT_BIT_SIZE	0x1UL
    19. 

  19. #define CC_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT	0x17UL
    20. 

  20. #define CC_HOST_IRR_AXIM_COMP_INT_BIT_SIZE	0x1UL
    21. 

  21. #define CC_HOST_SEP_SRAM_THRESHOLD_REG_OFFSET	0xA10UL
    22. 

  22. #define CC_HOST_SEP_SRAM_THRESHOLD_VALUE_BIT_SHIFT	0x0UL
    23. 

  23. #define CC_HOST_SEP_SRAM_THRESHOLD_VALUE_BIT_SIZE	0xCUL
    24. 

  24. #define CC_HOST_IMR_REG_OFFSET	0xA04UL
    25. 

  25. #define CC_HOST_IMR_NOT_USED_MASK_BIT_SHIFT	0x1UL
    26. 

  26. #define CC_HOST_IMR_NOT_USED_MASK_BIT_SIZE	0x1UL
    27. 

  27. #define CC_HOST_IMR_DSCRPTR_COMPLETION_MASK_BIT_SHIFT	0x2UL
    28. 

  28. #define CC_HOST_IMR_DSCRPTR_COMPLETION_MASK_BIT_SIZE	0x1UL
    29. 

  29. #define CC_HOST_IMR_AXI_ERR_MASK_BIT_SHIFT	0x8UL
    30. 

  30. #define CC_HOST_IMR_AXI_ERR_MASK_BIT_SIZE	0x1UL
    31. 

  31. #define CC_HOST_IMR_GPR0_BIT_SHIFT	0xBUL
    32. 

  32. #define CC_HOST_IMR_GPR0_BIT_SIZE	0x1UL
    33. 

  33. #define CC_HOST_IMR_DSCRPTR_WATERMARK_MASK0_BIT_SHIFT	0x13UL
    34. 

  34. #define CC_HOST_IMR_DSCRPTR_WATERMARK_MASK0_BIT_SIZE	0x1UL
    35. 

  35. #define CC_HOST_IMR_AXIM_COMP_INT_MASK_BIT_SHIFT	0x17UL
    36. 

  36. #define CC_HOST_IMR_AXIM_COMP_INT_MASK_BIT_SIZE	0x1UL
    37. 

  37. #define CC_HOST_ICR_REG_OFFSET	0xA08UL
    38. 

  38. #define CC_HOST_ICR_DSCRPTR_COMPLETION_BIT_SHIFT	0x2UL
    39. 

  39. #define CC_HOST_ICR_DSCRPTR_COMPLETION_BIT_SIZE	0x1UL
    40. 

  40. #define CC_HOST_ICR_AXI_ERR_CLEAR_BIT_SHIFT	0x8UL
    41. 

  41. #define CC_HOST_ICR_AXI_ERR_CLEAR_BIT_SIZE	0x1UL
    42. 

  42. #define CC_HOST_ICR_GPR_INT_CLEAR_BIT_SHIFT	0xBUL
    43. 

  43. #define CC_HOST_ICR_GPR_INT_CLEAR_BIT_SIZE	0x1UL
    44. 

  44. #define CC_HOST_ICR_DSCRPTR_WATERMARK_QUEUE0_CLEAR_BIT_SHIFT	0x13UL
    45. 

  45. #define CC_HOST_ICR_DSCRPTR_WATERMARK_QUEUE0_CLEAR_BIT_SIZE	0x1UL
    46. 

  46. #define CC_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SHIFT	0x17UL
    47. 

  47. #define CC_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SIZE	0x1UL
    48. 

  48. #define CC_HOST_SIGNATURE_712_REG_OFFSET	0xA24UL
    49. 

  49. #define CC_HOST_SIGNATURE_630_REG_OFFSET	0xAC8UL
    50. 

  50. #define CC_HOST_SIGNATURE_VALUE_BIT_SHIFT	0x0UL
    51. 

  51. #define CC_HOST_SIGNATURE_VALUE_BIT_SIZE	0x20UL
    52. 

  52. #define CC_HOST_BOOT_REG_OFFSET	0xA28UL
    53. 

  53. #define CC_HOST_BOOT_SYNTHESIS_CONFIG_BIT_SHIFT	0x0UL
    54. 

  54. #define CC_HOST_BOOT_SYNTHESIS_CONFIG_BIT_SIZE	0x1UL
    55. 

  55. #define CC_HOST_BOOT_LARGE_RKEK_LOCAL_BIT_SHIFT	0x1UL
    56. 

  56. #define CC_HOST_BOOT_LARGE_RKEK_LOCAL_BIT_SIZE	0x1UL
    57. 

  57. #define CC_HOST_BOOT_HASH_IN_FUSES_LOCAL_BIT_SHIFT	0x2UL
    58. 

  58. #define CC_HOST_BOOT_HASH_IN_FUSES_LOCAL_BIT_SIZE	0x1UL
    59. 

  59. #define CC_HOST_BOOT_EXT_MEM_SECURED_LOCAL_BIT_SHIFT	0x3UL
    60. 

  60. #define CC_HOST_BOOT_EXT_MEM_SECURED_LOCAL_BIT_SIZE	0x1UL
    61. 

  61. #define CC_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_BIT_SHIFT	0x5UL
    62. 

  62. #define CC_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_BIT_SIZE	0x1UL
    63. 

  63. #define CC_HOST_BOOT_SRAM_SIZE_LOCAL_BIT_SHIFT	0x6UL
    64. 

  64. #define CC_HOST_BOOT_SRAM_SIZE_LOCAL_BIT_SIZE	0x3UL
    65. 

  65. #define CC_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_BIT_SHIFT	0x9UL
    66. 

  66. #define CC_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_BIT_SIZE	0x1UL
    67. 

  67. #define CC_HOST_BOOT_PAU_EXISTS_LOCAL_BIT_SHIFT	0xAUL
    68. 

  68. #define CC_HOST_BOOT_PAU_EXISTS_LOCAL_BIT_SIZE	0x1UL
    69. 

  69. #define CC_HOST_BOOT_RNG_EXISTS_LOCAL_BIT_SHIFT	0xBUL
    70. 

  70. #define CC_HOST_BOOT_RNG_EXISTS_LOCAL_BIT_SIZE	0x1UL
    71. 

  71. #define CC_HOST_BOOT_PKA_EXISTS_LOCAL_BIT_SHIFT	0xCUL
    72. 

  72. #define CC_HOST_BOOT_PKA_EXISTS_LOCAL_BIT_SIZE	0x1UL
    73. 

  73. #define CC_HOST_BOOT_RC4_EXISTS_LOCAL_BIT_SHIFT	0xDUL
    74. 

  74. #define CC_HOST_BOOT_RC4_EXISTS_LOCAL_BIT_SIZE	0x1UL
    75. 

  75. #define CC_HOST_BOOT_SHA_512_PRSNT_LOCAL_BIT_SHIFT	0xEUL
    76. 

  76. #define CC_HOST_BOOT_SHA_512_PRSNT_LOCAL_BIT_SIZE	0x1UL
    77. 

  77. #define CC_HOST_BOOT_SHA_256_PRSNT_LOCAL_BIT_SHIFT	0xFUL
    78. 

  78. #define CC_HOST_BOOT_SHA_256_PRSNT_LOCAL_BIT_SIZE	0x1UL
    79. 

  79. #define CC_HOST_BOOT_MD5_PRSNT_LOCAL_BIT_SHIFT	0x10UL
    80. 

  80. #define CC_HOST_BOOT_MD5_PRSNT_LOCAL_BIT_SIZE	0x1UL
    81. 

  81. #define CC_HOST_BOOT_HASH_EXISTS_LOCAL_BIT_SHIFT	0x11UL
    82. 

  82. #define CC_HOST_BOOT_HASH_EXISTS_LOCAL_BIT_SIZE	0x1UL
    83. 

  83. #define CC_HOST_BOOT_C2_EXISTS_LOCAL_BIT_SHIFT	0x12UL
    84. 

  84. #define CC_HOST_BOOT_C2_EXISTS_LOCAL_BIT_SIZE	0x1UL
    85. 

  85. #define CC_HOST_BOOT_DES_EXISTS_LOCAL_BIT_SHIFT	0x13UL
    86. 

  86. #define CC_HOST_BOOT_DES_EXISTS_LOCAL_BIT_SIZE	0x1UL
    87. 

  87. #define CC_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_BIT_SHIFT	0x14UL
    88. 

  88. #define CC_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_BIT_SIZE	0x1UL
    89. 

  89. #define CC_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_BIT_SHIFT	0x15UL
    90. 

  90. #define CC_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_BIT_SIZE	0x1UL
    91. 

  91. #define CC_HOST_BOOT_AES_CCM_EXISTS_LOCAL_BIT_SHIFT	0x16UL
    92. 

  92. #define CC_HOST_BOOT_AES_CCM_EXISTS_LOCAL_BIT_SIZE	0x1UL
    93. 

  93. #define CC_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_BIT_SHIFT	0x17UL
    94. 

  94. #define CC_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_BIT_SIZE	0x1UL
    95. 

  95. #define CC_HOST_BOOT_AES_XEX_EXISTS_LOCAL_BIT_SHIFT	0x18UL
    96. 

  96. #define CC_HOST_BOOT_AES_XEX_EXISTS_LOCAL_BIT_SIZE	0x1UL
    97. 

  97. #define CC_HOST_BOOT_CTR_EXISTS_LOCAL_BIT_SHIFT	0x19UL
    98. 

  98. #define CC_HOST_BOOT_CTR_EXISTS_LOCAL_BIT_SIZE	0x1UL
    99. 

  99. #define CC_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_BIT_SHIFT	0x1AUL
    100. 

  100. #define CC_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_BIT_SIZE	0x1UL
    101. 

  101. #define CC_HOST_BOOT_TUNNELING_ENB_LOCAL_BIT_SHIFT	0x1BUL
    102. 

  102. #define CC_HOST_BOOT_TUNNELING_ENB_LOCAL_BIT_SIZE	0x1UL
    103. 

  103. #define CC_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_BIT_SHIFT	0x1CUL
    104. 

  104. #define CC_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_BIT_SIZE	0x1UL
    105. 

  105. #define CC_HOST_BOOT_ONLY_ENCRYPT_LOCAL_BIT_SHIFT	0x1DUL
    106. 

  106. #define CC_HOST_BOOT_ONLY_ENCRYPT_LOCAL_BIT_SIZE	0x1UL
    107. 

  107. #define CC_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SHIFT	0x1EUL
    108. 

  108. #define CC_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SIZE	0x1UL
    109. 

  109. #define CC_HOST_VERSION_712_REG_OFFSET	0xA40UL
    110. 

  110. #define CC_HOST_VERSION_630_REG_OFFSET	0xAD8UL
    111. 

  111. #define CC_HOST_VERSION_VALUE_BIT_SHIFT	0x0UL
    112. 

  112. #define CC_HOST_VERSION_VALUE_BIT_SIZE	0x20UL
    113. 

  113. #define CC_HOST_KFDE0_VALID_REG_OFFSET	0xA60UL
    114. 

  114. #define CC_HOST_KFDE0_VALID_VALUE_BIT_SHIFT	0x0UL
    115. 

  115. #define CC_HOST_KFDE0_VALID_VALUE_BIT_SIZE	0x1UL
    116. 

  116. #define CC_HOST_KFDE1_VALID_REG_OFFSET	0xA64UL
    117. 

  117. #define CC_HOST_KFDE1_VALID_VALUE_BIT_SHIFT	0x0UL
    118. 

  118. #define CC_HOST_KFDE1_VALID_VALUE_BIT_SIZE	0x1UL
    119. 

  119. #define CC_HOST_KFDE2_VALID_REG_OFFSET	0xA68UL
    120. 

  120. #define CC_HOST_KFDE2_VALID_VALUE_BIT_SHIFT	0x0UL
    121. 

  121. #define CC_HOST_KFDE2_VALID_VALUE_BIT_SIZE	0x1UL
    122. 

  122. #define CC_HOST_KFDE3_VALID_REG_OFFSET	0xA6CUL
    123. 

  123. #define CC_HOST_KFDE3_VALID_VALUE_BIT_SHIFT	0x0UL
    124. 

  124. #define CC_HOST_KFDE3_VALID_VALUE_BIT_SIZE	0x1UL
    125. 

  125. #define CC_HOST_GPR0_REG_OFFSET	0xA70UL
    126. 

  126. #define CC_HOST_GPR0_VALUE_BIT_SHIFT	0x0UL
    127. 

  127. #define CC_HOST_GPR0_VALUE_BIT_SIZE	0x20UL
    128. 

  128. #define CC_GPR_HOST_REG_OFFSET	0xA74UL
    129. 

  129. #define CC_GPR_HOST_VALUE_BIT_SHIFT	0x0UL
    130. 

  130. #define CC_GPR_HOST_VALUE_BIT_SIZE	0x20UL
    131. 

  131. #define CC_HOST_POWER_DOWN_EN_REG_OFFSET	0xA78UL
    132. 

  132. #define CC_HOST_POWER_DOWN_EN_VALUE_BIT_SHIFT	0x0UL
    133. 

  133. #define CC_HOST_POWER_DOWN_EN_VALUE_BIT_SIZE	0x1UL
    134. 

  134. // --------------------------------------
    135. 

  135. // BLOCK: HOST_SRAM
    136. 

  136. // --------------------------------------
    137. 

  137. #define CC_SRAM_DATA_REG_OFFSET	0xF00UL
    138. 

  138. #define CC_SRAM_DATA_VALUE_BIT_SHIFT	0x0UL
    139. 

  139. #define CC_SRAM_DATA_VALUE_BIT_SIZE	0x20UL
    140. 

  140. #define CC_SRAM_ADDR_REG_OFFSET	0xF04UL
    141. 

  141. #define CC_SRAM_ADDR_VALUE_BIT_SHIFT	0x0UL
    142. 

  142. #define CC_SRAM_ADDR_VALUE_BIT_SIZE	0xFUL
    143. 

  143. #define CC_SRAM_DATA_READY_REG_OFFSET	0xF08UL
    144. 

  144. #define CC_SRAM_DATA_READY_VALUE_BIT_SHIFT	0x0UL
    145. 

  145. #define CC_SRAM_DATA_READY_VALUE_BIT_SIZE	0x1UL
    146. 

  146. 

  147. #endif //__CC_HOST_H__
    148. 

  148.