clk-tegra-fixed.c 2.8 KB

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  1. /*
  2. * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms and conditions of the GNU General Public License,
  6. * version 2, as published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope it will be useful, but WITHOUT
  9. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  11. * more details.
  12. *
  13. * You should have received a copy of the GNU General Public License
  14. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  15. */
  16. #include <linux/io.h>
  17. #include <linux/clk-provider.h>
  18. #include <linux/of.h>
  19. #include <linux/of_address.h>
  20. #include <linux/delay.h>
  21. #include <linux/export.h>
  22. #include <linux/clk/tegra.h>
  23. #include "clk.h"
  24. #include "clk-id.h"
  25. #define OSC_CTRL 0x50
  26. #define OSC_CTRL_OSC_FREQ_SHIFT 28
  27. #define OSC_CTRL_PLL_REF_DIV_SHIFT 26
  28. int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
  29. unsigned long *input_freqs, unsigned int num,
  30. unsigned int clk_m_div, unsigned long *osc_freq,
  31. unsigned long *pll_ref_freq)
  32. {
  33. struct clk *clk, *osc;
  34. struct clk **dt_clk;
  35. u32 val, pll_ref_div;
  36. unsigned osc_idx;
  37. val = readl_relaxed(clk_base + OSC_CTRL);
  38. osc_idx = val >> OSC_CTRL_OSC_FREQ_SHIFT;
  39. if (osc_idx < num)
  40. *osc_freq = input_freqs[osc_idx];
  41. else
  42. *osc_freq = 0;
  43. if (!*osc_freq) {
  44. WARN_ON(1);
  45. return -EINVAL;
  46. }
  47. osc = clk_register_fixed_rate(NULL, "osc", NULL, 0, *osc_freq);
  48. dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m, clks);
  49. if (!dt_clk)
  50. return 0;
  51. clk = clk_register_fixed_factor(NULL, "clk_m", "osc",
  52. 0, 1, clk_m_div);
  53. *dt_clk = clk;
  54. /* pll_ref */
  55. val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3;
  56. pll_ref_div = 1 << val;
  57. dt_clk = tegra_lookup_dt_id(tegra_clk_pll_ref, clks);
  58. if (!dt_clk)
  59. return 0;
  60. clk = clk_register_fixed_factor(NULL, "pll_ref", "osc",
  61. 0, 1, pll_ref_div);
  62. *dt_clk = clk;
  63. if (pll_ref_freq)
  64. *pll_ref_freq = *osc_freq / pll_ref_div;
  65. return 0;
  66. }
  67. void __init tegra_fixed_clk_init(struct tegra_clk *tegra_clks)
  68. {
  69. struct clk *clk;
  70. struct clk **dt_clk;
  71. /* clk_32k */
  72. dt_clk = tegra_lookup_dt_id(tegra_clk_clk_32k, tegra_clks);
  73. if (dt_clk) {
  74. clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, 0, 32768);
  75. *dt_clk = clk;
  76. }
  77. /* clk_m_div2 */
  78. dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m_div2, tegra_clks);
  79. if (dt_clk) {
  80. clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
  81. CLK_SET_RATE_PARENT, 1, 2);
  82. *dt_clk = clk;
  83. }
  84. /* clk_m_div4 */
  85. dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m_div4, tegra_clks);
  86. if (dt_clk) {
  87. clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
  88. CLK_SET_RATE_PARENT, 1, 4);
  89. *dt_clk = clk;
  90. }
  91. }