ali-agp.c 10 KB

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  1. /*
  2. * ALi AGPGART routines.
  3. */
  4. #include <linux/types.h>
  5. #include <linux/module.h>
  6. #include <linux/pci.h>
  7. #include <linux/init.h>
  8. #include <linux/agp_backend.h>
  9. #include <asm/page.h> /* PAGE_SIZE */
  10. #include "agp.h"
  11. #define ALI_AGPCTRL 0xb8
  12. #define ALI_ATTBASE 0xbc
  13. #define ALI_TLBCTRL 0xc0
  14. #define ALI_TAGCTRL 0xc4
  15. #define ALI_CACHE_FLUSH_CTRL 0xD0
  16. #define ALI_CACHE_FLUSH_ADDR_MASK 0xFFFFF000
  17. #define ALI_CACHE_FLUSH_EN 0x100
  18. static int ali_fetch_size(void)
  19. {
  20. int i;
  21. u32 temp;
  22. struct aper_size_info_32 *values;
  23. pci_read_config_dword(agp_bridge->dev, ALI_ATTBASE, &temp);
  24. temp &= ~(0xfffffff0);
  25. values = A_SIZE_32(agp_bridge->driver->aperture_sizes);
  26. for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
  27. if (temp == values[i].size_value) {
  28. agp_bridge->previous_size =
  29. agp_bridge->current_size = (void *) (values + i);
  30. agp_bridge->aperture_size_idx = i;
  31. return values[i].size;
  32. }
  33. }
  34. return 0;
  35. }
  36. static void ali_tlbflush(struct agp_memory *mem)
  37. {
  38. u32 temp;
  39. pci_read_config_dword(agp_bridge->dev, ALI_TLBCTRL, &temp);
  40. temp &= 0xfffffff0;
  41. temp |= (1<<0 | 1<<1);
  42. pci_write_config_dword(agp_bridge->dev, ALI_TAGCTRL, temp);
  43. }
  44. static void ali_cleanup(void)
  45. {
  46. struct aper_size_info_32 *previous_size;
  47. u32 temp;
  48. previous_size = A_SIZE_32(agp_bridge->previous_size);
  49. pci_read_config_dword(agp_bridge->dev, ALI_TLBCTRL, &temp);
  50. // clear tag
  51. pci_write_config_dword(agp_bridge->dev, ALI_TAGCTRL,
  52. ((temp & 0xffffff00) | 0x00000001|0x00000002));
  53. pci_read_config_dword(agp_bridge->dev, ALI_ATTBASE, &temp);
  54. pci_write_config_dword(agp_bridge->dev, ALI_ATTBASE,
  55. ((temp & 0x00000ff0) | previous_size->size_value));
  56. }
  57. static int ali_configure(void)
  58. {
  59. u32 temp;
  60. struct aper_size_info_32 *current_size;
  61. current_size = A_SIZE_32(agp_bridge->current_size);
  62. /* aperture size and gatt addr */
  63. pci_read_config_dword(agp_bridge->dev, ALI_ATTBASE, &temp);
  64. temp = (((temp & 0x00000ff0) | (agp_bridge->gatt_bus_addr & 0xfffff000))
  65. | (current_size->size_value & 0xf));
  66. pci_write_config_dword(agp_bridge->dev, ALI_ATTBASE, temp);
  67. /* tlb control */
  68. pci_read_config_dword(agp_bridge->dev, ALI_TLBCTRL, &temp);
  69. pci_write_config_dword(agp_bridge->dev, ALI_TLBCTRL, ((temp & 0xffffff00) | 0x00000010));
  70. /* address to map to */
  71. agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
  72. AGP_APERTURE_BAR);
  73. #if 0
  74. if (agp_bridge->type == ALI_M1541) {
  75. u32 nlvm_addr = 0;
  76. switch (current_size->size_value) {
  77. case 0: break;
  78. case 1: nlvm_addr = 0x100000;break;
  79. case 2: nlvm_addr = 0x200000;break;
  80. case 3: nlvm_addr = 0x400000;break;
  81. case 4: nlvm_addr = 0x800000;break;
  82. case 6: nlvm_addr = 0x1000000;break;
  83. case 7: nlvm_addr = 0x2000000;break;
  84. case 8: nlvm_addr = 0x4000000;break;
  85. case 9: nlvm_addr = 0x8000000;break;
  86. case 10: nlvm_addr = 0x10000000;break;
  87. default: break;
  88. }
  89. nlvm_addr--;
  90. nlvm_addr&=0xfff00000;
  91. nlvm_addr+= agp_bridge->gart_bus_addr;
  92. nlvm_addr|=(agp_bridge->gart_bus_addr>>12);
  93. dev_info(&agp_bridge->dev->dev, "nlvm top &base = %8x\n",
  94. nlvm_addr);
  95. }
  96. #endif
  97. pci_read_config_dword(agp_bridge->dev, ALI_TLBCTRL, &temp);
  98. temp &= 0xffffff7f; //enable TLB
  99. pci_write_config_dword(agp_bridge->dev, ALI_TLBCTRL, temp);
  100. return 0;
  101. }
  102. static void m1541_cache_flush(void)
  103. {
  104. int i, page_count;
  105. u32 temp;
  106. global_cache_flush();
  107. page_count = 1 << A_SIZE_32(agp_bridge->current_size)->page_order;
  108. for (i = 0; i < PAGE_SIZE * page_count; i += PAGE_SIZE) {
  109. pci_read_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL,
  110. &temp);
  111. pci_write_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL,
  112. (((temp & ALI_CACHE_FLUSH_ADDR_MASK) |
  113. (agp_bridge->gatt_bus_addr + i)) |
  114. ALI_CACHE_FLUSH_EN));
  115. }
  116. }
  117. static struct page *m1541_alloc_page(struct agp_bridge_data *bridge)
  118. {
  119. struct page *page = agp_generic_alloc_page(agp_bridge);
  120. u32 temp;
  121. if (!page)
  122. return NULL;
  123. pci_read_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL, &temp);
  124. pci_write_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL,
  125. (((temp & ALI_CACHE_FLUSH_ADDR_MASK) |
  126. page_to_phys(page)) | ALI_CACHE_FLUSH_EN ));
  127. return page;
  128. }
  129. static void ali_destroy_page(struct page *page, int flags)
  130. {
  131. if (page) {
  132. if (flags & AGP_PAGE_DESTROY_UNMAP) {
  133. global_cache_flush(); /* is this really needed? --hch */
  134. agp_generic_destroy_page(page, flags);
  135. } else
  136. agp_generic_destroy_page(page, flags);
  137. }
  138. }
  139. static void m1541_destroy_page(struct page *page, int flags)
  140. {
  141. u32 temp;
  142. if (page == NULL)
  143. return;
  144. if (flags & AGP_PAGE_DESTROY_UNMAP) {
  145. global_cache_flush();
  146. pci_read_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL, &temp);
  147. pci_write_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL,
  148. (((temp & ALI_CACHE_FLUSH_ADDR_MASK) |
  149. page_to_phys(page)) | ALI_CACHE_FLUSH_EN));
  150. }
  151. agp_generic_destroy_page(page, flags);
  152. }
  153. /* Setup function */
  154. static const struct aper_size_info_32 ali_generic_sizes[7] =
  155. {
  156. {256, 65536, 6, 10},
  157. {128, 32768, 5, 9},
  158. {64, 16384, 4, 8},
  159. {32, 8192, 3, 7},
  160. {16, 4096, 2, 6},
  161. {8, 2048, 1, 4},
  162. {4, 1024, 0, 3}
  163. };
  164. static const struct agp_bridge_driver ali_generic_bridge = {
  165. .owner = THIS_MODULE,
  166. .aperture_sizes = ali_generic_sizes,
  167. .size_type = U32_APER_SIZE,
  168. .num_aperture_sizes = 7,
  169. .needs_scratch_page = true,
  170. .configure = ali_configure,
  171. .fetch_size = ali_fetch_size,
  172. .cleanup = ali_cleanup,
  173. .tlb_flush = ali_tlbflush,
  174. .mask_memory = agp_generic_mask_memory,
  175. .masks = NULL,
  176. .agp_enable = agp_generic_enable,
  177. .cache_flush = global_cache_flush,
  178. .create_gatt_table = agp_generic_create_gatt_table,
  179. .free_gatt_table = agp_generic_free_gatt_table,
  180. .insert_memory = agp_generic_insert_memory,
  181. .remove_memory = agp_generic_remove_memory,
  182. .alloc_by_type = agp_generic_alloc_by_type,
  183. .free_by_type = agp_generic_free_by_type,
  184. .agp_alloc_page = agp_generic_alloc_page,
  185. .agp_destroy_page = ali_destroy_page,
  186. .agp_type_to_mask_type = agp_generic_type_to_mask_type,
  187. };
  188. static const struct agp_bridge_driver ali_m1541_bridge = {
  189. .owner = THIS_MODULE,
  190. .aperture_sizes = ali_generic_sizes,
  191. .size_type = U32_APER_SIZE,
  192. .num_aperture_sizes = 7,
  193. .configure = ali_configure,
  194. .fetch_size = ali_fetch_size,
  195. .cleanup = ali_cleanup,
  196. .tlb_flush = ali_tlbflush,
  197. .mask_memory = agp_generic_mask_memory,
  198. .masks = NULL,
  199. .agp_enable = agp_generic_enable,
  200. .cache_flush = m1541_cache_flush,
  201. .create_gatt_table = agp_generic_create_gatt_table,
  202. .free_gatt_table = agp_generic_free_gatt_table,
  203. .insert_memory = agp_generic_insert_memory,
  204. .remove_memory = agp_generic_remove_memory,
  205. .alloc_by_type = agp_generic_alloc_by_type,
  206. .free_by_type = agp_generic_free_by_type,
  207. .agp_alloc_page = m1541_alloc_page,
  208. .agp_destroy_page = m1541_destroy_page,
  209. .agp_type_to_mask_type = agp_generic_type_to_mask_type,
  210. };
  211. static struct agp_device_ids ali_agp_device_ids[] =
  212. {
  213. {
  214. .device_id = PCI_DEVICE_ID_AL_M1541,
  215. .chipset_name = "M1541",
  216. },
  217. {
  218. .device_id = PCI_DEVICE_ID_AL_M1621,
  219. .chipset_name = "M1621",
  220. },
  221. {
  222. .device_id = PCI_DEVICE_ID_AL_M1631,
  223. .chipset_name = "M1631",
  224. },
  225. {
  226. .device_id = PCI_DEVICE_ID_AL_M1632,
  227. .chipset_name = "M1632",
  228. },
  229. {
  230. .device_id = PCI_DEVICE_ID_AL_M1641,
  231. .chipset_name = "M1641",
  232. },
  233. {
  234. .device_id = PCI_DEVICE_ID_AL_M1644,
  235. .chipset_name = "M1644",
  236. },
  237. {
  238. .device_id = PCI_DEVICE_ID_AL_M1647,
  239. .chipset_name = "M1647",
  240. },
  241. {
  242. .device_id = PCI_DEVICE_ID_AL_M1651,
  243. .chipset_name = "M1651",
  244. },
  245. {
  246. .device_id = PCI_DEVICE_ID_AL_M1671,
  247. .chipset_name = "M1671",
  248. },
  249. {
  250. .device_id = PCI_DEVICE_ID_AL_M1681,
  251. .chipset_name = "M1681",
  252. },
  253. {
  254. .device_id = PCI_DEVICE_ID_AL_M1683,
  255. .chipset_name = "M1683",
  256. },
  257. { }, /* dummy final entry, always present */
  258. };
  259. static int agp_ali_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  260. {
  261. struct agp_device_ids *devs = ali_agp_device_ids;
  262. struct agp_bridge_data *bridge;
  263. u8 hidden_1621_id, cap_ptr;
  264. int j;
  265. cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
  266. if (!cap_ptr)
  267. return -ENODEV;
  268. /* probe for known chipsets */
  269. for (j = 0; devs[j].chipset_name; j++) {
  270. if (pdev->device == devs[j].device_id)
  271. goto found;
  272. }
  273. dev_err(&pdev->dev, "unsupported ALi chipset [%04x/%04x])\n",
  274. pdev->vendor, pdev->device);
  275. return -ENODEV;
  276. found:
  277. bridge = agp_alloc_bridge();
  278. if (!bridge)
  279. return -ENOMEM;
  280. bridge->dev = pdev;
  281. bridge->capndx = cap_ptr;
  282. switch (pdev->device) {
  283. case PCI_DEVICE_ID_AL_M1541:
  284. bridge->driver = &ali_m1541_bridge;
  285. break;
  286. case PCI_DEVICE_ID_AL_M1621:
  287. pci_read_config_byte(pdev, 0xFB, &hidden_1621_id);
  288. switch (hidden_1621_id) {
  289. case 0x31:
  290. devs[j].chipset_name = "M1631";
  291. break;
  292. case 0x32:
  293. devs[j].chipset_name = "M1632";
  294. break;
  295. case 0x41:
  296. devs[j].chipset_name = "M1641";
  297. break;
  298. case 0x43:
  299. devs[j].chipset_name = "M1621";
  300. break;
  301. case 0x47:
  302. devs[j].chipset_name = "M1647";
  303. break;
  304. case 0x51:
  305. devs[j].chipset_name = "M1651";
  306. break;
  307. default:
  308. break;
  309. }
  310. /*FALLTHROUGH*/
  311. default:
  312. bridge->driver = &ali_generic_bridge;
  313. }
  314. dev_info(&pdev->dev, "ALi %s chipset\n", devs[j].chipset_name);
  315. /* Fill in the mode register */
  316. pci_read_config_dword(pdev,
  317. bridge->capndx+PCI_AGP_STATUS,
  318. &bridge->mode);
  319. pci_set_drvdata(pdev, bridge);
  320. return agp_add_bridge(bridge);
  321. }
  322. static void agp_ali_remove(struct pci_dev *pdev)
  323. {
  324. struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
  325. agp_remove_bridge(bridge);
  326. agp_put_bridge(bridge);
  327. }
  328. static const struct pci_device_id agp_ali_pci_table[] = {
  329. {
  330. .class = (PCI_CLASS_BRIDGE_HOST << 8),
  331. .class_mask = ~0,
  332. .vendor = PCI_VENDOR_ID_AL,
  333. .device = PCI_ANY_ID,
  334. .subvendor = PCI_ANY_ID,
  335. .subdevice = PCI_ANY_ID,
  336. },
  337. { }
  338. };
  339. MODULE_DEVICE_TABLE(pci, agp_ali_pci_table);
  340. static struct pci_driver agp_ali_pci_driver = {
  341. .name = "agpgart-ali",
  342. .id_table = agp_ali_pci_table,
  343. .probe = agp_ali_probe,
  344. .remove = agp_ali_remove,
  345. };
  346. static int __init agp_ali_init(void)
  347. {
  348. if (agp_off)
  349. return -EINVAL;
  350. return pci_register_driver(&agp_ali_pci_driver);
  351. }
  352. static void __exit agp_ali_cleanup(void)
  353. {
  354. pci_unregister_driver(&agp_ali_pci_driver);
  355. }
  356. module_init(agp_ali_init);
  357. module_exit(agp_ali_cleanup);
  358. MODULE_AUTHOR("Dave Jones");
  359. MODULE_LICENSE("GPL and additional rights");