regmap-mmio.c 8.2 KB

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  1. /*
  2. * Register map access API - MMIO support
  3. *
  4. * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms and conditions of the GNU General Public License,
  8. * version 2, as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #include <linux/clk.h>
  19. #include <linux/err.h>
  20. #include <linux/io.h>
  21. #include <linux/module.h>
  22. #include <linux/regmap.h>
  23. #include <linux/slab.h>
  24. #include "internal.h"
  25. struct regmap_mmio_context {
  26. void __iomem *regs;
  27. unsigned val_bytes;
  28. bool attached_clk;
  29. struct clk *clk;
  30. void (*reg_write)(struct regmap_mmio_context *ctx,
  31. unsigned int reg, unsigned int val);
  32. unsigned int (*reg_read)(struct regmap_mmio_context *ctx,
  33. unsigned int reg);
  34. };
  35. static int regmap_mmio_regbits_check(size_t reg_bits)
  36. {
  37. switch (reg_bits) {
  38. case 8:
  39. case 16:
  40. case 32:
  41. #ifdef CONFIG_64BIT
  42. case 64:
  43. #endif
  44. return 0;
  45. default:
  46. return -EINVAL;
  47. }
  48. }
  49. static int regmap_mmio_get_min_stride(size_t val_bits)
  50. {
  51. int min_stride;
  52. switch (val_bits) {
  53. case 8:
  54. /* The core treats 0 as 1 */
  55. min_stride = 0;
  56. return 0;
  57. case 16:
  58. min_stride = 2;
  59. break;
  60. case 32:
  61. min_stride = 4;
  62. break;
  63. #ifdef CONFIG_64BIT
  64. case 64:
  65. min_stride = 8;
  66. break;
  67. #endif
  68. default:
  69. return -EINVAL;
  70. }
  71. return min_stride;
  72. }
  73. static void regmap_mmio_write8(struct regmap_mmio_context *ctx,
  74. unsigned int reg,
  75. unsigned int val)
  76. {
  77. writeb(val, ctx->regs + reg);
  78. }
  79. static void regmap_mmio_write16le(struct regmap_mmio_context *ctx,
  80. unsigned int reg,
  81. unsigned int val)
  82. {
  83. writew(val, ctx->regs + reg);
  84. }
  85. static void regmap_mmio_write16be(struct regmap_mmio_context *ctx,
  86. unsigned int reg,
  87. unsigned int val)
  88. {
  89. iowrite16be(val, ctx->regs + reg);
  90. }
  91. static void regmap_mmio_write32le(struct regmap_mmio_context *ctx,
  92. unsigned int reg,
  93. unsigned int val)
  94. {
  95. writel(val, ctx->regs + reg);
  96. }
  97. static void regmap_mmio_write32be(struct regmap_mmio_context *ctx,
  98. unsigned int reg,
  99. unsigned int val)
  100. {
  101. iowrite32be(val, ctx->regs + reg);
  102. }
  103. #ifdef CONFIG_64BIT
  104. static void regmap_mmio_write64le(struct regmap_mmio_context *ctx,
  105. unsigned int reg,
  106. unsigned int val)
  107. {
  108. writeq(val, ctx->regs + reg);
  109. }
  110. #endif
  111. static int regmap_mmio_write(void *context, unsigned int reg, unsigned int val)
  112. {
  113. struct regmap_mmio_context *ctx = context;
  114. int ret;
  115. if (!IS_ERR(ctx->clk)) {
  116. ret = clk_enable(ctx->clk);
  117. if (ret < 0)
  118. return ret;
  119. }
  120. ctx->reg_write(ctx, reg, val);
  121. if (!IS_ERR(ctx->clk))
  122. clk_disable(ctx->clk);
  123. return 0;
  124. }
  125. static unsigned int regmap_mmio_read8(struct regmap_mmio_context *ctx,
  126. unsigned int reg)
  127. {
  128. return readb(ctx->regs + reg);
  129. }
  130. static unsigned int regmap_mmio_read16le(struct regmap_mmio_context *ctx,
  131. unsigned int reg)
  132. {
  133. return readw(ctx->regs + reg);
  134. }
  135. static unsigned int regmap_mmio_read16be(struct regmap_mmio_context *ctx,
  136. unsigned int reg)
  137. {
  138. return ioread16be(ctx->regs + reg);
  139. }
  140. static unsigned int regmap_mmio_read32le(struct regmap_mmio_context *ctx,
  141. unsigned int reg)
  142. {
  143. return readl(ctx->regs + reg);
  144. }
  145. static unsigned int regmap_mmio_read32be(struct regmap_mmio_context *ctx,
  146. unsigned int reg)
  147. {
  148. return ioread32be(ctx->regs + reg);
  149. }
  150. #ifdef CONFIG_64BIT
  151. static unsigned int regmap_mmio_read64le(struct regmap_mmio_context *ctx,
  152. unsigned int reg)
  153. {
  154. return readq(ctx->regs + reg);
  155. }
  156. #endif
  157. static int regmap_mmio_read(void *context, unsigned int reg, unsigned int *val)
  158. {
  159. struct regmap_mmio_context *ctx = context;
  160. int ret;
  161. if (!IS_ERR(ctx->clk)) {
  162. ret = clk_enable(ctx->clk);
  163. if (ret < 0)
  164. return ret;
  165. }
  166. *val = ctx->reg_read(ctx, reg);
  167. if (!IS_ERR(ctx->clk))
  168. clk_disable(ctx->clk);
  169. return 0;
  170. }
  171. static void regmap_mmio_free_context(void *context)
  172. {
  173. struct regmap_mmio_context *ctx = context;
  174. if (!IS_ERR(ctx->clk)) {
  175. clk_unprepare(ctx->clk);
  176. if (!ctx->attached_clk)
  177. clk_put(ctx->clk);
  178. }
  179. kfree(context);
  180. }
  181. static const struct regmap_bus regmap_mmio = {
  182. .fast_io = true,
  183. .reg_write = regmap_mmio_write,
  184. .reg_read = regmap_mmio_read,
  185. .free_context = regmap_mmio_free_context,
  186. .val_format_endian_default = REGMAP_ENDIAN_LITTLE,
  187. };
  188. static struct regmap_mmio_context *regmap_mmio_gen_context(struct device *dev,
  189. const char *clk_id,
  190. void __iomem *regs,
  191. const struct regmap_config *config)
  192. {
  193. struct regmap_mmio_context *ctx;
  194. int min_stride;
  195. int ret;
  196. ret = regmap_mmio_regbits_check(config->reg_bits);
  197. if (ret)
  198. return ERR_PTR(ret);
  199. if (config->pad_bits)
  200. return ERR_PTR(-EINVAL);
  201. min_stride = regmap_mmio_get_min_stride(config->val_bits);
  202. if (min_stride < 0)
  203. return ERR_PTR(min_stride);
  204. if (config->reg_stride < min_stride)
  205. return ERR_PTR(-EINVAL);
  206. ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
  207. if (!ctx)
  208. return ERR_PTR(-ENOMEM);
  209. ctx->regs = regs;
  210. ctx->val_bytes = config->val_bits / 8;
  211. ctx->clk = ERR_PTR(-ENODEV);
  212. switch (regmap_get_val_endian(dev, &regmap_mmio, config)) {
  213. case REGMAP_ENDIAN_DEFAULT:
  214. case REGMAP_ENDIAN_LITTLE:
  215. #ifdef __LITTLE_ENDIAN
  216. case REGMAP_ENDIAN_NATIVE:
  217. #endif
  218. switch (config->val_bits) {
  219. case 8:
  220. ctx->reg_read = regmap_mmio_read8;
  221. ctx->reg_write = regmap_mmio_write8;
  222. break;
  223. case 16:
  224. ctx->reg_read = regmap_mmio_read16le;
  225. ctx->reg_write = regmap_mmio_write16le;
  226. break;
  227. case 32:
  228. ctx->reg_read = regmap_mmio_read32le;
  229. ctx->reg_write = regmap_mmio_write32le;
  230. break;
  231. #ifdef CONFIG_64BIT
  232. case 64:
  233. ctx->reg_read = regmap_mmio_read64le;
  234. ctx->reg_write = regmap_mmio_write64le;
  235. break;
  236. #endif
  237. default:
  238. ret = -EINVAL;
  239. goto err_free;
  240. }
  241. break;
  242. case REGMAP_ENDIAN_BIG:
  243. #ifdef __BIG_ENDIAN
  244. case REGMAP_ENDIAN_NATIVE:
  245. #endif
  246. switch (config->val_bits) {
  247. case 8:
  248. ctx->reg_read = regmap_mmio_read8;
  249. ctx->reg_write = regmap_mmio_write8;
  250. break;
  251. case 16:
  252. ctx->reg_read = regmap_mmio_read16be;
  253. ctx->reg_write = regmap_mmio_write16be;
  254. break;
  255. case 32:
  256. ctx->reg_read = regmap_mmio_read32be;
  257. ctx->reg_write = regmap_mmio_write32be;
  258. break;
  259. default:
  260. ret = -EINVAL;
  261. goto err_free;
  262. }
  263. break;
  264. default:
  265. ret = -EINVAL;
  266. goto err_free;
  267. }
  268. if (clk_id == NULL)
  269. return ctx;
  270. ctx->clk = clk_get(dev, clk_id);
  271. if (IS_ERR(ctx->clk)) {
  272. ret = PTR_ERR(ctx->clk);
  273. goto err_free;
  274. }
  275. ret = clk_prepare(ctx->clk);
  276. if (ret < 0) {
  277. clk_put(ctx->clk);
  278. goto err_free;
  279. }
  280. return ctx;
  281. err_free:
  282. kfree(ctx);
  283. return ERR_PTR(ret);
  284. }
  285. struct regmap *__regmap_init_mmio_clk(struct device *dev, const char *clk_id,
  286. void __iomem *regs,
  287. const struct regmap_config *config,
  288. struct lock_class_key *lock_key,
  289. const char *lock_name)
  290. {
  291. struct regmap_mmio_context *ctx;
  292. ctx = regmap_mmio_gen_context(dev, clk_id, regs, config);
  293. if (IS_ERR(ctx))
  294. return ERR_CAST(ctx);
  295. return __regmap_init(dev, &regmap_mmio, ctx, config,
  296. lock_key, lock_name);
  297. }
  298. EXPORT_SYMBOL_GPL(__regmap_init_mmio_clk);
  299. struct regmap *__devm_regmap_init_mmio_clk(struct device *dev,
  300. const char *clk_id,
  301. void __iomem *regs,
  302. const struct regmap_config *config,
  303. struct lock_class_key *lock_key,
  304. const char *lock_name)
  305. {
  306. struct regmap_mmio_context *ctx;
  307. ctx = regmap_mmio_gen_context(dev, clk_id, regs, config);
  308. if (IS_ERR(ctx))
  309. return ERR_CAST(ctx);
  310. return __devm_regmap_init(dev, &regmap_mmio, ctx, config,
  311. lock_key, lock_name);
  312. }
  313. EXPORT_SYMBOL_GPL(__devm_regmap_init_mmio_clk);
  314. int regmap_mmio_attach_clk(struct regmap *map, struct clk *clk)
  315. {
  316. struct regmap_mmio_context *ctx = map->bus_context;
  317. ctx->clk = clk;
  318. ctx->attached_clk = true;
  319. return clk_prepare(ctx->clk);
  320. }
  321. EXPORT_SYMBOL_GPL(regmap_mmio_attach_clk);
  322. void regmap_mmio_detach_clk(struct regmap *map)
  323. {
  324. struct regmap_mmio_context *ctx = map->bus_context;
  325. clk_unprepare(ctx->clk);
  326. ctx->attached_clk = false;
  327. ctx->clk = NULL;
  328. }
  329. EXPORT_SYMBOL_GPL(regmap_mmio_detach_clk);
  330. MODULE_LICENSE("GPL v2");