pata_hpt37x.c 25 KB

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  1. /*
  2. * Libata driver for the highpoint 37x and 30x UDMA66 ATA controllers.
  3. *
  4. * This driver is heavily based upon:
  5. *
  6. * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
  7. *
  8. * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
  9. * Portions Copyright (C) 2001 Sun Microsystems, Inc.
  10. * Portions Copyright (C) 2003 Red Hat Inc
  11. * Portions Copyright (C) 2005-2010 MontaVista Software, Inc.
  12. *
  13. * TODO
  14. * Look into engine reset on timeout errors. Should not be required.
  15. */
  16. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  17. #include <linux/kernel.h>
  18. #include <linux/module.h>
  19. #include <linux/pci.h>
  20. #include <linux/blkdev.h>
  21. #include <linux/delay.h>
  22. #include <scsi/scsi_host.h>
  23. #include <linux/libata.h>
  24. #define DRV_NAME "pata_hpt37x"
  25. #define DRV_VERSION "0.6.23"
  26. struct hpt_clock {
  27. u8 xfer_speed;
  28. u32 timing;
  29. };
  30. struct hpt_chip {
  31. const char *name;
  32. unsigned int base;
  33. struct hpt_clock const *clocks[4];
  34. };
  35. /* key for bus clock timings
  36. * bit
  37. * 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
  38. * cycles = value + 1
  39. * 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
  40. * cycles = value + 1
  41. * 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
  42. * register access.
  43. * 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
  44. * register access.
  45. * 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
  46. * 21 CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock.
  47. * 22:24 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
  48. * 25:27 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
  49. * register access.
  50. * 28 UDMA enable.
  51. * 29 DMA enable.
  52. * 30 PIO_MST enable. If set, the chip is in bus master mode during
  53. * PIO xfer.
  54. * 31 FIFO enable. Only for PIO.
  55. */
  56. static struct hpt_clock hpt37x_timings_33[] = {
  57. { XFER_UDMA_6, 0x12446231 }, /* 0x12646231 ?? */
  58. { XFER_UDMA_5, 0x12446231 },
  59. { XFER_UDMA_4, 0x12446231 },
  60. { XFER_UDMA_3, 0x126c6231 },
  61. { XFER_UDMA_2, 0x12486231 },
  62. { XFER_UDMA_1, 0x124c6233 },
  63. { XFER_UDMA_0, 0x12506297 },
  64. { XFER_MW_DMA_2, 0x22406c31 },
  65. { XFER_MW_DMA_1, 0x22406c33 },
  66. { XFER_MW_DMA_0, 0x22406c97 },
  67. { XFER_PIO_4, 0x06414e31 },
  68. { XFER_PIO_3, 0x06414e42 },
  69. { XFER_PIO_2, 0x06414e53 },
  70. { XFER_PIO_1, 0x06814e93 },
  71. { XFER_PIO_0, 0x06814ea7 }
  72. };
  73. static struct hpt_clock hpt37x_timings_50[] = {
  74. { XFER_UDMA_6, 0x12848242 },
  75. { XFER_UDMA_5, 0x12848242 },
  76. { XFER_UDMA_4, 0x12ac8242 },
  77. { XFER_UDMA_3, 0x128c8242 },
  78. { XFER_UDMA_2, 0x120c8242 },
  79. { XFER_UDMA_1, 0x12148254 },
  80. { XFER_UDMA_0, 0x121882ea },
  81. { XFER_MW_DMA_2, 0x22808242 },
  82. { XFER_MW_DMA_1, 0x22808254 },
  83. { XFER_MW_DMA_0, 0x228082ea },
  84. { XFER_PIO_4, 0x0a81f442 },
  85. { XFER_PIO_3, 0x0a81f443 },
  86. { XFER_PIO_2, 0x0a81f454 },
  87. { XFER_PIO_1, 0x0ac1f465 },
  88. { XFER_PIO_0, 0x0ac1f48a }
  89. };
  90. static struct hpt_clock hpt37x_timings_66[] = {
  91. { XFER_UDMA_6, 0x1c869c62 },
  92. { XFER_UDMA_5, 0x1cae9c62 }, /* 0x1c8a9c62 */
  93. { XFER_UDMA_4, 0x1c8a9c62 },
  94. { XFER_UDMA_3, 0x1c8e9c62 },
  95. { XFER_UDMA_2, 0x1c929c62 },
  96. { XFER_UDMA_1, 0x1c9a9c62 },
  97. { XFER_UDMA_0, 0x1c829c62 },
  98. { XFER_MW_DMA_2, 0x2c829c62 },
  99. { XFER_MW_DMA_1, 0x2c829c66 },
  100. { XFER_MW_DMA_0, 0x2c829d2e },
  101. { XFER_PIO_4, 0x0c829c62 },
  102. { XFER_PIO_3, 0x0c829c84 },
  103. { XFER_PIO_2, 0x0c829ca6 },
  104. { XFER_PIO_1, 0x0d029d26 },
  105. { XFER_PIO_0, 0x0d029d5e }
  106. };
  107. static const struct hpt_chip hpt370 = {
  108. "HPT370",
  109. 48,
  110. {
  111. hpt37x_timings_33,
  112. NULL,
  113. NULL,
  114. NULL
  115. }
  116. };
  117. static const struct hpt_chip hpt370a = {
  118. "HPT370A",
  119. 48,
  120. {
  121. hpt37x_timings_33,
  122. NULL,
  123. hpt37x_timings_50,
  124. NULL
  125. }
  126. };
  127. static const struct hpt_chip hpt372 = {
  128. "HPT372",
  129. 55,
  130. {
  131. hpt37x_timings_33,
  132. NULL,
  133. hpt37x_timings_50,
  134. hpt37x_timings_66
  135. }
  136. };
  137. static const struct hpt_chip hpt302 = {
  138. "HPT302",
  139. 66,
  140. {
  141. hpt37x_timings_33,
  142. NULL,
  143. hpt37x_timings_50,
  144. hpt37x_timings_66
  145. }
  146. };
  147. static const struct hpt_chip hpt371 = {
  148. "HPT371",
  149. 66,
  150. {
  151. hpt37x_timings_33,
  152. NULL,
  153. hpt37x_timings_50,
  154. hpt37x_timings_66
  155. }
  156. };
  157. static const struct hpt_chip hpt372a = {
  158. "HPT372A",
  159. 66,
  160. {
  161. hpt37x_timings_33,
  162. NULL,
  163. hpt37x_timings_50,
  164. hpt37x_timings_66
  165. }
  166. };
  167. static const struct hpt_chip hpt374 = {
  168. "HPT374",
  169. 48,
  170. {
  171. hpt37x_timings_33,
  172. NULL,
  173. NULL,
  174. NULL
  175. }
  176. };
  177. /**
  178. * hpt37x_find_mode - reset the hpt37x bus
  179. * @ap: ATA port
  180. * @speed: transfer mode
  181. *
  182. * Return the 32bit register programming information for this channel
  183. * that matches the speed provided.
  184. */
  185. static u32 hpt37x_find_mode(struct ata_port *ap, int speed)
  186. {
  187. struct hpt_clock *clocks = ap->host->private_data;
  188. while (clocks->xfer_speed) {
  189. if (clocks->xfer_speed == speed)
  190. return clocks->timing;
  191. clocks++;
  192. }
  193. BUG();
  194. return 0xffffffffU; /* silence compiler warning */
  195. }
  196. static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr,
  197. const char * const list[])
  198. {
  199. unsigned char model_num[ATA_ID_PROD_LEN + 1];
  200. int i;
  201. ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
  202. i = match_string(list, -1, model_num);
  203. if (i >= 0) {
  204. pr_warn("%s is not supported for %s\n", modestr, list[i]);
  205. return 1;
  206. }
  207. return 0;
  208. }
  209. static const char * const bad_ata33[] = {
  210. "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3",
  211. "Maxtor 90845U3", "Maxtor 90650U2",
  212. "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5",
  213. "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
  214. "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6",
  215. "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
  216. "Maxtor 90510D4",
  217. "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
  218. "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7",
  219. "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
  220. "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5",
  221. "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
  222. NULL
  223. };
  224. static const char * const bad_ata100_5[] = {
  225. "IBM-DTLA-307075",
  226. "IBM-DTLA-307060",
  227. "IBM-DTLA-307045",
  228. "IBM-DTLA-307030",
  229. "IBM-DTLA-307020",
  230. "IBM-DTLA-307015",
  231. "IBM-DTLA-305040",
  232. "IBM-DTLA-305030",
  233. "IBM-DTLA-305020",
  234. "IC35L010AVER07-0",
  235. "IC35L020AVER07-0",
  236. "IC35L030AVER07-0",
  237. "IC35L040AVER07-0",
  238. "IC35L060AVER07-0",
  239. "WDC AC310200R",
  240. NULL
  241. };
  242. /**
  243. * hpt370_filter - mode selection filter
  244. * @adev: ATA device
  245. *
  246. * Block UDMA on devices that cause trouble with this controller.
  247. */
  248. static unsigned long hpt370_filter(struct ata_device *adev, unsigned long mask)
  249. {
  250. if (adev->class == ATA_DEV_ATA) {
  251. if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
  252. mask &= ~ATA_MASK_UDMA;
  253. if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
  254. mask &= ~(0xE0 << ATA_SHIFT_UDMA);
  255. }
  256. return mask;
  257. }
  258. /**
  259. * hpt370a_filter - mode selection filter
  260. * @adev: ATA device
  261. *
  262. * Block UDMA on devices that cause trouble with this controller.
  263. */
  264. static unsigned long hpt370a_filter(struct ata_device *adev, unsigned long mask)
  265. {
  266. if (adev->class == ATA_DEV_ATA) {
  267. if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
  268. mask &= ~(0xE0 << ATA_SHIFT_UDMA);
  269. }
  270. return mask;
  271. }
  272. /**
  273. * hpt372_filter - mode selection filter
  274. * @adev: ATA device
  275. * @mask: mode mask
  276. *
  277. * The Marvell bridge chips used on the HighPoint SATA cards do not seem
  278. * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
  279. */
  280. static unsigned long hpt372_filter(struct ata_device *adev, unsigned long mask)
  281. {
  282. if (ata_id_is_sata(adev->id))
  283. mask &= ~((0xE << ATA_SHIFT_UDMA) | ATA_MASK_MWDMA);
  284. return mask;
  285. }
  286. /**
  287. * hpt37x_cable_detect - Detect the cable type
  288. * @ap: ATA port to detect on
  289. *
  290. * Return the cable type attached to this port
  291. */
  292. static int hpt37x_cable_detect(struct ata_port *ap)
  293. {
  294. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  295. u8 scr2, ata66;
  296. pci_read_config_byte(pdev, 0x5B, &scr2);
  297. pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
  298. udelay(10); /* debounce */
  299. /* Cable register now active */
  300. pci_read_config_byte(pdev, 0x5A, &ata66);
  301. /* Restore state */
  302. pci_write_config_byte(pdev, 0x5B, scr2);
  303. if (ata66 & (2 >> ap->port_no))
  304. return ATA_CBL_PATA40;
  305. else
  306. return ATA_CBL_PATA80;
  307. }
  308. /**
  309. * hpt374_fn1_cable_detect - Detect the cable type
  310. * @ap: ATA port to detect on
  311. *
  312. * Return the cable type attached to this port
  313. */
  314. static int hpt374_fn1_cable_detect(struct ata_port *ap)
  315. {
  316. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  317. unsigned int mcrbase = 0x50 + 4 * ap->port_no;
  318. u16 mcr3;
  319. u8 ata66;
  320. /* Do the extra channel work */
  321. pci_read_config_word(pdev, mcrbase + 2, &mcr3);
  322. /* Set bit 15 of 0x52 to enable TCBLID as input */
  323. pci_write_config_word(pdev, mcrbase + 2, mcr3 | 0x8000);
  324. pci_read_config_byte(pdev, 0x5A, &ata66);
  325. /* Reset TCBLID/FCBLID to output */
  326. pci_write_config_word(pdev, mcrbase + 2, mcr3);
  327. if (ata66 & (2 >> ap->port_no))
  328. return ATA_CBL_PATA40;
  329. else
  330. return ATA_CBL_PATA80;
  331. }
  332. /**
  333. * hpt37x_pre_reset - reset the hpt37x bus
  334. * @link: ATA link to reset
  335. * @deadline: deadline jiffies for the operation
  336. *
  337. * Perform the initial reset handling for the HPT37x.
  338. */
  339. static int hpt37x_pre_reset(struct ata_link *link, unsigned long deadline)
  340. {
  341. struct ata_port *ap = link->ap;
  342. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  343. static const struct pci_bits hpt37x_enable_bits[] = {
  344. { 0x50, 1, 0x04, 0x04 },
  345. { 0x54, 1, 0x04, 0x04 }
  346. };
  347. if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no]))
  348. return -ENOENT;
  349. /* Reset the state machine */
  350. pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
  351. udelay(100);
  352. return ata_sff_prereset(link, deadline);
  353. }
  354. static void hpt370_set_mode(struct ata_port *ap, struct ata_device *adev,
  355. u8 mode)
  356. {
  357. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  358. u32 addr1, addr2;
  359. u32 reg, timing, mask;
  360. u8 fast;
  361. addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
  362. addr2 = 0x51 + 4 * ap->port_no;
  363. /* Fast interrupt prediction disable, hold off interrupt disable */
  364. pci_read_config_byte(pdev, addr2, &fast);
  365. fast &= ~0x02;
  366. fast |= 0x01;
  367. pci_write_config_byte(pdev, addr2, fast);
  368. /* Determine timing mask and find matching mode entry */
  369. if (mode < XFER_MW_DMA_0)
  370. mask = 0xcfc3ffff;
  371. else if (mode < XFER_UDMA_0)
  372. mask = 0x31c001ff;
  373. else
  374. mask = 0x303c0000;
  375. timing = hpt37x_find_mode(ap, mode);
  376. pci_read_config_dword(pdev, addr1, &reg);
  377. reg = (reg & ~mask) | (timing & mask);
  378. pci_write_config_dword(pdev, addr1, reg);
  379. }
  380. /**
  381. * hpt370_set_piomode - PIO setup
  382. * @ap: ATA interface
  383. * @adev: device on the interface
  384. *
  385. * Perform PIO mode setup.
  386. */
  387. static void hpt370_set_piomode(struct ata_port *ap, struct ata_device *adev)
  388. {
  389. hpt370_set_mode(ap, adev, adev->pio_mode);
  390. }
  391. /**
  392. * hpt370_set_dmamode - DMA timing setup
  393. * @ap: ATA interface
  394. * @adev: Device being configured
  395. *
  396. * Set up the channel for MWDMA or UDMA modes.
  397. */
  398. static void hpt370_set_dmamode(struct ata_port *ap, struct ata_device *adev)
  399. {
  400. hpt370_set_mode(ap, adev, adev->dma_mode);
  401. }
  402. /**
  403. * hpt370_bmdma_end - DMA engine stop
  404. * @qc: ATA command
  405. *
  406. * Work around the HPT370 DMA engine.
  407. */
  408. static void hpt370_bmdma_stop(struct ata_queued_cmd *qc)
  409. {
  410. struct ata_port *ap = qc->ap;
  411. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  412. void __iomem *bmdma = ap->ioaddr.bmdma_addr;
  413. u8 dma_stat = ioread8(bmdma + ATA_DMA_STATUS);
  414. u8 dma_cmd;
  415. if (dma_stat & ATA_DMA_ACTIVE) {
  416. udelay(20);
  417. dma_stat = ioread8(bmdma + ATA_DMA_STATUS);
  418. }
  419. if (dma_stat & ATA_DMA_ACTIVE) {
  420. /* Clear the engine */
  421. pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
  422. udelay(10);
  423. /* Stop DMA */
  424. dma_cmd = ioread8(bmdma + ATA_DMA_CMD);
  425. iowrite8(dma_cmd & ~ATA_DMA_START, bmdma + ATA_DMA_CMD);
  426. /* Clear Error */
  427. dma_stat = ioread8(bmdma + ATA_DMA_STATUS);
  428. iowrite8(dma_stat | ATA_DMA_INTR | ATA_DMA_ERR,
  429. bmdma + ATA_DMA_STATUS);
  430. /* Clear the engine */
  431. pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
  432. udelay(10);
  433. }
  434. ata_bmdma_stop(qc);
  435. }
  436. static void hpt372_set_mode(struct ata_port *ap, struct ata_device *adev,
  437. u8 mode)
  438. {
  439. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  440. u32 addr1, addr2;
  441. u32 reg, timing, mask;
  442. u8 fast;
  443. addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
  444. addr2 = 0x51 + 4 * ap->port_no;
  445. /* Fast interrupt prediction disable, hold off interrupt disable */
  446. pci_read_config_byte(pdev, addr2, &fast);
  447. fast &= ~0x07;
  448. pci_write_config_byte(pdev, addr2, fast);
  449. /* Determine timing mask and find matching mode entry */
  450. if (mode < XFER_MW_DMA_0)
  451. mask = 0xcfc3ffff;
  452. else if (mode < XFER_UDMA_0)
  453. mask = 0x31c001ff;
  454. else
  455. mask = 0x303c0000;
  456. timing = hpt37x_find_mode(ap, mode);
  457. pci_read_config_dword(pdev, addr1, &reg);
  458. reg = (reg & ~mask) | (timing & mask);
  459. pci_write_config_dword(pdev, addr1, reg);
  460. }
  461. /**
  462. * hpt372_set_piomode - PIO setup
  463. * @ap: ATA interface
  464. * @adev: device on the interface
  465. *
  466. * Perform PIO mode setup.
  467. */
  468. static void hpt372_set_piomode(struct ata_port *ap, struct ata_device *adev)
  469. {
  470. hpt372_set_mode(ap, adev, adev->pio_mode);
  471. }
  472. /**
  473. * hpt372_set_dmamode - DMA timing setup
  474. * @ap: ATA interface
  475. * @adev: Device being configured
  476. *
  477. * Set up the channel for MWDMA or UDMA modes.
  478. */
  479. static void hpt372_set_dmamode(struct ata_port *ap, struct ata_device *adev)
  480. {
  481. hpt372_set_mode(ap, adev, adev->dma_mode);
  482. }
  483. /**
  484. * hpt37x_bmdma_end - DMA engine stop
  485. * @qc: ATA command
  486. *
  487. * Clean up after the HPT372 and later DMA engine
  488. */
  489. static void hpt37x_bmdma_stop(struct ata_queued_cmd *qc)
  490. {
  491. struct ata_port *ap = qc->ap;
  492. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  493. int mscreg = 0x50 + 4 * ap->port_no;
  494. u8 bwsr_stat, msc_stat;
  495. pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
  496. pci_read_config_byte(pdev, mscreg, &msc_stat);
  497. if (bwsr_stat & (1 << ap->port_no))
  498. pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
  499. ata_bmdma_stop(qc);
  500. }
  501. static struct scsi_host_template hpt37x_sht = {
  502. ATA_BMDMA_SHT(DRV_NAME),
  503. };
  504. /*
  505. * Configuration for HPT370
  506. */
  507. static struct ata_port_operations hpt370_port_ops = {
  508. .inherits = &ata_bmdma_port_ops,
  509. .bmdma_stop = hpt370_bmdma_stop,
  510. .mode_filter = hpt370_filter,
  511. .cable_detect = hpt37x_cable_detect,
  512. .set_piomode = hpt370_set_piomode,
  513. .set_dmamode = hpt370_set_dmamode,
  514. .prereset = hpt37x_pre_reset,
  515. };
  516. /*
  517. * Configuration for HPT370A. Close to 370 but less filters
  518. */
  519. static struct ata_port_operations hpt370a_port_ops = {
  520. .inherits = &hpt370_port_ops,
  521. .mode_filter = hpt370a_filter,
  522. };
  523. /*
  524. * Configuration for HPT371 and HPT302. Slightly different PIO and DMA
  525. * mode setting functionality.
  526. */
  527. static struct ata_port_operations hpt302_port_ops = {
  528. .inherits = &ata_bmdma_port_ops,
  529. .bmdma_stop = hpt37x_bmdma_stop,
  530. .cable_detect = hpt37x_cable_detect,
  531. .set_piomode = hpt372_set_piomode,
  532. .set_dmamode = hpt372_set_dmamode,
  533. .prereset = hpt37x_pre_reset,
  534. };
  535. /*
  536. * Configuration for HPT372. Mode setting works like 371 and 302
  537. * but we have a mode filter.
  538. */
  539. static struct ata_port_operations hpt372_port_ops = {
  540. .inherits = &hpt302_port_ops,
  541. .mode_filter = hpt372_filter,
  542. };
  543. /*
  544. * Configuration for HPT374. Mode setting and filtering works like 372
  545. * but we have a different cable detection procedure for function 1.
  546. */
  547. static struct ata_port_operations hpt374_fn1_port_ops = {
  548. .inherits = &hpt372_port_ops,
  549. .cable_detect = hpt374_fn1_cable_detect,
  550. };
  551. /**
  552. * hpt37x_clock_slot - Turn timing to PC clock entry
  553. * @freq: Reported frequency timing
  554. * @base: Base timing
  555. *
  556. * Turn the timing data intoa clock slot (0 for 33, 1 for 40, 2 for 50
  557. * and 3 for 66Mhz)
  558. */
  559. static int hpt37x_clock_slot(unsigned int freq, unsigned int base)
  560. {
  561. unsigned int f = (base * freq) / 192; /* Mhz */
  562. if (f < 40)
  563. return 0; /* 33Mhz slot */
  564. if (f < 45)
  565. return 1; /* 40Mhz slot */
  566. if (f < 55)
  567. return 2; /* 50Mhz slot */
  568. return 3; /* 60Mhz slot */
  569. }
  570. /**
  571. * hpt37x_calibrate_dpll - Calibrate the DPLL loop
  572. * @dev: PCI device
  573. *
  574. * Perform a calibration cycle on the HPT37x DPLL. Returns 1 if this
  575. * succeeds
  576. */
  577. static int hpt37x_calibrate_dpll(struct pci_dev *dev)
  578. {
  579. u8 reg5b;
  580. u32 reg5c;
  581. int tries;
  582. for (tries = 0; tries < 0x5000; tries++) {
  583. udelay(50);
  584. pci_read_config_byte(dev, 0x5b, &reg5b);
  585. if (reg5b & 0x80) {
  586. /* See if it stays set */
  587. for (tries = 0; tries < 0x1000; tries++) {
  588. pci_read_config_byte(dev, 0x5b, &reg5b);
  589. /* Failed ? */
  590. if ((reg5b & 0x80) == 0)
  591. return 0;
  592. }
  593. /* Turn off tuning, we have the DPLL set */
  594. pci_read_config_dword(dev, 0x5c, &reg5c);
  595. pci_write_config_dword(dev, 0x5c, reg5c & ~0x100);
  596. return 1;
  597. }
  598. }
  599. /* Never went stable */
  600. return 0;
  601. }
  602. static u32 hpt374_read_freq(struct pci_dev *pdev)
  603. {
  604. u32 freq;
  605. unsigned long io_base = pci_resource_start(pdev, 4);
  606. if (PCI_FUNC(pdev->devfn) & 1) {
  607. struct pci_dev *pdev_0;
  608. pdev_0 = pci_get_slot(pdev->bus, pdev->devfn - 1);
  609. /* Someone hot plugged the controller on us ? */
  610. if (pdev_0 == NULL)
  611. return 0;
  612. io_base = pci_resource_start(pdev_0, 4);
  613. freq = inl(io_base + 0x90);
  614. pci_dev_put(pdev_0);
  615. } else
  616. freq = inl(io_base + 0x90);
  617. return freq;
  618. }
  619. /**
  620. * hpt37x_init_one - Initialise an HPT37X/302
  621. * @dev: PCI device
  622. * @id: Entry in match table
  623. *
  624. * Initialise an HPT37x device. There are some interesting complications
  625. * here. Firstly the chip may report 366 and be one of several variants.
  626. * Secondly all the timings depend on the clock for the chip which we must
  627. * detect and look up
  628. *
  629. * This is the known chip mappings. It may be missing a couple of later
  630. * releases.
  631. *
  632. * Chip version PCI Rev Notes
  633. * HPT366 4 (HPT366) 0 Other driver
  634. * HPT366 4 (HPT366) 1 Other driver
  635. * HPT368 4 (HPT366) 2 Other driver
  636. * HPT370 4 (HPT366) 3 UDMA100
  637. * HPT370A 4 (HPT366) 4 UDMA100
  638. * HPT372 4 (HPT366) 5 UDMA133 (1)
  639. * HPT372N 4 (HPT366) 6 Other driver
  640. * HPT372A 5 (HPT372) 1 UDMA133 (1)
  641. * HPT372N 5 (HPT372) 2 Other driver
  642. * HPT302 6 (HPT302) 1 UDMA133
  643. * HPT302N 6 (HPT302) 2 Other driver
  644. * HPT371 7 (HPT371) * UDMA133
  645. * HPT374 8 (HPT374) * UDMA133 4 channel
  646. * HPT372N 9 (HPT372N) * Other driver
  647. *
  648. * (1) UDMA133 support depends on the bus clock
  649. */
  650. static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
  651. {
  652. /* HPT370 - UDMA100 */
  653. static const struct ata_port_info info_hpt370 = {
  654. .flags = ATA_FLAG_SLAVE_POSS,
  655. .pio_mask = ATA_PIO4,
  656. .mwdma_mask = ATA_MWDMA2,
  657. .udma_mask = ATA_UDMA5,
  658. .port_ops = &hpt370_port_ops
  659. };
  660. /* HPT370A - UDMA100 */
  661. static const struct ata_port_info info_hpt370a = {
  662. .flags = ATA_FLAG_SLAVE_POSS,
  663. .pio_mask = ATA_PIO4,
  664. .mwdma_mask = ATA_MWDMA2,
  665. .udma_mask = ATA_UDMA5,
  666. .port_ops = &hpt370a_port_ops
  667. };
  668. /* HPT370 - UDMA66 */
  669. static const struct ata_port_info info_hpt370_33 = {
  670. .flags = ATA_FLAG_SLAVE_POSS,
  671. .pio_mask = ATA_PIO4,
  672. .mwdma_mask = ATA_MWDMA2,
  673. .udma_mask = ATA_UDMA4,
  674. .port_ops = &hpt370_port_ops
  675. };
  676. /* HPT370A - UDMA66 */
  677. static const struct ata_port_info info_hpt370a_33 = {
  678. .flags = ATA_FLAG_SLAVE_POSS,
  679. .pio_mask = ATA_PIO4,
  680. .mwdma_mask = ATA_MWDMA2,
  681. .udma_mask = ATA_UDMA4,
  682. .port_ops = &hpt370a_port_ops
  683. };
  684. /* HPT372 - UDMA133 */
  685. static const struct ata_port_info info_hpt372 = {
  686. .flags = ATA_FLAG_SLAVE_POSS,
  687. .pio_mask = ATA_PIO4,
  688. .mwdma_mask = ATA_MWDMA2,
  689. .udma_mask = ATA_UDMA6,
  690. .port_ops = &hpt372_port_ops
  691. };
  692. /* HPT371, 302 - UDMA133 */
  693. static const struct ata_port_info info_hpt302 = {
  694. .flags = ATA_FLAG_SLAVE_POSS,
  695. .pio_mask = ATA_PIO4,
  696. .mwdma_mask = ATA_MWDMA2,
  697. .udma_mask = ATA_UDMA6,
  698. .port_ops = &hpt302_port_ops
  699. };
  700. /* HPT374 - UDMA100, function 1 uses different cable_detect method */
  701. static const struct ata_port_info info_hpt374_fn0 = {
  702. .flags = ATA_FLAG_SLAVE_POSS,
  703. .pio_mask = ATA_PIO4,
  704. .mwdma_mask = ATA_MWDMA2,
  705. .udma_mask = ATA_UDMA5,
  706. .port_ops = &hpt372_port_ops
  707. };
  708. static const struct ata_port_info info_hpt374_fn1 = {
  709. .flags = ATA_FLAG_SLAVE_POSS,
  710. .pio_mask = ATA_PIO4,
  711. .mwdma_mask = ATA_MWDMA2,
  712. .udma_mask = ATA_UDMA5,
  713. .port_ops = &hpt374_fn1_port_ops
  714. };
  715. static const int MHz[4] = { 33, 40, 50, 66 };
  716. void *private_data = NULL;
  717. const struct ata_port_info *ppi[] = { NULL, NULL };
  718. u8 rev = dev->revision;
  719. u8 irqmask;
  720. u8 mcr1;
  721. u32 freq;
  722. int prefer_dpll = 1;
  723. unsigned long iobase = pci_resource_start(dev, 4);
  724. const struct hpt_chip *chip_table;
  725. int clock_slot;
  726. int rc;
  727. rc = pcim_enable_device(dev);
  728. if (rc)
  729. return rc;
  730. switch (dev->device) {
  731. case PCI_DEVICE_ID_TTI_HPT366:
  732. /* May be a later chip in disguise. Check */
  733. /* Older chips are in the HPT366 driver. Ignore them */
  734. if (rev < 3)
  735. return -ENODEV;
  736. /* N series chips have their own driver. Ignore */
  737. if (rev == 6)
  738. return -ENODEV;
  739. switch (rev) {
  740. case 3:
  741. ppi[0] = &info_hpt370;
  742. chip_table = &hpt370;
  743. prefer_dpll = 0;
  744. break;
  745. case 4:
  746. ppi[0] = &info_hpt370a;
  747. chip_table = &hpt370a;
  748. prefer_dpll = 0;
  749. break;
  750. case 5:
  751. ppi[0] = &info_hpt372;
  752. chip_table = &hpt372;
  753. break;
  754. default:
  755. pr_err("Unknown HPT366 subtype, please report (%d)\n",
  756. rev);
  757. return -ENODEV;
  758. }
  759. break;
  760. case PCI_DEVICE_ID_TTI_HPT372:
  761. /* 372N if rev >= 2 */
  762. if (rev >= 2)
  763. return -ENODEV;
  764. ppi[0] = &info_hpt372;
  765. chip_table = &hpt372a;
  766. break;
  767. case PCI_DEVICE_ID_TTI_HPT302:
  768. /* 302N if rev > 1 */
  769. if (rev > 1)
  770. return -ENODEV;
  771. ppi[0] = &info_hpt302;
  772. /* Check this */
  773. chip_table = &hpt302;
  774. break;
  775. case PCI_DEVICE_ID_TTI_HPT371:
  776. if (rev > 1)
  777. return -ENODEV;
  778. ppi[0] = &info_hpt302;
  779. chip_table = &hpt371;
  780. /*
  781. * Single channel device, master is not present but the BIOS
  782. * (or us for non x86) must mark it absent
  783. */
  784. pci_read_config_byte(dev, 0x50, &mcr1);
  785. mcr1 &= ~0x04;
  786. pci_write_config_byte(dev, 0x50, mcr1);
  787. break;
  788. case PCI_DEVICE_ID_TTI_HPT374:
  789. chip_table = &hpt374;
  790. if (!(PCI_FUNC(dev->devfn) & 1))
  791. *ppi = &info_hpt374_fn0;
  792. else
  793. *ppi = &info_hpt374_fn1;
  794. break;
  795. default:
  796. pr_err("PCI table is bogus, please report (%d)\n", dev->device);
  797. return -ENODEV;
  798. }
  799. /* Ok so this is a chip we support */
  800. pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
  801. pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
  802. pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
  803. pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
  804. pci_read_config_byte(dev, 0x5A, &irqmask);
  805. irqmask &= ~0x10;
  806. pci_write_config_byte(dev, 0x5a, irqmask);
  807. /*
  808. * default to pci clock. make sure MA15/16 are set to output
  809. * to prevent drives having problems with 40-pin cables. Needed
  810. * for some drives such as IBM-DTLA which will not enter ready
  811. * state on reset when PDIAG is a input.
  812. */
  813. pci_write_config_byte(dev, 0x5b, 0x23);
  814. /*
  815. * HighPoint does this for HPT372A.
  816. * NOTE: This register is only writeable via I/O space.
  817. */
  818. if (chip_table == &hpt372a)
  819. outb(0x0e, iobase + 0x9c);
  820. /*
  821. * Some devices do not let this value be accessed via PCI space
  822. * according to the old driver. In addition we must use the value
  823. * from FN 0 on the HPT374.
  824. */
  825. if (chip_table == &hpt374) {
  826. freq = hpt374_read_freq(dev);
  827. if (freq == 0)
  828. return -ENODEV;
  829. } else
  830. freq = inl(iobase + 0x90);
  831. if ((freq >> 12) != 0xABCDE) {
  832. int i;
  833. u8 sr;
  834. u32 total = 0;
  835. pr_warn("BIOS has not set timing clocks\n");
  836. /* This is the process the HPT371 BIOS is reported to use */
  837. for (i = 0; i < 128; i++) {
  838. pci_read_config_byte(dev, 0x78, &sr);
  839. total += sr & 0x1FF;
  840. udelay(15);
  841. }
  842. freq = total / 128;
  843. }
  844. freq &= 0x1FF;
  845. /*
  846. * Turn the frequency check into a band and then find a timing
  847. * table to match it.
  848. */
  849. clock_slot = hpt37x_clock_slot(freq, chip_table->base);
  850. if (chip_table->clocks[clock_slot] == NULL || prefer_dpll) {
  851. /*
  852. * We need to try PLL mode instead
  853. *
  854. * For non UDMA133 capable devices we should
  855. * use a 50MHz DPLL by choice
  856. */
  857. unsigned int f_low, f_high;
  858. int dpll, adjust;
  859. /* Compute DPLL */
  860. dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2;
  861. f_low = (MHz[clock_slot] * 48) / MHz[dpll];
  862. f_high = f_low + 2;
  863. if (clock_slot > 1)
  864. f_high += 2;
  865. /* Select the DPLL clock. */
  866. pci_write_config_byte(dev, 0x5b, 0x21);
  867. pci_write_config_dword(dev, 0x5C,
  868. (f_high << 16) | f_low | 0x100);
  869. for (adjust = 0; adjust < 8; adjust++) {
  870. if (hpt37x_calibrate_dpll(dev))
  871. break;
  872. /*
  873. * See if it'll settle at a fractionally
  874. * different clock
  875. */
  876. if (adjust & 1)
  877. f_low -= adjust >> 1;
  878. else
  879. f_high += adjust >> 1;
  880. pci_write_config_dword(dev, 0x5C,
  881. (f_high << 16) | f_low | 0x100);
  882. }
  883. if (adjust == 8) {
  884. pr_err("DPLL did not stabilize!\n");
  885. return -ENODEV;
  886. }
  887. if (dpll == 3)
  888. private_data = (void *)hpt37x_timings_66;
  889. else
  890. private_data = (void *)hpt37x_timings_50;
  891. pr_info("bus clock %dMHz, using %dMHz DPLL\n",
  892. MHz[clock_slot], MHz[dpll]);
  893. } else {
  894. private_data = (void *)chip_table->clocks[clock_slot];
  895. /*
  896. * Perform a final fixup. Note that we will have used the
  897. * DPLL on the HPT372 which means we don't have to worry
  898. * about lack of UDMA133 support on lower clocks
  899. */
  900. if (clock_slot < 2 && ppi[0] == &info_hpt370)
  901. ppi[0] = &info_hpt370_33;
  902. if (clock_slot < 2 && ppi[0] == &info_hpt370a)
  903. ppi[0] = &info_hpt370a_33;
  904. pr_info("%s using %dMHz bus clock\n",
  905. chip_table->name, MHz[clock_slot]);
  906. }
  907. /* Now kick off ATA set up */
  908. return ata_pci_bmdma_init_one(dev, ppi, &hpt37x_sht, private_data, 0);
  909. }
  910. static const struct pci_device_id hpt37x[] = {
  911. { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
  912. { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
  913. { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
  914. { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), },
  915. { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
  916. { },
  917. };
  918. static struct pci_driver hpt37x_pci_driver = {
  919. .name = DRV_NAME,
  920. .id_table = hpt37x,
  921. .probe = hpt37x_init_one,
  922. .remove = ata_pci_remove_one
  923. };
  924. module_pci_driver(hpt37x_pci_driver);
  925. MODULE_AUTHOR("Alan Cox");
  926. MODULE_DESCRIPTION("low-level driver for the Highpoint HPT37x/30x");
  927. MODULE_LICENSE("GPL");
  928. MODULE_DEVICE_TABLE(pci, hpt37x);
  929. MODULE_VERSION(DRV_VERSION);