processor_32.h 4.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * include/asm-sh/processor.h
  4. *
  5. * Copyright (C) 1999, 2000 Niibe Yutaka
  6. * Copyright (C) 2002, 2003 Paul Mundt
  7. */
  8. #ifndef __ASM_SH_PROCESSOR_32_H
  9. #define __ASM_SH_PROCESSOR_32_H
  10. #ifdef __KERNEL__
  11. #include <linux/compiler.h>
  12. #include <linux/linkage.h>
  13. #include <asm/page.h>
  14. #include <asm/types.h>
  15. #include <asm/hw_breakpoint.h>
  16. /*
  17. * Default implementation of macro that returns current
  18. * instruction pointer ("program counter").
  19. */
  20. #define current_text_addr() ({ void *pc; __asm__("mova 1f, %0\n.align 2\n1:":"=z" (pc)); pc; })
  21. /* Core Processor Version Register */
  22. #define CCN_PVR 0xff000030
  23. #define CCN_CVR 0xff000040
  24. #define CCN_PRR 0xff000044
  25. /*
  26. * User space process size: 2GB.
  27. *
  28. * Since SH7709 and SH7750 have "area 7", we can't use 0x7c000000--0x7fffffff
  29. */
  30. #define TASK_SIZE 0x7c000000UL
  31. #define STACK_TOP TASK_SIZE
  32. #define STACK_TOP_MAX STACK_TOP
  33. /* This decides where the kernel will search for a free chunk of vm
  34. * space during mmap's.
  35. */
  36. #define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3)
  37. /*
  38. * Bit of SR register
  39. *
  40. * FD-bit:
  41. * When it's set, it means the processor doesn't have right to use FPU,
  42. * and it results exception when the floating operation is executed.
  43. *
  44. * IMASK-bit:
  45. * Interrupt level mask
  46. */
  47. #define SR_DSP 0x00001000
  48. #define SR_IMASK 0x000000f0
  49. #define SR_FD 0x00008000
  50. #define SR_MD 0x40000000
  51. /*
  52. * DSP structure and data
  53. */
  54. struct sh_dsp_struct {
  55. unsigned long dsp_regs[14];
  56. long status;
  57. };
  58. /*
  59. * FPU structure and data
  60. */
  61. struct sh_fpu_hard_struct {
  62. unsigned long fp_regs[16];
  63. unsigned long xfp_regs[16];
  64. unsigned long fpscr;
  65. unsigned long fpul;
  66. long status; /* software status information */
  67. };
  68. /* Dummy fpu emulator */
  69. struct sh_fpu_soft_struct {
  70. unsigned long fp_regs[16];
  71. unsigned long xfp_regs[16];
  72. unsigned long fpscr;
  73. unsigned long fpul;
  74. unsigned char lookahead;
  75. unsigned long entry_pc;
  76. };
  77. union thread_xstate {
  78. struct sh_fpu_hard_struct hardfpu;
  79. struct sh_fpu_soft_struct softfpu;
  80. };
  81. struct thread_struct {
  82. /* Saved registers when thread is descheduled */
  83. unsigned long sp;
  84. unsigned long pc;
  85. /* Various thread flags, see SH_THREAD_xxx */
  86. unsigned long flags;
  87. /* Save middle states of ptrace breakpoints */
  88. struct perf_event *ptrace_bps[HBP_NUM];
  89. #ifdef CONFIG_SH_DSP
  90. /* Dsp status information */
  91. struct sh_dsp_struct dsp_status;
  92. #endif
  93. /* Extended processor state */
  94. union thread_xstate *xstate;
  95. /*
  96. * fpu_counter contains the number of consecutive context switches
  97. * that the FPU is used. If this is over a threshold, the lazy fpu
  98. * saving becomes unlazy to save the trap. This is an unsigned char
  99. * so that after 256 times the counter wraps and the behavior turns
  100. * lazy again; this to deal with bursty apps that only use FPU for
  101. * a short time
  102. */
  103. unsigned char fpu_counter;
  104. };
  105. #define INIT_THREAD { \
  106. .sp = sizeof(init_stack) + (long) &init_stack, \
  107. .flags = 0, \
  108. }
  109. /* Forward declaration, a strange C thing */
  110. struct task_struct;
  111. extern void start_thread(struct pt_regs *regs, unsigned long new_pc, unsigned long new_sp);
  112. /* Free all resources held by a thread. */
  113. extern void release_thread(struct task_struct *);
  114. /*
  115. * FPU lazy state save handling.
  116. */
  117. static __inline__ void disable_fpu(void)
  118. {
  119. unsigned long __dummy;
  120. /* Set FD flag in SR */
  121. __asm__ __volatile__("stc sr, %0\n\t"
  122. "or %1, %0\n\t"
  123. "ldc %0, sr"
  124. : "=&r" (__dummy)
  125. : "r" (SR_FD));
  126. }
  127. static __inline__ void enable_fpu(void)
  128. {
  129. unsigned long __dummy;
  130. /* Clear out FD flag in SR */
  131. __asm__ __volatile__("stc sr, %0\n\t"
  132. "and %1, %0\n\t"
  133. "ldc %0, sr"
  134. : "=&r" (__dummy)
  135. : "r" (~SR_FD));
  136. }
  137. /* Double presision, NANS as NANS, rounding to nearest, no exceptions */
  138. #define FPSCR_INIT 0x00080000
  139. #define FPSCR_CAUSE_MASK 0x0001f000 /* Cause bits */
  140. #define FPSCR_FLAG_MASK 0x0000007c /* Flag bits */
  141. /*
  142. * Return saved PC of a blocked thread.
  143. */
  144. #define thread_saved_pc(tsk) (tsk->thread.pc)
  145. void show_trace(struct task_struct *tsk, unsigned long *sp,
  146. struct pt_regs *regs);
  147. #ifdef CONFIG_DUMP_CODE
  148. void show_code(struct pt_regs *regs);
  149. #else
  150. static inline void show_code(struct pt_regs *regs)
  151. {
  152. }
  153. #endif
  154. extern unsigned long get_wchan(struct task_struct *p);
  155. #define KSTK_EIP(tsk) (task_pt_regs(tsk)->pc)
  156. #define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[15])
  157. #if defined(CONFIG_CPU_SH2A) || defined(CONFIG_CPU_SH4)
  158. #define PREFETCH_STRIDE L1_CACHE_BYTES
  159. #define ARCH_HAS_PREFETCH
  160. #define ARCH_HAS_PREFETCHW
  161. static inline void prefetch(const void *x)
  162. {
  163. __builtin_prefetch(x, 0, 3);
  164. }
  165. static inline void prefetchw(const void *x)
  166. {
  167. __builtin_prefetch(x, 1, 3);
  168. }
  169. #endif
  170. #endif /* __KERNEL__ */
  171. #endif /* __ASM_SH_PROCESSOR_32_H */