spinlock.c 7.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Out of line spinlock code.
  4. *
  5. * Copyright IBM Corp. 2004, 2006
  6. * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
  7. */
  8. #include <linux/types.h>
  9. #include <linux/export.h>
  10. #include <linux/spinlock.h>
  11. #include <linux/jiffies.h>
  12. #include <linux/init.h>
  13. #include <linux/smp.h>
  14. #include <linux/percpu.h>
  15. #include <asm/alternative.h>
  16. #include <asm/io.h>
  17. int spin_retry = -1;
  18. static int __init spin_retry_init(void)
  19. {
  20. if (spin_retry < 0)
  21. spin_retry = 1000;
  22. return 0;
  23. }
  24. early_initcall(spin_retry_init);
  25. /**
  26. * spin_retry= parameter
  27. */
  28. static int __init spin_retry_setup(char *str)
  29. {
  30. spin_retry = simple_strtoul(str, &str, 0);
  31. return 1;
  32. }
  33. __setup("spin_retry=", spin_retry_setup);
  34. struct spin_wait {
  35. struct spin_wait *next, *prev;
  36. int node_id;
  37. } __aligned(32);
  38. static DEFINE_PER_CPU_ALIGNED(struct spin_wait, spin_wait[4]);
  39. #define _Q_LOCK_CPU_OFFSET 0
  40. #define _Q_LOCK_STEAL_OFFSET 16
  41. #define _Q_TAIL_IDX_OFFSET 18
  42. #define _Q_TAIL_CPU_OFFSET 20
  43. #define _Q_LOCK_CPU_MASK 0x0000ffff
  44. #define _Q_LOCK_STEAL_ADD 0x00010000
  45. #define _Q_LOCK_STEAL_MASK 0x00030000
  46. #define _Q_TAIL_IDX_MASK 0x000c0000
  47. #define _Q_TAIL_CPU_MASK 0xfff00000
  48. #define _Q_LOCK_MASK (_Q_LOCK_CPU_MASK | _Q_LOCK_STEAL_MASK)
  49. #define _Q_TAIL_MASK (_Q_TAIL_IDX_MASK | _Q_TAIL_CPU_MASK)
  50. void arch_spin_lock_setup(int cpu)
  51. {
  52. struct spin_wait *node;
  53. int ix;
  54. node = per_cpu_ptr(&spin_wait[0], cpu);
  55. for (ix = 0; ix < 4; ix++, node++) {
  56. memset(node, 0, sizeof(*node));
  57. node->node_id = ((cpu + 1) << _Q_TAIL_CPU_OFFSET) +
  58. (ix << _Q_TAIL_IDX_OFFSET);
  59. }
  60. }
  61. static inline int arch_load_niai4(int *lock)
  62. {
  63. int owner;
  64. asm volatile(
  65. ALTERNATIVE("", ".long 0xb2fa0040", 49) /* NIAI 4 */
  66. " l %0,%1\n"
  67. : "=d" (owner) : "Q" (*lock) : "memory");
  68. return owner;
  69. }
  70. static inline int arch_cmpxchg_niai8(int *lock, int old, int new)
  71. {
  72. int expected = old;
  73. asm volatile(
  74. ALTERNATIVE("", ".long 0xb2fa0080", 49) /* NIAI 8 */
  75. " cs %0,%3,%1\n"
  76. : "=d" (old), "=Q" (*lock)
  77. : "0" (old), "d" (new), "Q" (*lock)
  78. : "cc", "memory");
  79. return expected == old;
  80. }
  81. static inline struct spin_wait *arch_spin_decode_tail(int lock)
  82. {
  83. int ix, cpu;
  84. ix = (lock & _Q_TAIL_IDX_MASK) >> _Q_TAIL_IDX_OFFSET;
  85. cpu = (lock & _Q_TAIL_CPU_MASK) >> _Q_TAIL_CPU_OFFSET;
  86. return per_cpu_ptr(&spin_wait[ix], cpu - 1);
  87. }
  88. static inline int arch_spin_yield_target(int lock, struct spin_wait *node)
  89. {
  90. if (lock & _Q_LOCK_CPU_MASK)
  91. return lock & _Q_LOCK_CPU_MASK;
  92. if (node == NULL || node->prev == NULL)
  93. return 0; /* 0 -> no target cpu */
  94. while (node->prev)
  95. node = node->prev;
  96. return node->node_id >> _Q_TAIL_CPU_OFFSET;
  97. }
  98. static inline void arch_spin_lock_queued(arch_spinlock_t *lp)
  99. {
  100. struct spin_wait *node, *next;
  101. int lockval, ix, node_id, tail_id, old, new, owner, count;
  102. ix = S390_lowcore.spinlock_index++;
  103. barrier();
  104. lockval = SPINLOCK_LOCKVAL; /* cpu + 1 */
  105. node = this_cpu_ptr(&spin_wait[ix]);
  106. node->prev = node->next = NULL;
  107. node_id = node->node_id;
  108. /* Enqueue the node for this CPU in the spinlock wait queue */
  109. while (1) {
  110. old = READ_ONCE(lp->lock);
  111. if ((old & _Q_LOCK_CPU_MASK) == 0 &&
  112. (old & _Q_LOCK_STEAL_MASK) != _Q_LOCK_STEAL_MASK) {
  113. /*
  114. * The lock is free but there may be waiters.
  115. * With no waiters simply take the lock, if there
  116. * are waiters try to steal the lock. The lock may
  117. * be stolen three times before the next queued
  118. * waiter will get the lock.
  119. */
  120. new = (old ? (old + _Q_LOCK_STEAL_ADD) : 0) | lockval;
  121. if (__atomic_cmpxchg_bool(&lp->lock, old, new))
  122. /* Got the lock */
  123. goto out;
  124. /* lock passing in progress */
  125. continue;
  126. }
  127. /* Make the node of this CPU the new tail. */
  128. new = node_id | (old & _Q_LOCK_MASK);
  129. if (__atomic_cmpxchg_bool(&lp->lock, old, new))
  130. break;
  131. }
  132. /* Set the 'next' pointer of the tail node in the queue */
  133. tail_id = old & _Q_TAIL_MASK;
  134. if (tail_id != 0) {
  135. node->prev = arch_spin_decode_tail(tail_id);
  136. WRITE_ONCE(node->prev->next, node);
  137. }
  138. /* Pass the virtual CPU to the lock holder if it is not running */
  139. owner = arch_spin_yield_target(old, node);
  140. if (owner && arch_vcpu_is_preempted(owner - 1))
  141. smp_yield_cpu(owner - 1);
  142. /* Spin on the CPU local node->prev pointer */
  143. if (tail_id != 0) {
  144. count = spin_retry;
  145. while (READ_ONCE(node->prev) != NULL) {
  146. if (count-- >= 0)
  147. continue;
  148. count = spin_retry;
  149. /* Query running state of lock holder again. */
  150. owner = arch_spin_yield_target(old, node);
  151. if (owner && arch_vcpu_is_preempted(owner - 1))
  152. smp_yield_cpu(owner - 1);
  153. }
  154. }
  155. /* Spin on the lock value in the spinlock_t */
  156. count = spin_retry;
  157. while (1) {
  158. old = READ_ONCE(lp->lock);
  159. owner = old & _Q_LOCK_CPU_MASK;
  160. if (!owner) {
  161. tail_id = old & _Q_TAIL_MASK;
  162. new = ((tail_id != node_id) ? tail_id : 0) | lockval;
  163. if (__atomic_cmpxchg_bool(&lp->lock, old, new))
  164. /* Got the lock */
  165. break;
  166. continue;
  167. }
  168. if (count-- >= 0)
  169. continue;
  170. count = spin_retry;
  171. if (!MACHINE_IS_LPAR || arch_vcpu_is_preempted(owner - 1))
  172. smp_yield_cpu(owner - 1);
  173. }
  174. /* Pass lock_spin job to next CPU in the queue */
  175. if (node_id && tail_id != node_id) {
  176. /* Wait until the next CPU has set up the 'next' pointer */
  177. while ((next = READ_ONCE(node->next)) == NULL)
  178. ;
  179. next->prev = NULL;
  180. }
  181. out:
  182. S390_lowcore.spinlock_index--;
  183. }
  184. static inline void arch_spin_lock_classic(arch_spinlock_t *lp)
  185. {
  186. int lockval, old, new, owner, count;
  187. lockval = SPINLOCK_LOCKVAL; /* cpu + 1 */
  188. /* Pass the virtual CPU to the lock holder if it is not running */
  189. owner = arch_spin_yield_target(READ_ONCE(lp->lock), NULL);
  190. if (owner && arch_vcpu_is_preempted(owner - 1))
  191. smp_yield_cpu(owner - 1);
  192. count = spin_retry;
  193. while (1) {
  194. old = arch_load_niai4(&lp->lock);
  195. owner = old & _Q_LOCK_CPU_MASK;
  196. /* Try to get the lock if it is free. */
  197. if (!owner) {
  198. new = (old & _Q_TAIL_MASK) | lockval;
  199. if (arch_cmpxchg_niai8(&lp->lock, old, new)) {
  200. /* Got the lock */
  201. return;
  202. }
  203. continue;
  204. }
  205. if (count-- >= 0)
  206. continue;
  207. count = spin_retry;
  208. if (!MACHINE_IS_LPAR || arch_vcpu_is_preempted(owner - 1))
  209. smp_yield_cpu(owner - 1);
  210. }
  211. }
  212. void arch_spin_lock_wait(arch_spinlock_t *lp)
  213. {
  214. /* Use classic spinlocks + niai if the steal time is >= 10% */
  215. if (test_cpu_flag(CIF_DEDICATED_CPU))
  216. arch_spin_lock_queued(lp);
  217. else
  218. arch_spin_lock_classic(lp);
  219. }
  220. EXPORT_SYMBOL(arch_spin_lock_wait);
  221. int arch_spin_trylock_retry(arch_spinlock_t *lp)
  222. {
  223. int cpu = SPINLOCK_LOCKVAL;
  224. int owner, count;
  225. for (count = spin_retry; count > 0; count--) {
  226. owner = READ_ONCE(lp->lock);
  227. /* Try to get the lock if it is free. */
  228. if (!owner) {
  229. if (__atomic_cmpxchg_bool(&lp->lock, 0, cpu))
  230. return 1;
  231. }
  232. }
  233. return 0;
  234. }
  235. EXPORT_SYMBOL(arch_spin_trylock_retry);
  236. void arch_read_lock_wait(arch_rwlock_t *rw)
  237. {
  238. if (unlikely(in_interrupt())) {
  239. while (READ_ONCE(rw->cnts) & 0x10000)
  240. barrier();
  241. return;
  242. }
  243. /* Remove this reader again to allow recursive read locking */
  244. __atomic_add_const(-1, &rw->cnts);
  245. /* Put the reader into the wait queue */
  246. arch_spin_lock(&rw->wait);
  247. /* Now add this reader to the count value again */
  248. __atomic_add_const(1, &rw->cnts);
  249. /* Loop until the writer is done */
  250. while (READ_ONCE(rw->cnts) & 0x10000)
  251. barrier();
  252. arch_spin_unlock(&rw->wait);
  253. }
  254. EXPORT_SYMBOL(arch_read_lock_wait);
  255. void arch_write_lock_wait(arch_rwlock_t *rw)
  256. {
  257. int old;
  258. /* Add this CPU to the write waiters */
  259. __atomic_add(0x20000, &rw->cnts);
  260. /* Put the writer into the wait queue */
  261. arch_spin_lock(&rw->wait);
  262. while (1) {
  263. old = READ_ONCE(rw->cnts);
  264. if ((old & 0x1ffff) == 0 &&
  265. __atomic_cmpxchg_bool(&rw->cnts, old, old | 0x10000))
  266. /* Got the lock */
  267. break;
  268. barrier();
  269. }
  270. arch_spin_unlock(&rw->wait);
  271. }
  272. EXPORT_SYMBOL(arch_write_lock_wait);
  273. void arch_spin_relax(arch_spinlock_t *lp)
  274. {
  275. int cpu;
  276. cpu = READ_ONCE(lp->lock) & _Q_LOCK_CPU_MASK;
  277. if (!cpu)
  278. return;
  279. if (MACHINE_IS_LPAR && !arch_vcpu_is_preempted(cpu - 1))
  280. return;
  281. smp_yield_cpu(cpu - 1);
  282. }
  283. EXPORT_SYMBOL(arch_spin_relax);