Kconfig.cpu 12 KB

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  1. # SPDX-License-Identifier: GPL-2.0
  2. comment "Processor Type"
  3. choice
  4. prompt "CPU family support"
  5. default M68KCLASSIC if MMU
  6. default COLDFIRE if !MMU
  7. help
  8. The Freescale (was Motorola) M68K family of processors implements
  9. the full 68000 processor instruction set.
  10. The Freescale ColdFire family of processors is a modern derivative
  11. of the 68000 processor family. They are mainly targeted at embedded
  12. applications, and are all System-On-Chip (SOC) devices, as opposed
  13. to stand alone CPUs. They implement a subset of the original 68000
  14. processor instruction set.
  15. If you anticipate running this kernel on a computer with a classic
  16. MC68xxx processor, select M68KCLASSIC.
  17. If you anticipate running this kernel on a computer with a ColdFire
  18. processor, select COLDFIRE.
  19. config M68KCLASSIC
  20. bool "Classic M68K CPU family support"
  21. config COLDFIRE
  22. bool "Coldfire CPU family support"
  23. select ARCH_HAVE_CUSTOM_GPIO_H
  24. select CPU_HAS_NO_BITFIELDS
  25. select CPU_HAS_NO_MULDIV64
  26. select GENERIC_CSUM
  27. select GPIOLIB
  28. select HAVE_CLK
  29. endchoice
  30. if M68KCLASSIC
  31. config M68000
  32. bool "MC68000"
  33. depends on !MMU
  34. select CPU_HAS_NO_BITFIELDS
  35. select CPU_HAS_NO_MULDIV64
  36. select CPU_HAS_NO_UNALIGNED
  37. select GENERIC_CSUM
  38. select CPU_NO_EFFICIENT_FFS
  39. select HAVE_ARCH_HASH
  40. help
  41. The Freescale (was Motorola) 68000 CPU is the first generation of
  42. the well known M68K family of processors. The CPU core as well as
  43. being available as a stand alone CPU was also used in many
  44. System-On-Chip devices (eg 68328, 68302, etc). It does not contain
  45. a paging MMU.
  46. config MCPU32
  47. bool
  48. select CPU_HAS_NO_BITFIELDS
  49. select CPU_HAS_NO_UNALIGNED
  50. select CPU_NO_EFFICIENT_FFS
  51. help
  52. The Freescale (was then Motorola) CPU32 is a CPU core that is
  53. based on the 68020 processor. For the most part it is used in
  54. System-On-Chip parts, and does not contain a paging MMU.
  55. config M68020
  56. bool "68020 support"
  57. depends on MMU
  58. select FPU
  59. select CPU_HAS_ADDRESS_SPACES
  60. help
  61. If you anticipate running this kernel on a computer with a MC68020
  62. processor, say Y. Otherwise, say N. Note that the 68020 requires a
  63. 68851 MMU (Memory Management Unit) to run Linux/m68k, except on the
  64. Sun 3, which provides its own version.
  65. config M68030
  66. bool "68030 support"
  67. depends on MMU && !MMU_SUN3
  68. select FPU
  69. select CPU_HAS_ADDRESS_SPACES
  70. help
  71. If you anticipate running this kernel on a computer with a MC68030
  72. processor, say Y. Otherwise, say N. Note that a MC68EC030 will not
  73. work, as it does not include an MMU (Memory Management Unit).
  74. config M68040
  75. bool "68040 support"
  76. depends on MMU && !MMU_SUN3
  77. select FPU
  78. select CPU_HAS_ADDRESS_SPACES
  79. help
  80. If you anticipate running this kernel on a computer with a MC68LC040
  81. or MC68040 processor, say Y. Otherwise, say N. Note that an
  82. MC68EC040 will not work, as it does not include an MMU (Memory
  83. Management Unit).
  84. config M68060
  85. bool "68060 support"
  86. depends on MMU && !MMU_SUN3
  87. select FPU
  88. select CPU_HAS_ADDRESS_SPACES
  89. help
  90. If you anticipate running this kernel on a computer with a MC68060
  91. processor, say Y. Otherwise, say N.
  92. config M68328
  93. bool "MC68328"
  94. depends on !MMU
  95. select M68000
  96. help
  97. Motorola 68328 processor support.
  98. config M68EZ328
  99. bool "MC68EZ328"
  100. depends on !MMU
  101. select M68000
  102. help
  103. Motorola 68EX328 processor support.
  104. config M68VZ328
  105. bool "MC68VZ328"
  106. depends on !MMU
  107. select M68000
  108. help
  109. Motorola 68VZ328 processor support.
  110. endif # M68KCLASSIC
  111. if COLDFIRE
  112. choice
  113. prompt "ColdFire SoC type"
  114. default M520x
  115. help
  116. Select the type of ColdFire System-on-Chip (SoC) that you want
  117. to build for.
  118. config M5206
  119. bool "MCF5206"
  120. depends on !MMU
  121. select COLDFIRE_SW_A7
  122. select HAVE_MBAR
  123. select CPU_NO_EFFICIENT_FFS
  124. help
  125. Motorola ColdFire 5206 processor support.
  126. config M5206e
  127. bool "MCF5206e"
  128. depends on !MMU
  129. select COLDFIRE_SW_A7
  130. select HAVE_MBAR
  131. select CPU_NO_EFFICIENT_FFS
  132. help
  133. Motorola ColdFire 5206e processor support.
  134. config M520x
  135. bool "MCF520x"
  136. depends on !MMU
  137. select GENERIC_CLOCKEVENTS
  138. select HAVE_CACHE_SPLIT
  139. help
  140. Freescale Coldfire 5207/5208 processor support.
  141. config M523x
  142. bool "MCF523x"
  143. depends on !MMU
  144. select GENERIC_CLOCKEVENTS
  145. select HAVE_CACHE_SPLIT
  146. select HAVE_IPSBAR
  147. help
  148. Freescale Coldfire 5230/1/2/4/5 processor support
  149. config M5249
  150. bool "MCF5249"
  151. depends on !MMU
  152. select COLDFIRE_SW_A7
  153. select HAVE_MBAR
  154. select CPU_NO_EFFICIENT_FFS
  155. help
  156. Motorola ColdFire 5249 processor support.
  157. config M525x
  158. bool "MCF525x"
  159. depends on !MMU
  160. select COLDFIRE_SW_A7
  161. select HAVE_MBAR
  162. select CPU_NO_EFFICIENT_FFS
  163. help
  164. Freescale (Motorola) Coldfire 5251/5253 processor support.
  165. config M5271
  166. bool "MCF5271"
  167. depends on !MMU
  168. select M527x
  169. select HAVE_CACHE_SPLIT
  170. select HAVE_IPSBAR
  171. select GENERIC_CLOCKEVENTS
  172. help
  173. Freescale (Motorola) ColdFire 5270/5271 processor support.
  174. config M5272
  175. bool "MCF5272"
  176. depends on !MMU
  177. select COLDFIRE_SW_A7
  178. select HAVE_MBAR
  179. select CPU_NO_EFFICIENT_FFS
  180. help
  181. Motorola ColdFire 5272 processor support.
  182. config M5275
  183. bool "MCF5275"
  184. depends on !MMU
  185. select M527x
  186. select HAVE_CACHE_SPLIT
  187. select HAVE_IPSBAR
  188. select GENERIC_CLOCKEVENTS
  189. help
  190. Freescale (Motorola) ColdFire 5274/5275 processor support.
  191. config M528x
  192. bool "MCF528x"
  193. depends on !MMU
  194. select GENERIC_CLOCKEVENTS
  195. select HAVE_CACHE_SPLIT
  196. select HAVE_IPSBAR
  197. help
  198. Motorola ColdFire 5280/5282 processor support.
  199. config M5307
  200. bool "MCF5307"
  201. depends on !MMU
  202. select COLDFIRE_SW_A7
  203. select HAVE_CACHE_CB
  204. select HAVE_MBAR
  205. select CPU_NO_EFFICIENT_FFS
  206. help
  207. Motorola ColdFire 5307 processor support.
  208. config M532x
  209. bool "MCF532x"
  210. depends on !MMU
  211. select M53xx
  212. select HAVE_CACHE_CB
  213. help
  214. Freescale (Motorola) ColdFire 532x processor support.
  215. config M537x
  216. bool "MCF537x"
  217. depends on !MMU
  218. select M53xx
  219. select HAVE_CACHE_CB
  220. help
  221. Freescale ColdFire 537x processor support.
  222. config M5407
  223. bool "MCF5407"
  224. depends on !MMU
  225. select COLDFIRE_SW_A7
  226. select HAVE_CACHE_CB
  227. select HAVE_MBAR
  228. select CPU_NO_EFFICIENT_FFS
  229. help
  230. Motorola ColdFire 5407 processor support.
  231. config M547x
  232. bool "MCF547x"
  233. select M54xx
  234. select MMU_COLDFIRE if MMU
  235. select FPU if MMU
  236. select HAVE_CACHE_CB
  237. select HAVE_MBAR
  238. select CPU_NO_EFFICIENT_FFS
  239. help
  240. Freescale ColdFire 5470/5471/5472/5473/5474/5475 processor support.
  241. config M548x
  242. bool "MCF548x"
  243. select MMU_COLDFIRE if MMU
  244. select FPU if MMU
  245. select M54xx
  246. select HAVE_CACHE_CB
  247. select HAVE_MBAR
  248. select CPU_NO_EFFICIENT_FFS
  249. help
  250. Freescale ColdFire 5480/5481/5482/5483/5484/5485 processor support.
  251. config M5441x
  252. bool "MCF5441x"
  253. select MMU_COLDFIRE if MMU
  254. select GENERIC_CLOCKEVENTS
  255. select HAVE_CACHE_CB
  256. help
  257. Freescale Coldfire 54410/54415/54416/54417/54418 processor support.
  258. endchoice
  259. config M527x
  260. bool
  261. config M53xx
  262. bool
  263. config M54xx
  264. bool
  265. endif # COLDFIRE
  266. comment "Processor Specific Options"
  267. config M68KFPU_EMU
  268. bool "Math emulation support"
  269. depends on MMU
  270. help
  271. At some point in the future, this will cause floating-point math
  272. instructions to be emulated by the kernel on machines that lack a
  273. floating-point math coprocessor. Thrill-seekers and chronically
  274. sleep-deprived psychotic hacker types can say Y now, everyone else
  275. should probably wait a while.
  276. config M68KFPU_EMU_EXTRAPREC
  277. bool "Math emulation extra precision"
  278. depends on M68KFPU_EMU
  279. help
  280. The fpu uses normally a few bit more during calculations for
  281. correct rounding, the emulator can (often) do the same but this
  282. extra calculation can cost quite some time, so you can disable
  283. it here. The emulator will then "only" calculate with a 64 bit
  284. mantissa and round slightly incorrect, what is more than enough
  285. for normal usage.
  286. config M68KFPU_EMU_ONLY
  287. bool "Math emulation only kernel"
  288. depends on M68KFPU_EMU
  289. help
  290. This option prevents any floating-point instructions from being
  291. compiled into the kernel, thereby the kernel doesn't save any
  292. floating point context anymore during task switches, so this
  293. kernel will only be usable on machines without a floating-point
  294. math coprocessor. This makes the kernel a bit faster as no tests
  295. needs to be executed whether a floating-point instruction in the
  296. kernel should be executed or not.
  297. config ADVANCED
  298. bool "Advanced configuration options"
  299. depends on MMU
  300. ---help---
  301. This gives you access to some advanced options for the CPU. The
  302. defaults should be fine for most users, but these options may make
  303. it possible for you to improve performance somewhat if you know what
  304. you are doing.
  305. Note that the answer to this question won't directly affect the
  306. kernel: saying N will just cause the configurator to skip all
  307. the questions about these options.
  308. Most users should say N to this question.
  309. config RMW_INSNS
  310. bool "Use read-modify-write instructions"
  311. depends on ADVANCED
  312. ---help---
  313. This allows to use certain instructions that work with indivisible
  314. read-modify-write bus cycles. While this is faster than the
  315. workaround of disabling interrupts, it can conflict with DMA
  316. ( = direct memory access) on many Amiga systems, and it is also said
  317. to destabilize other machines. It is very likely that this will
  318. cause serious problems on any Amiga or Atari Medusa if set. The only
  319. configuration where it should work are 68030-based Ataris, where it
  320. apparently improves performance. But you've been warned! Unless you
  321. really know what you are doing, say N. Try Y only if you're quite
  322. adventurous.
  323. config SINGLE_MEMORY_CHUNK
  324. bool "Use one physical chunk of memory only" if ADVANCED && !SUN3
  325. depends on MMU
  326. default y if SUN3
  327. select NEED_MULTIPLE_NODES
  328. help
  329. Ignore all but the first contiguous chunk of physical memory for VM
  330. purposes. This will save a few bytes kernel size and may speed up
  331. some operations. Say N if not sure.
  332. config ARCH_DISCONTIGMEM_ENABLE
  333. def_bool MMU && !SINGLE_MEMORY_CHUNK
  334. config 060_WRITETHROUGH
  335. bool "Use write-through caching for 68060 supervisor accesses"
  336. depends on ADVANCED && M68060
  337. ---help---
  338. The 68060 generally uses copyback caching of recently accessed data.
  339. Copyback caching means that memory writes will be held in an on-chip
  340. cache and only written back to memory some time later. Saying Y
  341. here will force supervisor (kernel) accesses to use writethrough
  342. caching. Writethrough caching means that data is written to memory
  343. straight away, so that cache and memory data always agree.
  344. Writethrough caching is less efficient, but is needed for some
  345. drivers on 68060 based systems where the 68060 bus snooping signal
  346. is hardwired on. The 53c710 SCSI driver is known to suffer from
  347. this problem.
  348. config M68K_L2_CACHE
  349. bool
  350. depends on MAC
  351. default y
  352. config NODES_SHIFT
  353. int
  354. default "3"
  355. depends on !SINGLE_MEMORY_CHUNK
  356. config CPU_HAS_NO_BITFIELDS
  357. bool
  358. config CPU_HAS_NO_MULDIV64
  359. bool
  360. config CPU_HAS_NO_UNALIGNED
  361. bool
  362. config CPU_HAS_ADDRESS_SPACES
  363. bool
  364. config FPU
  365. bool
  366. config COLDFIRE_SW_A7
  367. bool
  368. config HAVE_CACHE_SPLIT
  369. bool
  370. config HAVE_CACHE_CB
  371. bool
  372. config HAVE_MBAR
  373. bool
  374. config HAVE_IPSBAR
  375. bool
  376. config CLOCK_FREQ
  377. int "Set the core clock frequency"
  378. default "25000000" if M5206
  379. default "54000000" if M5206e
  380. default "166666666" if M520x
  381. default "140000000" if M5249
  382. default "150000000" if M527x || M523x
  383. default "90000000" if M5307
  384. default "50000000" if M5407
  385. default "266000000" if M54xx
  386. default "66666666"
  387. depends on COLDFIRE
  388. help
  389. Define the CPU clock frequency in use. This is the core clock
  390. frequency, it may or may not be the same as the external clock
  391. crystal fitted to your board. Some processors have an internal
  392. PLL and can have their frequency programmed at run time, others
  393. use internal dividers. In general the kernel won't setup a PLL
  394. if it is fitted (there are some exceptions). This value will be
  395. specific to the exact CPU that you are using.
  396. config OLDMASK
  397. bool "Old mask 5307 (1H55J) silicon"
  398. depends on M5307
  399. help
  400. Build support for the older revision ColdFire 5307 silicon.
  401. Specifically this is the 1H55J mask revision.
  402. if HAVE_CACHE_SPLIT
  403. choice
  404. prompt "Split Cache Configuration"
  405. default CACHE_I
  406. config CACHE_I
  407. bool "Instruction"
  408. help
  409. Use all of the ColdFire CPU cache memory as an instruction cache.
  410. config CACHE_D
  411. bool "Data"
  412. help
  413. Use all of the ColdFire CPU cache memory as a data cache.
  414. config CACHE_BOTH
  415. bool "Both"
  416. help
  417. Split the ColdFire CPU cache, and use half as an instruction cache
  418. and half as a data cache.
  419. endchoice
  420. endif
  421. if HAVE_CACHE_CB
  422. choice
  423. prompt "Data cache mode"
  424. default CACHE_WRITETHRU
  425. config CACHE_WRITETHRU
  426. bool "Write-through"
  427. help
  428. The ColdFire CPU cache is set into Write-through mode.
  429. config CACHE_COPYBACK
  430. bool "Copy-back"
  431. help
  432. The ColdFire CPU cache is set into Copy-back mode.
  433. endchoice
  434. endif