tegra132-norrin.dts 30 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /dts-v1/;
  3. #include <dt-bindings/input/input.h>
  4. #include "tegra132.dtsi"
  5. / {
  6. model = "NVIDIA Tegra132 Norrin";
  7. compatible = "nvidia,norrin", "nvidia,tegra132", "nvidia,tegra124";
  8. aliases {
  9. rtc0 = "/i2c@7000d000/as3722@40";
  10. rtc1 = "/rtc@7000e000";
  11. serial0 = &uarta;
  12. };
  13. chosen {
  14. stdout-path = "serial0:115200n8";
  15. };
  16. memory {
  17. device_type = "memory";
  18. reg = <0x0 0x80000000 0x0 0x80000000>;
  19. };
  20. host1x@50000000 {
  21. hdmi@54280000 {
  22. status = "disabled";
  23. vdd-supply = <&vdd_3v3_hdmi>;
  24. pll-supply = <&vdd_hdmi_pll>;
  25. hdmi-supply = <&vdd_5v0_hdmi>;
  26. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  27. nvidia,hpd-gpio =
  28. <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
  29. };
  30. sor@54540000 {
  31. status = "okay";
  32. nvidia,dpaux = <&dpaux>;
  33. nvidia,panel = <&panel>;
  34. };
  35. dpaux: dpaux@545c0000 {
  36. vdd-supply = <&vdd_3v3_panel>;
  37. status = "okay";
  38. };
  39. };
  40. gpu@57000000 {
  41. status = "okay";
  42. vdd-supply = <&vdd_gpu>;
  43. };
  44. pinmux@70000868 {
  45. pinctrl-names = "default";
  46. pinctrl-0 = <&pinmux_default>;
  47. pinmux_default: pinmux@0 {
  48. dap_mclk1_pw4 {
  49. nvidia,pins = "dap_mclk1_pw4";
  50. nvidia,function = "extperiph1";
  51. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  52. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  53. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  54. };
  55. dap2_din_pa4 {
  56. nvidia,pins = "dap2_din_pa4";
  57. nvidia,function = "i2s1";
  58. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  59. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  60. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  61. };
  62. dap2_dout_pa5 {
  63. nvidia,pins = "dap2_dout_pa5",
  64. "dap2_fs_pa2",
  65. "dap2_sclk_pa3";
  66. nvidia,function = "i2s1";
  67. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  68. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  69. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  70. };
  71. dap3_dout_pp2 {
  72. nvidia,pins = "dap3_dout_pp2";
  73. nvidia,function = "i2s2";
  74. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  75. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  76. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  77. };
  78. dvfs_pwm_px0 {
  79. nvidia,pins = "dvfs_pwm_px0",
  80. "dvfs_clk_px2";
  81. nvidia,function = "cldvfs";
  82. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  83. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  84. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  85. };
  86. ulpi_clk_py0 {
  87. nvidia,pins = "ulpi_clk_py0",
  88. "ulpi_nxt_py2",
  89. "ulpi_stp_py3";
  90. nvidia,function = "spi1";
  91. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  92. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  93. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  94. };
  95. ulpi_dir_py1 {
  96. nvidia,pins = "ulpi_dir_py1";
  97. nvidia,function = "spi1";
  98. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  99. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  100. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  101. };
  102. cam_i2c_scl_pbb1 {
  103. nvidia,pins = "cam_i2c_scl_pbb1",
  104. "cam_i2c_sda_pbb2";
  105. nvidia,function = "i2c3";
  106. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  107. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  108. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  109. nvidia,lock = <TEGRA_PIN_DISABLE>;
  110. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  111. };
  112. gen2_i2c_scl_pt5 {
  113. nvidia,pins = "gen2_i2c_scl_pt5",
  114. "gen2_i2c_sda_pt6";
  115. nvidia,function = "i2c2";
  116. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  117. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  118. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  119. nvidia,lock = <TEGRA_PIN_DISABLE>;
  120. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  121. };
  122. pj7 {
  123. nvidia,pins = "pj7";
  124. nvidia,function = "uartd";
  125. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  126. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  127. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  128. };
  129. spdif_in_pk6 {
  130. nvidia,pins = "spdif_in_pk6";
  131. nvidia,function = "spdif";
  132. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  133. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  134. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  135. };
  136. pk7 {
  137. nvidia,pins = "pk7";
  138. nvidia,function = "uartd";
  139. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  140. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  141. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  142. };
  143. pg4 {
  144. nvidia,pins = "pg4",
  145. "pg5",
  146. "pg6",
  147. "pi3";
  148. nvidia,function = "spi4";
  149. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  150. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  151. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  152. };
  153. pg7 {
  154. nvidia,pins = "pg7";
  155. nvidia,function = "spi4";
  156. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  157. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  158. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  159. };
  160. ph1 {
  161. nvidia,pins = "ph1";
  162. nvidia,function = "pwm1";
  163. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  164. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  165. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  166. };
  167. pk0 {
  168. nvidia,pins = "pk0",
  169. "kb_row15_ps7",
  170. "clk_32k_out_pa0";
  171. nvidia,function = "soc";
  172. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  173. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  174. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  175. };
  176. sdmmc1_clk_pz0 {
  177. nvidia,pins = "sdmmc1_clk_pz0";
  178. nvidia,function = "sdmmc1";
  179. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  180. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  181. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  182. };
  183. sdmmc1_cmd_pz1 {
  184. nvidia,pins = "sdmmc1_cmd_pz1",
  185. "sdmmc1_dat0_py7",
  186. "sdmmc1_dat1_py6",
  187. "sdmmc1_dat2_py5",
  188. "sdmmc1_dat3_py4";
  189. nvidia,function = "sdmmc1";
  190. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  191. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  192. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  193. };
  194. sdmmc3_clk_pa6 {
  195. nvidia,pins = "sdmmc3_clk_pa6";
  196. nvidia,function = "sdmmc3";
  197. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  198. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  199. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  200. };
  201. sdmmc3_cmd_pa7 {
  202. nvidia,pins = "sdmmc3_cmd_pa7",
  203. "sdmmc3_dat0_pb7",
  204. "sdmmc3_dat1_pb6",
  205. "sdmmc3_dat2_pb5",
  206. "sdmmc3_dat3_pb4",
  207. "kb_col4_pq4",
  208. "sdmmc3_clk_lb_out_pee4",
  209. "sdmmc3_clk_lb_in_pee5",
  210. "sdmmc3_cd_n_pv2";
  211. nvidia,function = "sdmmc3";
  212. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  213. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  214. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  215. };
  216. sdmmc4_clk_pcc4 {
  217. nvidia,pins = "sdmmc4_clk_pcc4";
  218. nvidia,function = "sdmmc4";
  219. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  220. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  221. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  222. };
  223. sdmmc4_cmd_pt7 {
  224. nvidia,pins = "sdmmc4_cmd_pt7",
  225. "sdmmc4_dat0_paa0",
  226. "sdmmc4_dat1_paa1",
  227. "sdmmc4_dat2_paa2",
  228. "sdmmc4_dat3_paa3",
  229. "sdmmc4_dat4_paa4",
  230. "sdmmc4_dat5_paa5",
  231. "sdmmc4_dat6_paa6",
  232. "sdmmc4_dat7_paa7";
  233. nvidia,function = "sdmmc4";
  234. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  235. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  236. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  237. };
  238. mic_det_l {
  239. nvidia,pins = "kb_row7_pr7";
  240. nvidia,function = "rsvd2";
  241. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  242. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  243. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  244. };
  245. kb_row10_ps2 {
  246. nvidia,pins = "kb_row10_ps2";
  247. nvidia,function = "uarta";
  248. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  249. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  250. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  251. };
  252. kb_row9_ps1 {
  253. nvidia,pins = "kb_row9_ps1";
  254. nvidia,function = "uarta";
  255. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  256. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  257. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  258. };
  259. pwr_i2c_scl_pz6 {
  260. nvidia,pins = "pwr_i2c_scl_pz6",
  261. "pwr_i2c_sda_pz7";
  262. nvidia,function = "i2cpwr";
  263. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  264. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  265. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  266. nvidia,lock = <TEGRA_PIN_DISABLE>;
  267. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  268. };
  269. jtag_rtck {
  270. nvidia,pins = "jtag_rtck";
  271. nvidia,function = "rtck";
  272. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  273. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  274. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  275. };
  276. clk_32k_in {
  277. nvidia,pins = "clk_32k_in";
  278. nvidia,function = "clk";
  279. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  280. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  281. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  282. };
  283. core_pwr_req {
  284. nvidia,pins = "core_pwr_req";
  285. nvidia,function = "pwron";
  286. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  287. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  288. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  289. };
  290. cpu_pwr_req {
  291. nvidia,pins = "cpu_pwr_req";
  292. nvidia,function = "cpu";
  293. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  294. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  295. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  296. };
  297. kb_col0_ap {
  298. nvidia,pins = "kb_col0_pq0";
  299. nvidia,function = "rsvd4";
  300. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  301. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  302. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  303. };
  304. en_vdd_sd {
  305. nvidia,pins = "kb_row0_pr0";
  306. nvidia,function = "rsvd4";
  307. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  308. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  309. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  310. };
  311. lid_open {
  312. nvidia,pins = "kb_row4_pr4";
  313. nvidia,function = "rsvd3";
  314. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  315. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  316. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  317. };
  318. pwr_int_n {
  319. nvidia,pins = "pwr_int_n";
  320. nvidia,function = "pmi";
  321. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  322. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  323. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  324. };
  325. reset_out_n {
  326. nvidia,pins = "reset_out_n";
  327. nvidia,function = "reset_out_n";
  328. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  329. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  330. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  331. };
  332. clk3_out_pee0 {
  333. nvidia,pins = "clk3_out_pee0";
  334. nvidia,function = "extperiph3";
  335. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  336. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  337. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  338. };
  339. gen1_i2c_scl_pc4 {
  340. nvidia,pins = "gen1_i2c_scl_pc4",
  341. "gen1_i2c_sda_pc5";
  342. nvidia,function = "i2c1";
  343. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  344. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  345. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  346. nvidia,lock = <TEGRA_PIN_DISABLE>;
  347. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  348. };
  349. hdmi_cec_pee3 {
  350. nvidia,pins = "hdmi_cec_pee3";
  351. nvidia,function = "cec";
  352. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  353. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  354. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  355. nvidia,lock = <TEGRA_PIN_DISABLE>;
  356. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  357. };
  358. hdmi_int_pn7 {
  359. nvidia,pins = "hdmi_int_pn7";
  360. nvidia,function = "rsvd1";
  361. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  362. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  363. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  364. };
  365. ddc_scl_pv4 {
  366. nvidia,pins = "ddc_scl_pv4",
  367. "ddc_sda_pv5";
  368. nvidia,function = "i2c4";
  369. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  370. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  371. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  372. nvidia,lock = <TEGRA_PIN_DISABLE>;
  373. nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
  374. };
  375. usb_vbus_en0_pn4 {
  376. nvidia,pins = "usb_vbus_en0_pn4",
  377. "usb_vbus_en1_pn5",
  378. "usb_vbus_en2_pff1";
  379. nvidia,function = "usb";
  380. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  381. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  382. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  383. nvidia,lock = <TEGRA_PIN_DISABLE>;
  384. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  385. };
  386. drive_sdio1 {
  387. nvidia,pins = "drive_sdio1";
  388. nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
  389. nvidia,schmitt = <TEGRA_PIN_DISABLE>;
  390. nvidia,pull-down-strength = <36>;
  391. nvidia,pull-up-strength = <20>;
  392. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>;
  393. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>;
  394. };
  395. drive_sdio3 {
  396. nvidia,pins = "drive_sdio3";
  397. nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
  398. nvidia,schmitt = <TEGRA_PIN_DISABLE>;
  399. nvidia,pull-down-strength = <22>;
  400. nvidia,pull-up-strength = <36>;
  401. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  402. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  403. };
  404. drive_gma {
  405. nvidia,pins = "drive_gma";
  406. nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
  407. nvidia,schmitt = <TEGRA_PIN_DISABLE>;
  408. nvidia,pull-down-strength = <2>;
  409. nvidia,pull-up-strength = <1>;
  410. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  411. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  412. nvidia,drive-type = <1>;
  413. };
  414. ac_ok {
  415. nvidia,pins = "pj0";
  416. nvidia,function = "gmi";
  417. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  418. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  419. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  420. };
  421. codec_irq_l {
  422. nvidia,pins = "ph4";
  423. nvidia,function = "gmi";
  424. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  425. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  426. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  427. };
  428. lcd_bl_en {
  429. nvidia,pins = "ph2";
  430. nvidia,function = "gmi";
  431. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  432. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  433. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  434. };
  435. touch_irq_l {
  436. nvidia,pins = "gpio_w3_aud_pw3";
  437. nvidia,function = "spi6";
  438. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  439. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  440. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  441. };
  442. tpm_davint_l {
  443. nvidia,pins = "ph6";
  444. nvidia,function = "gmi";
  445. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  446. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  447. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  448. };
  449. ts_irq_l {
  450. nvidia,pins = "pk2";
  451. nvidia,function = "gmi";
  452. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  453. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  454. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  455. };
  456. ts_reset_l {
  457. nvidia,pins = "pk4";
  458. nvidia,function = "gmi";
  459. nvidia,pull = <1>;
  460. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  461. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  462. };
  463. ts_shdn_l {
  464. nvidia,pins = "pk1";
  465. nvidia,function = "gmi";
  466. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  467. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  468. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  469. };
  470. ph7 {
  471. nvidia,pins = "ph7";
  472. nvidia,function = "gmi";
  473. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  474. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  475. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  476. };
  477. sensor_irq_l {
  478. nvidia,pins = "pi6";
  479. nvidia,function = "gmi";
  480. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  481. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  482. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  483. };
  484. wifi_en {
  485. nvidia,pins = "gpio_x7_aud_px7";
  486. nvidia,function = "rsvd4";
  487. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  488. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  489. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  490. };
  491. chromeos_write_protect {
  492. nvidia,pins = "kb_row1_pr1";
  493. nvidia,function = "rsvd4";
  494. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  495. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  496. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  497. };
  498. hp_det_l {
  499. nvidia,pins = "pi7";
  500. nvidia,function = "rsvd1";
  501. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  502. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  503. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  504. };
  505. soc_warm_reset_l {
  506. nvidia,pins = "pi5";
  507. nvidia,function = "gmi";
  508. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  509. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  510. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  511. };
  512. };
  513. };
  514. serial@70006000 {
  515. status = "okay";
  516. };
  517. pwm: pwm@7000a000 {
  518. status = "okay";
  519. };
  520. /* HDMI DDC */
  521. hdmi_ddc: i2c@7000c700 {
  522. status = "okay";
  523. clock-frequency = <100000>;
  524. };
  525. i2c@7000d000 {
  526. status = "okay";
  527. clock-frequency = <400000>;
  528. as3722: pmic@40 {
  529. compatible = "ams,as3722";
  530. reg = <0x40>;
  531. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  532. ams,system-power-controller;
  533. #interrupt-cells = <2>;
  534. interrupt-controller;
  535. #gpio-cells = <2>;
  536. gpio-controller;
  537. pinctrl-names = "default";
  538. pinctrl-0 = <&as3722_default>;
  539. as3722_default: pinmux@0 {
  540. gpio0 {
  541. pins = "gpio0";
  542. function = "gpio";
  543. bias-pull-down;
  544. };
  545. gpio1 {
  546. pins = "gpio1";
  547. function = "gpio";
  548. bias-pull-up;
  549. };
  550. gpio2_4_7 {
  551. pins = "gpio2", "gpio4", "gpio7";
  552. function = "gpio";
  553. bias-pull-up;
  554. };
  555. gpio3 {
  556. pins = "gpio3";
  557. function = "gpio";
  558. bias-high-impedance;
  559. };
  560. gpio5 {
  561. pins = "gpio5";
  562. function = "clk32k-out";
  563. bias-pull-down;
  564. };
  565. gpio6 {
  566. pins = "gpio6";
  567. function = "clk32k-out";
  568. bias-pull-down;
  569. };
  570. };
  571. regulators {
  572. vsup-sd2-supply = <&vdd_5v0_sys>;
  573. vsup-sd3-supply = <&vdd_5v0_sys>;
  574. vsup-sd4-supply = <&vdd_5v0_sys>;
  575. vsup-sd5-supply = <&vdd_5v0_sys>;
  576. vin-ldo0-supply = <&vdd_1v35_lp0>;
  577. vin-ldo1-6-supply = <&vdd_3v3_sys>;
  578. vin-ldo2-5-7-supply = <&vddio_1v8>;
  579. vin-ldo3-4-supply = <&vdd_3v3_sys>;
  580. vin-ldo9-10-supply = <&vdd_5v0_sys>;
  581. vin-ldo11-supply = <&vdd_3v3_run>;
  582. sd0 {
  583. regulator-name = "+VDD_CPU_AP";
  584. regulator-min-microvolt = <700000>;
  585. regulator-max-microvolt = <1350000>;
  586. regulator-max-microamp = <3500000>;
  587. regulator-always-on;
  588. regulator-boot-on;
  589. ams,ext-control = <2>;
  590. };
  591. sd1 {
  592. regulator-name = "+VDD_CORE";
  593. regulator-min-microvolt = <700000>;
  594. regulator-max-microvolt = <1350000>;
  595. regulator-max-microamp = <4000000>;
  596. regulator-always-on;
  597. regulator-boot-on;
  598. ams,ext-control = <1>;
  599. };
  600. vdd_1v35_lp0: sd2 {
  601. regulator-name = "+1.35V_LP0(sd2)";
  602. regulator-min-microvolt = <1350000>;
  603. regulator-max-microvolt = <1350000>;
  604. regulator-always-on;
  605. regulator-boot-on;
  606. };
  607. sd3 {
  608. regulator-name = "+1.35V_LP0(sd3)";
  609. regulator-min-microvolt = <1350000>;
  610. regulator-max-microvolt = <1350000>;
  611. regulator-always-on;
  612. regulator-boot-on;
  613. };
  614. vdd_1v05_run: sd4 {
  615. regulator-name = "+1.05V_RUN";
  616. regulator-min-microvolt = <1050000>;
  617. regulator-max-microvolt = <1050000>;
  618. };
  619. vddio_1v8: sd5 {
  620. regulator-name = "+1.8V_VDDIO";
  621. regulator-min-microvolt = <1800000>;
  622. regulator-max-microvolt = <1800000>;
  623. regulator-always-on;
  624. regulator-boot-on;
  625. };
  626. vdd_gpu: sd6 {
  627. regulator-name = "+VDD_GPU_AP";
  628. regulator-min-microvolt = <800000>;
  629. regulator-max-microvolt = <1200000>;
  630. regulator-min-microamp = <3500000>;
  631. regulator-max-microamp = <3500000>;
  632. regulator-always-on;
  633. regulator-boot-on;
  634. };
  635. ldo0 {
  636. regulator-name = "+1.05_RUN_AVDD";
  637. regulator-min-microvolt = <1050000>;
  638. regulator-max-microvolt = <1050000>;
  639. regulator-always-on;
  640. regulator-boot-on;
  641. ams,ext-control = <1>;
  642. };
  643. ldo1 {
  644. regulator-name = "+1.8V_RUN_CAM";
  645. regulator-min-microvolt = <1800000>;
  646. regulator-max-microvolt = <1800000>;
  647. };
  648. ldo2 {
  649. regulator-name = "+1.2V_GEN_AVDD";
  650. regulator-min-microvolt = <1200000>;
  651. regulator-max-microvolt = <1200000>;
  652. regulator-always-on;
  653. regulator-boot-on;
  654. };
  655. ldo3 {
  656. regulator-name = "+1.00V_LP0_VDD_RTC";
  657. regulator-min-microvolt = <1000000>;
  658. regulator-max-microvolt = <1000000>;
  659. regulator-always-on;
  660. regulator-boot-on;
  661. ams,enable-tracking;
  662. };
  663. vdd_run_cam: ldo4 {
  664. regulator-name = "+2.8V_RUN_CAM";
  665. regulator-min-microvolt = <2800000>;
  666. regulator-max-microvolt = <2800000>;
  667. };
  668. ldo5 {
  669. regulator-name = "+1.2V_RUN_CAM_FRONT";
  670. regulator-min-microvolt = <1200000>;
  671. regulator-max-microvolt = <1200000>;
  672. };
  673. vddio_sdmmc3: ldo6 {
  674. regulator-name = "+VDDIO_SDMMC3";
  675. regulator-min-microvolt = <1800000>;
  676. regulator-max-microvolt = <3300000>;
  677. };
  678. ldo7 {
  679. regulator-name = "+1.05V_RUN_CAM_REAR";
  680. regulator-min-microvolt = <1050000>;
  681. regulator-max-microvolt = <1050000>;
  682. };
  683. ldo9 {
  684. regulator-name = "+2.8V_RUN_TOUCH";
  685. regulator-min-microvolt = <2800000>;
  686. regulator-max-microvolt = <2800000>;
  687. };
  688. ldo10 {
  689. regulator-name = "+2.8V_RUN_CAM_AF";
  690. regulator-min-microvolt = <2800000>;
  691. regulator-max-microvolt = <2800000>;
  692. };
  693. ldo11 {
  694. regulator-name = "+1.8V_RUN_VPP_FUSE";
  695. regulator-min-microvolt = <1800000>;
  696. regulator-max-microvolt = <1800000>;
  697. };
  698. };
  699. };
  700. };
  701. spi@7000d400 {
  702. status = "okay";
  703. ec: cros-ec@0 {
  704. compatible = "google,cros-ec-spi";
  705. spi-max-frequency = <3000000>;
  706. interrupt-parent = <&gpio>;
  707. interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
  708. reg = <0>;
  709. google,cros-ec-spi-msg-delay = <2000>;
  710. i2c_20: i2c-tunnel {
  711. compatible = "google,cros-ec-i2c-tunnel";
  712. #address-cells = <1>;
  713. #size-cells = <0>;
  714. google,remote-bus = <0>;
  715. charger: bq24735 {
  716. compatible = "ti,bq24735";
  717. reg = <0x9>;
  718. interrupt-parent = <&gpio>;
  719. interrupts = <TEGRA_GPIO(J, 0)
  720. GPIO_ACTIVE_HIGH>;
  721. ti,ac-detect-gpios = <&gpio
  722. TEGRA_GPIO(J, 0)
  723. GPIO_ACTIVE_HIGH>;
  724. };
  725. battery: smart-battery {
  726. compatible = "sbs,sbs-battery";
  727. reg = <0xb>;
  728. battery-name = "battery";
  729. sbs,i2c-retry-count = <2>;
  730. sbs,poll-retry-count = <10>;
  731. /* power-supplies = <&charger>; */
  732. };
  733. };
  734. keyboard-controller {
  735. compatible = "google,cros-ec-keyb";
  736. keypad,num-rows = <8>;
  737. keypad,num-columns = <13>;
  738. google,needs-ghost-filter;
  739. linux,keymap =
  740. <MATRIX_KEY(0x00, 0x01, KEY_LEFTMETA)
  741. MATRIX_KEY(0x00, 0x02, KEY_F1)
  742. MATRIX_KEY(0x00, 0x03, KEY_B)
  743. MATRIX_KEY(0x00, 0x04, KEY_F10)
  744. MATRIX_KEY(0x00, 0x06, KEY_N)
  745. MATRIX_KEY(0x00, 0x08, KEY_EQUAL)
  746. MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT)
  747. MATRIX_KEY(0x01, 0x01, KEY_ESC)
  748. MATRIX_KEY(0x01, 0x02, KEY_F4)
  749. MATRIX_KEY(0x01, 0x03, KEY_G)
  750. MATRIX_KEY(0x01, 0x04, KEY_F7)
  751. MATRIX_KEY(0x01, 0x06, KEY_H)
  752. MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE)
  753. MATRIX_KEY(0x01, 0x09, KEY_F9)
  754. MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE)
  755. MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL)
  756. MATRIX_KEY(0x02, 0x01, KEY_TAB)
  757. MATRIX_KEY(0x02, 0x02, KEY_F3)
  758. MATRIX_KEY(0x02, 0x03, KEY_T)
  759. MATRIX_KEY(0x02, 0x04, KEY_F6)
  760. MATRIX_KEY(0x02, 0x05, KEY_RIGHTBRACE)
  761. MATRIX_KEY(0x02, 0x06, KEY_Y)
  762. MATRIX_KEY(0x02, 0x07, KEY_102ND)
  763. MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE)
  764. MATRIX_KEY(0x02, 0x09, KEY_F8)
  765. MATRIX_KEY(0x03, 0x01, KEY_GRAVE)
  766. MATRIX_KEY(0x03, 0x02, KEY_F2)
  767. MATRIX_KEY(0x03, 0x03, KEY_5)
  768. MATRIX_KEY(0x03, 0x04, KEY_F5)
  769. MATRIX_KEY(0x03, 0x06, KEY_6)
  770. MATRIX_KEY(0x03, 0x08, KEY_MINUS)
  771. MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH)
  772. MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL)
  773. MATRIX_KEY(0x04, 0x01, KEY_A)
  774. MATRIX_KEY(0x04, 0x02, KEY_D)
  775. MATRIX_KEY(0x04, 0x03, KEY_F)
  776. MATRIX_KEY(0x04, 0x04, KEY_S)
  777. MATRIX_KEY(0x04, 0x05, KEY_K)
  778. MATRIX_KEY(0x04, 0x06, KEY_J)
  779. MATRIX_KEY(0x04, 0x08, KEY_SEMICOLON)
  780. MATRIX_KEY(0x04, 0x09, KEY_L)
  781. MATRIX_KEY(0x04, 0x0a, KEY_BACKSLASH)
  782. MATRIX_KEY(0x04, 0x0b, KEY_ENTER)
  783. MATRIX_KEY(0x05, 0x01, KEY_Z)
  784. MATRIX_KEY(0x05, 0x02, KEY_C)
  785. MATRIX_KEY(0x05, 0x03, KEY_V)
  786. MATRIX_KEY(0x05, 0x04, KEY_X)
  787. MATRIX_KEY(0x05, 0x05, KEY_COMMA)
  788. MATRIX_KEY(0x05, 0x06, KEY_M)
  789. MATRIX_KEY(0x05, 0x07, KEY_LEFTSHIFT)
  790. MATRIX_KEY(0x05, 0x08, KEY_SLASH)
  791. MATRIX_KEY(0x05, 0x09, KEY_DOT)
  792. MATRIX_KEY(0x05, 0x0b, KEY_SPACE)
  793. MATRIX_KEY(0x06, 0x01, KEY_1)
  794. MATRIX_KEY(0x06, 0x02, KEY_3)
  795. MATRIX_KEY(0x06, 0x03, KEY_4)
  796. MATRIX_KEY(0x06, 0x04, KEY_2)
  797. MATRIX_KEY(0x06, 0x05, KEY_8)
  798. MATRIX_KEY(0x06, 0x06, KEY_7)
  799. MATRIX_KEY(0x06, 0x08, KEY_0)
  800. MATRIX_KEY(0x06, 0x09, KEY_9)
  801. MATRIX_KEY(0x06, 0x0a, KEY_LEFTALT)
  802. MATRIX_KEY(0x06, 0x0b, KEY_DOWN)
  803. MATRIX_KEY(0x06, 0x0c, KEY_RIGHT)
  804. MATRIX_KEY(0x07, 0x01, KEY_Q)
  805. MATRIX_KEY(0x07, 0x02, KEY_E)
  806. MATRIX_KEY(0x07, 0x03, KEY_R)
  807. MATRIX_KEY(0x07, 0x04, KEY_W)
  808. MATRIX_KEY(0x07, 0x05, KEY_I)
  809. MATRIX_KEY(0x07, 0x06, KEY_U)
  810. MATRIX_KEY(0x07, 0x07, KEY_RIGHTSHIFT)
  811. MATRIX_KEY(0x07, 0x08, KEY_P)
  812. MATRIX_KEY(0x07, 0x09, KEY_O)
  813. MATRIX_KEY(0x07, 0x0b, KEY_UP)
  814. MATRIX_KEY(0x07, 0x0c, KEY_LEFT)>;
  815. };
  816. };
  817. };
  818. pmc@7000e400 {
  819. nvidia,invert-interrupt;
  820. nvidia,suspend-mode = <0>;
  821. #wake-cells = <3>;
  822. nvidia,cpu-pwr-good-time = <500>;
  823. nvidia,cpu-pwr-off-time = <300>;
  824. nvidia,core-pwr-good-time = <641 3845>;
  825. nvidia,core-pwr-off-time = <61036>;
  826. nvidia,core-power-req-active-high;
  827. nvidia,sys-clock-req-active-high;
  828. nvidia,reset-gpio = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
  829. };
  830. /* WIFI/BT module */
  831. sdhci@700b0000 {
  832. status = "disabled";
  833. };
  834. /* external SD/MMC */
  835. sdhci@700b0400 {
  836. cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
  837. power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
  838. wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>;
  839. status = "okay";
  840. bus-width = <4>;
  841. vqmmc-supply = <&vddio_sdmmc3>;
  842. };
  843. /* EMMC 4.51 */
  844. sdhci@700b0600 {
  845. status = "okay";
  846. bus-width = <8>;
  847. non-removable;
  848. };
  849. usb@7d000000 {
  850. status = "okay";
  851. };
  852. usb-phy@7d000000 {
  853. status = "okay";
  854. vbus-supply = <&vdd_usb1_vbus>;
  855. };
  856. usb@7d004000 {
  857. status = "okay";
  858. };
  859. usb-phy@7d004000 {
  860. status = "okay";
  861. vbus-supply = <&vdd_run_cam>;
  862. };
  863. usb@7d008000 {
  864. status = "okay";
  865. };
  866. usb-phy@7d008000 {
  867. status = "okay";
  868. vbus-supply = <&vdd_usb3_vbus>;
  869. };
  870. backlight: backlight {
  871. compatible = "pwm-backlight";
  872. enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
  873. power-supply = <&vdd_led>;
  874. pwms = <&pwm 1 1000000>;
  875. brightness-levels = <0 4 8 16 32 64 128 255>;
  876. default-brightness-level = <6>;
  877. backlight-boot-off;
  878. };
  879. clocks {
  880. compatible = "simple-bus";
  881. #address-cells = <1>;
  882. #size-cells = <0>;
  883. clk32k_in: clock@0 {
  884. compatible = "fixed-clock";
  885. reg=<0>;
  886. #clock-cells = <0>;
  887. clock-frequency = <32768>;
  888. };
  889. };
  890. gpio-keys {
  891. compatible = "gpio-keys";
  892. lid {
  893. label = "Lid";
  894. gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>;
  895. linux,input-type = <5>;
  896. linux,code = <0>;
  897. debounce-interval = <1>;
  898. wakeup-source;
  899. };
  900. power {
  901. label = "Power";
  902. gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
  903. linux,code = <KEY_POWER>;
  904. debounce-interval = <10>;
  905. wakeup-source;
  906. };
  907. };
  908. panel: panel {
  909. compatible = "innolux,n116bge", "simple-panel";
  910. backlight = <&backlight>;
  911. ddc-i2c-bus = <&dpaux>;
  912. };
  913. regulators {
  914. compatible = "simple-bus";
  915. #address-cells = <1>;
  916. #size-cells = <0>;
  917. vdd_mux: regulator@0 {
  918. compatible = "regulator-fixed";
  919. reg = <0>;
  920. regulator-name = "+VDD_MUX";
  921. regulator-min-microvolt = <19000000>;
  922. regulator-max-microvolt = <19000000>;
  923. regulator-always-on;
  924. regulator-boot-on;
  925. };
  926. vdd_5v0_sys: regulator@1 {
  927. compatible = "regulator-fixed";
  928. reg = <1>;
  929. regulator-name = "+5V_SYS";
  930. regulator-min-microvolt = <5000000>;
  931. regulator-max-microvolt = <5000000>;
  932. regulator-always-on;
  933. regulator-boot-on;
  934. vin-supply = <&vdd_mux>;
  935. };
  936. vdd_3v3_sys: regulator@2 {
  937. compatible = "regulator-fixed";
  938. reg = <2>;
  939. regulator-name = "+3.3V_SYS";
  940. regulator-min-microvolt = <3300000>;
  941. regulator-max-microvolt = <3300000>;
  942. regulator-always-on;
  943. regulator-boot-on;
  944. vin-supply = <&vdd_mux>;
  945. };
  946. vdd_3v3_run: regulator@3 {
  947. compatible = "regulator-fixed";
  948. reg = <3>;
  949. regulator-name = "+3.3V_RUN";
  950. regulator-min-microvolt = <3300000>;
  951. regulator-max-microvolt = <3300000>;
  952. regulator-always-on;
  953. regulator-boot-on;
  954. gpio = <&as3722 1 GPIO_ACTIVE_HIGH>;
  955. enable-active-high;
  956. vin-supply = <&vdd_3v3_sys>;
  957. };
  958. vdd_3v3_hdmi: regulator@4 {
  959. compatible = "regulator-fixed";
  960. reg = <4>;
  961. regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
  962. regulator-min-microvolt = <3300000>;
  963. regulator-max-microvolt = <3300000>;
  964. vin-supply = <&vdd_3v3_run>;
  965. };
  966. vdd_led: regulator@5 {
  967. compatible = "regulator-fixed";
  968. reg = <5>;
  969. regulator-name = "+VDD_LED";
  970. regulator-min-microvolt = <3300000>;
  971. regulator-max-microvolt = <3300000>;
  972. gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
  973. enable-active-high;
  974. vin-supply = <&vdd_mux>;
  975. };
  976. vdd_usb1_vbus: regulator@6 {
  977. compatible = "regulator-fixed";
  978. reg = <6>;
  979. regulator-name = "+5V_USB_HS";
  980. regulator-min-microvolt = <5000000>;
  981. regulator-max-microvolt = <5000000>;
  982. gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
  983. enable-active-high;
  984. gpio-open-drain;
  985. vin-supply = <&vdd_5v0_sys>;
  986. };
  987. vdd_usb3_vbus: regulator@7 {
  988. compatible = "regulator-fixed";
  989. reg = <7>;
  990. regulator-name = "+5V_USB_SS";
  991. regulator-min-microvolt = <5000000>;
  992. regulator-max-microvolt = <5000000>;
  993. gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
  994. enable-active-high;
  995. gpio-open-drain;
  996. vin-supply = <&vdd_5v0_sys>;
  997. };
  998. vdd_3v3_panel: regulator@8 {
  999. compatible = "regulator-fixed";
  1000. reg = <8>;
  1001. regulator-name = "+3.3V_PANEL";
  1002. regulator-min-microvolt = <3300000>;
  1003. regulator-max-microvolt = <3300000>;
  1004. gpio = <&as3722 4 GPIO_ACTIVE_HIGH>;
  1005. enable-active-high;
  1006. vin-supply = <&vdd_3v3_sys>;
  1007. };
  1008. vdd_hdmi_pll: regulator@9 {
  1009. compatible = "regulator-fixed";
  1010. reg = <9>;
  1011. regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL_AP_GATE";
  1012. regulator-min-microvolt = <1050000>;
  1013. regulator-max-microvolt = <1050000>;
  1014. gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
  1015. vin-supply = <&vdd_1v05_run>;
  1016. };
  1017. vdd_5v0_hdmi: regulator@10 {
  1018. compatible = "regulator-fixed";
  1019. reg = <10>;
  1020. regulator-name = "+5V_HDMI_CON";
  1021. regulator-min-microvolt = <5000000>;
  1022. regulator-max-microvolt = <5000000>;
  1023. gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
  1024. enable-active-high;
  1025. vin-supply = <&vdd_5v0_sys>;
  1026. };
  1027. vdd_5v0_ts: regulator@11 {
  1028. compatible = "regulator-fixed";
  1029. reg = <11>;
  1030. regulator-name = "+5V_VDD_TS";
  1031. regulator-min-microvolt = <5000000>;
  1032. regulator-max-microvolt = <5000000>;
  1033. regulator-always-on;
  1034. regulator-boot-on;
  1035. gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
  1036. enable-active-high;
  1037. };
  1038. };
  1039. };