exynos5433-bus.dtsi 4.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Samsung's Exynos5433 SoC Memory interface and AMBA bus device tree source
  4. *
  5. * Copyright (c) 2016 Samsung Electronics Co., Ltd.
  6. * Chanwoo Choi <cw00.choi@samsung.com>
  7. */
  8. &soc {
  9. bus_g2d_400: bus0 {
  10. compatible = "samsung,exynos-bus";
  11. clocks = <&cmu_top CLK_ACLK_G2D_400>;
  12. clock-names = "bus";
  13. operating-points-v2 = <&bus_g2d_400_opp_table>;
  14. status = "disabled";
  15. };
  16. bus_g2d_266: bus1 {
  17. compatible = "samsung,exynos-bus";
  18. clocks = <&cmu_top CLK_ACLK_G2D_266>;
  19. clock-names = "bus";
  20. operating-points-v2 = <&bus_g2d_266_opp_table>;
  21. status = "disabled";
  22. };
  23. bus_gscl: bus2 {
  24. compatible = "samsung,exynos-bus";
  25. clocks = <&cmu_top CLK_ACLK_GSCL_333>;
  26. clock-names = "bus";
  27. operating-points-v2 = <&bus_gscl_opp_table>;
  28. status = "disabled";
  29. };
  30. bus_hevc: bus3 {
  31. compatible = "samsung,exynos-bus";
  32. clocks = <&cmu_top CLK_ACLK_HEVC_400>;
  33. clock-names = "bus";
  34. operating-points-v2 = <&bus_hevc_opp_table>;
  35. status = "disabled";
  36. };
  37. bus_jpeg: bus4 {
  38. compatible = "samsung,exynos-bus";
  39. clocks = <&cmu_top CLK_SCLK_JPEG_MSCL>;
  40. clock-names = "bus";
  41. operating-points-v2 = <&bus_g2d_400_opp_table>;
  42. status = "disabled";
  43. };
  44. bus_mfc: bus5 {
  45. compatible = "samsung,exynos-bus";
  46. clocks = <&cmu_top CLK_ACLK_MFC_400>;
  47. clock-names = "bus";
  48. operating-points-v2 = <&bus_g2d_400_opp_table>;
  49. status = "disabled";
  50. };
  51. bus_mscl: bus6 {
  52. compatible = "samsung,exynos-bus";
  53. clocks = <&cmu_top CLK_ACLK_MSCL_400>;
  54. clock-names = "bus";
  55. operating-points-v2 = <&bus_g2d_400_opp_table>;
  56. status = "disabled";
  57. };
  58. bus_noc0: bus7 {
  59. compatible = "samsung,exynos-bus";
  60. clocks = <&cmu_top CLK_ACLK_BUS0_400>;
  61. clock-names = "bus";
  62. operating-points-v2 = <&bus_hevc_opp_table>;
  63. status = "disabled";
  64. };
  65. bus_noc1: bus8 {
  66. compatible = "samsung,exynos-bus";
  67. clocks = <&cmu_top CLK_ACLK_BUS1_400>;
  68. clock-names = "bus";
  69. operating-points-v2 = <&bus_hevc_opp_table>;
  70. status = "disabled";
  71. };
  72. bus_noc2: bus9 {
  73. compatible = "samsung,exynos-bus";
  74. clocks = <&cmu_mif CLK_ACLK_BUS2_400>;
  75. clock-names = "bus";
  76. operating-points-v2 = <&bus_noc2_opp_table>;
  77. status = "disabled";
  78. };
  79. bus_g2d_400_opp_table: opp_table2 {
  80. compatible = "operating-points-v2";
  81. opp-shared;
  82. opp-400000000 {
  83. opp-hz = /bits/ 64 <400000000>;
  84. opp-microvolt = <1075000>;
  85. };
  86. opp-267000000 {
  87. opp-hz = /bits/ 64 <267000000>;
  88. opp-microvolt = <1000000>;
  89. };
  90. opp-200000000 {
  91. opp-hz = /bits/ 64 <200000000>;
  92. opp-microvolt = <975000>;
  93. };
  94. opp-160000000 {
  95. opp-hz = /bits/ 64 <160000000>;
  96. opp-microvolt = <962500>;
  97. };
  98. opp-134000000 {
  99. opp-hz = /bits/ 64 <134000000>;
  100. opp-microvolt = <950000>;
  101. };
  102. opp-100000000 {
  103. opp-hz = /bits/ 64 <100000000>;
  104. opp-microvolt = <937500>;
  105. };
  106. };
  107. bus_g2d_266_opp_table: opp_table3 {
  108. compatible = "operating-points-v2";
  109. opp-267000000 {
  110. opp-hz = /bits/ 64 <267000000>;
  111. };
  112. opp-200000000 {
  113. opp-hz = /bits/ 64 <200000000>;
  114. };
  115. opp-160000000 {
  116. opp-hz = /bits/ 64 <160000000>;
  117. };
  118. opp-134000000 {
  119. opp-hz = /bits/ 64 <134000000>;
  120. };
  121. opp-100000000 {
  122. opp-hz = /bits/ 64 <100000000>;
  123. };
  124. };
  125. bus_gscl_opp_table: opp_table4 {
  126. compatible = "operating-points-v2";
  127. opp-333000000 {
  128. opp-hz = /bits/ 64 <333000000>;
  129. };
  130. opp-222000000 {
  131. opp-hz = /bits/ 64 <222000000>;
  132. };
  133. opp-166500000 {
  134. opp-hz = /bits/ 64 <166500000>;
  135. };
  136. };
  137. bus_hevc_opp_table: opp_table5 {
  138. compatible = "operating-points-v2";
  139. opp-shared;
  140. opp-400000000 {
  141. opp-hz = /bits/ 64 <400000000>;
  142. };
  143. opp-267000000 {
  144. opp-hz = /bits/ 64 <267000000>;
  145. };
  146. opp-200000000 {
  147. opp-hz = /bits/ 64 <200000000>;
  148. };
  149. opp-160000000 {
  150. opp-hz = /bits/ 64 <160000000>;
  151. };
  152. opp-134000000 {
  153. opp-hz = /bits/ 64 <134000000>;
  154. };
  155. opp-100000000 {
  156. opp-hz = /bits/ 64 <100000000>;
  157. };
  158. };
  159. bus_noc2_opp_table: opp_table6 {
  160. compatible = "operating-points-v2";
  161. opp-400000000 {
  162. opp-hz = /bits/ 64 <400000000>;
  163. };
  164. opp-200000000 {
  165. opp-hz = /bits/ 64 <200000000>;
  166. };
  167. opp-134000000 {
  168. opp-hz = /bits/ 64 <134000000>;
  169. };
  170. opp-100000000 {
  171. opp-hz = /bits/ 64 <100000000>;
  172. };
  173. };
  174. };