socfpga_stratix10_socdk.dts 3.4 KB

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  1. /*
  2. * Copyright Altera Corporation (C) 2015. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms and conditions of the GNU General Public License,
  6. * version 2, as published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope it will be useful, but WITHOUT
  9. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  11. * more details.
  12. *
  13. * You should have received a copy of the GNU General Public License along with
  14. * this program. If not, see <http://www.gnu.org/licenses/>.
  15. */
  16. #include "socfpga_stratix10.dtsi"
  17. / {
  18. model = "SoCFPGA Stratix 10 SoCDK";
  19. aliases {
  20. serial0 = &uart0;
  21. };
  22. chosen {
  23. stdout-path = "serial0:115200n8";
  24. };
  25. leds {
  26. compatible = "gpio-leds";
  27. hps0 {
  28. label = "hps_led0";
  29. gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
  30. };
  31. hps1 {
  32. label = "hps_led1";
  33. gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
  34. };
  35. hps2 {
  36. label = "hps_led2";
  37. gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
  38. };
  39. };
  40. memory {
  41. device_type = "memory";
  42. /* We expect the bootloader to fill in the reg */
  43. reg = <0 0 0 0>;
  44. };
  45. ref_033v: 033-v-ref {
  46. compatible = "regulator-fixed";
  47. regulator-name = "0.33V";
  48. regulator-min-microvolt = <330000>;
  49. regulator-max-microvolt = <330000>;
  50. };
  51. soc {
  52. clocks {
  53. osc1 {
  54. clock-frequency = <25000000>;
  55. };
  56. };
  57. };
  58. };
  59. &gpio1 {
  60. status = "okay";
  61. };
  62. &gmac0 {
  63. status = "okay";
  64. phy-mode = "rgmii";
  65. phy-handle = <&phy0>;
  66. max-frame-size = <9000>;
  67. mdio0 {
  68. #address-cells = <1>;
  69. #size-cells = <0>;
  70. compatible = "snps,dwmac-mdio";
  71. phy0: ethernet-phy@0 {
  72. reg = <4>;
  73. txd0-skew-ps = <0>; /* -420ps */
  74. txd1-skew-ps = <0>; /* -420ps */
  75. txd2-skew-ps = <0>; /* -420ps */
  76. txd3-skew-ps = <0>; /* -420ps */
  77. rxd0-skew-ps = <420>; /* 0ps */
  78. rxd1-skew-ps = <420>; /* 0ps */
  79. rxd2-skew-ps = <420>; /* 0ps */
  80. rxd3-skew-ps = <420>; /* 0ps */
  81. txen-skew-ps = <0>; /* -420ps */
  82. txc-skew-ps = <900>; /* 0ps */
  83. rxdv-skew-ps = <420>; /* 0ps */
  84. rxc-skew-ps = <1680>; /* 780ps */
  85. };
  86. };
  87. };
  88. &mmc {
  89. status = "okay";
  90. cap-sd-highspeed;
  91. broken-cd;
  92. bus-width = <4>;
  93. };
  94. &uart0 {
  95. status = "okay";
  96. };
  97. &usb0 {
  98. status = "okay";
  99. disable-over-current;
  100. };
  101. &watchdog0 {
  102. status = "okay";
  103. };
  104. &i2c1 {
  105. status = "okay";
  106. clock-frequency = <100000>;
  107. i2c-sda-falling-time-ns = <890>; /* hcnt */
  108. i2c-sdl-falling-time-ns = <890>; /* lcnt */
  109. adc@14 {
  110. compatible = "lltc,ltc2497";
  111. reg = <0x14>;
  112. vref-supply = <&ref_033v>;
  113. };
  114. temp@4c {
  115. compatible = "maxim,max1619";
  116. reg = <0x4c>;
  117. };
  118. eeprom@51 {
  119. compatible = "atmel,24c32";
  120. reg = <0x51>;
  121. pagesize = <32>;
  122. };
  123. rtc@68 {
  124. compatible = "dallas,ds1339";
  125. reg = <0x68>;
  126. };
  127. };
  128. &qspi {
  129. flash@0 {
  130. #address-cells = <1>;
  131. #size-cells = <1>;
  132. compatible = "n25q00a";
  133. reg = <0>;
  134. spi-max-frequency = <50000000>;
  135. m25p,fast-read;
  136. cdns,page-size = <256>;
  137. cdns,block-size = <16>;
  138. cdns,read-delay = <1>;
  139. cdns,tshsl-ns = <50>;
  140. cdns,tsd2d-ns = <50>;
  141. cdns,tchsh-ns = <4>;
  142. cdns,tslch-ns = <4>;
  143. partitions {
  144. compatible = "fixed-partitions";
  145. #address-cells = <1>;
  146. #size-cells = <1>;
  147. qspi_boot: partition@0 {
  148. label = "Boot and fpga data";
  149. reg = <0x0 0x4000000>;
  150. };
  151. qspi_rootfs: partition@4000000 {
  152. label = "Root Filesystem - JFFS2";
  153. reg = <0x4000000 0x4000000>;
  154. };
  155. };
  156. };
  157. };