headsmp.S 2.0 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182
  1. /* SPDX-License-Identifier: GPL-2.0
  2. *
  3. * Copyright (c) 2018 Chen-Yu Tsai
  4. * Copyright (c) 2018 Bootlin
  5. *
  6. * Chen-Yu Tsai <wens@csie.org>
  7. * Mylène Josserand <mylene.josserand@bootlin.com>
  8. *
  9. * SMP support for sunxi based systems with Cortex A7/A15
  10. *
  11. */
  12. #include <linux/linkage.h>
  13. #include <asm/assembler.h>
  14. #include <asm/cputype.h>
  15. ENTRY(sunxi_mc_smp_cluster_cache_enable)
  16. .arch armv7-a
  17. /*
  18. * Enable cluster-level coherency, in preparation for turning on the MMU.
  19. *
  20. * Also enable regional clock gating and L2 data latency settings for
  21. * Cortex-A15. These settings are from the vendor kernel.
  22. */
  23. mrc p15, 0, r1, c0, c0, 0
  24. movw r2, #(ARM_CPU_PART_MASK & 0xffff)
  25. movt r2, #(ARM_CPU_PART_MASK >> 16)
  26. and r1, r1, r2
  27. movw r2, #(ARM_CPU_PART_CORTEX_A15 & 0xffff)
  28. movt r2, #(ARM_CPU_PART_CORTEX_A15 >> 16)
  29. cmp r1, r2
  30. bne not_a15
  31. /* The following is Cortex-A15 specific */
  32. /* ACTLR2: Enable CPU regional clock gates */
  33. mrc p15, 1, r1, c15, c0, 4
  34. orr r1, r1, #(0x1 << 31)
  35. mcr p15, 1, r1, c15, c0, 4
  36. /* L2ACTLR */
  37. mrc p15, 1, r1, c15, c0, 0
  38. /* Enable L2, GIC, and Timer regional clock gates */
  39. orr r1, r1, #(0x1 << 26)
  40. /* Disable clean/evict from being pushed to external */
  41. orr r1, r1, #(0x1<<3)
  42. mcr p15, 1, r1, c15, c0, 0
  43. /* L2CTRL: L2 data RAM latency */
  44. mrc p15, 1, r1, c9, c0, 2
  45. bic r1, r1, #(0x7 << 0)
  46. orr r1, r1, #(0x3 << 0)
  47. mcr p15, 1, r1, c9, c0, 2
  48. /* End of Cortex-A15 specific setup */
  49. not_a15:
  50. /* Get value of sunxi_mc_smp_first_comer */
  51. adr r1, first
  52. ldr r0, [r1]
  53. ldr r0, [r1, r0]
  54. /* Skip cci_enable_port_for_self if not first comer */
  55. cmp r0, #0
  56. bxeq lr
  57. b cci_enable_port_for_self
  58. .align 2
  59. first: .word sunxi_mc_smp_first_comer - .
  60. ENDPROC(sunxi_mc_smp_cluster_cache_enable)
  61. ENTRY(sunxi_mc_smp_secondary_startup)
  62. bl sunxi_mc_smp_cluster_cache_enable
  63. bl secure_cntvoff_init
  64. b secondary_startup
  65. ENDPROC(sunxi_mc_smp_secondary_startup)
  66. ENTRY(sunxi_mc_smp_resume)
  67. bl sunxi_mc_smp_cluster_cache_enable
  68. b cpu_resume
  69. ENDPROC(sunxi_mc_smp_resume)