exynos.S 1.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com
  5. */
  6. /* pull in the relevant register and map files. */
  7. #define S3C_ADDR_BASE 0xF6000000
  8. #define S3C_VA_UART S3C_ADDR_BASE + 0x01000000
  9. #define EXYNOS4_PA_UART 0x13800000
  10. #define EXYNOS5_PA_UART 0x12C00000
  11. /* note, for the boot process to work we have to keep the UART
  12. * virtual address aligned to an 1MiB boundary for the L1
  13. * mapping the head code makes. We keep the UART virtual address
  14. * aligned and add in the offset when we load the value here.
  15. */
  16. .macro addruart, rp, rv, tmp
  17. mrc p15, 0, \tmp, c0, c0, 0
  18. and \tmp, \tmp, #0xf0
  19. teq \tmp, #0xf0 @@ A15
  20. beq 100f
  21. mrc p15, 0, \tmp, c0, c0, 5
  22. and \tmp, \tmp, #0xf00
  23. teq \tmp, #0x100 @@ A15 + A7 but boot to A7
  24. 100: ldreq \rp, =EXYNOS5_PA_UART
  25. movne \rp, #EXYNOS4_PA_UART @@ EXYNOS4
  26. ldr \rv, =S3C_VA_UART
  27. #if CONFIG_DEBUG_S3C_UART != 0
  28. add \rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART)
  29. add \rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART)
  30. #endif
  31. .endm
  32. #define fifo_full fifo_full_s5pv210
  33. #define fifo_level fifo_level_s5pv210
  34. #include <debug/samsung.S>