Kconfig 1.9 KB

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  1. # SPDX-License-Identifier: GPL-2.0
  2. #
  3. # For a description of the syntax of this configuration file,
  4. # see Documentation/kbuild/kconfig-language.txt.
  5. #
  6. menuconfig ARC_PLAT_EZNPS
  7. bool "\"EZchip\" ARC dev platform"
  8. select CPU_BIG_ENDIAN
  9. select CLKSRC_NPS if !PHYS_ADDR_T_64BIT
  10. select EZNPS_GIC
  11. select EZCHIP_NPS_MANAGEMENT_ENET if ETHERNET
  12. help
  13. Support for EZchip development platforms,
  14. based on ARC700 cores.
  15. We handle few flavors:
  16. - Hardware Emulator AKA HE which is FPGA based chassis
  17. - Simulator based on MetaWare nSIM
  18. - NPS400 chip based on ASIC
  19. config EZNPS_MTM_EXT
  20. bool "ARC-EZchip MTM Extensions"
  21. select CPUMASK_OFFSTACK
  22. depends on ARC_PLAT_EZNPS && SMP
  23. default y
  24. help
  25. Here we add new hierarchy for CPUs topology.
  26. We got:
  27. Core
  28. Thread
  29. At the new thread level each CPU represent one HW thread.
  30. At highest hierarchy each core contain 16 threads,
  31. any of them seem like CPU from Linux point of view.
  32. All threads within same core share the execution unit of the
  33. core and HW scheduler round robin between them.
  34. config EZNPS_MEM_ERROR_ALIGN
  35. bool "ARC-EZchip Memory error as an exception"
  36. depends on EZNPS_MTM_EXT
  37. default n
  38. help
  39. On the real chip of the NPS, user memory errors are handled
  40. as a machine check exception, which is fatal, whereas on
  41. simulator platform for NPS, is handled as a Level 2 interrupt
  42. (just a stock ARC700) which is recoverable. This option makes
  43. simulator behave like hardware.
  44. config EZNPS_SHARED_AUX_REGS
  45. bool "ARC-EZchip Shared Auxiliary Registers Per Core"
  46. depends on ARC_PLAT_EZNPS
  47. default y
  48. help
  49. On the real chip of the NPS, auxiliary registers are shared between
  50. all the cpus of the core, whereas on simulator platform for NPS,
  51. each cpu has a different set of auxiliary registers. Configuration
  52. should be unset if auxiliary registers are not shared between the cpus
  53. of the core, so there will be a need to initialize them per cpu.