smc_wr.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Shared Memory Communications over RDMA (SMC-R) and RoCE
  4. *
  5. * Work Requests exploiting Infiniband API
  6. *
  7. * Work requests (WR) of type ib_post_send or ib_post_recv respectively
  8. * are submitted to either RC SQ or RC RQ respectively
  9. * (reliably connected send/receive queue)
  10. * and become work queue entries (WQEs).
  11. * While an SQ WR/WQE is pending, we track it until transmission completion.
  12. * Through a send or receive completion queue (CQ) respectively,
  13. * we get completion queue entries (CQEs) [aka work completions (WCs)].
  14. * Since the CQ callback is called from IRQ context, we split work by using
  15. * bottom halves implemented by tasklets.
  16. *
  17. * SMC uses this to exchange LLC (link layer control)
  18. * and CDC (connection data control) messages.
  19. *
  20. * Copyright IBM Corp. 2016
  21. *
  22. * Author(s): Steffen Maier <maier@linux.vnet.ibm.com>
  23. */
  24. #include <linux/atomic.h>
  25. #include <linux/hashtable.h>
  26. #include <linux/wait.h>
  27. #include <rdma/ib_verbs.h>
  28. #include <asm/div64.h>
  29. #include "smc.h"
  30. #include "smc_wr.h"
  31. #define SMC_WR_MAX_POLL_CQE 10 /* max. # of compl. queue elements in 1 poll */
  32. #define SMC_WR_RX_HASH_BITS 4
  33. static DEFINE_HASHTABLE(smc_wr_rx_hash, SMC_WR_RX_HASH_BITS);
  34. static DEFINE_SPINLOCK(smc_wr_rx_hash_lock);
  35. struct smc_wr_tx_pend { /* control data for a pending send request */
  36. u64 wr_id; /* work request id sent */
  37. smc_wr_tx_handler handler;
  38. enum ib_wc_status wc_status; /* CQE status */
  39. struct smc_link *link;
  40. u32 idx;
  41. struct smc_wr_tx_pend_priv priv;
  42. };
  43. /******************************** send queue *********************************/
  44. /*------------------------------- completion --------------------------------*/
  45. static inline int smc_wr_tx_find_pending_index(struct smc_link *link, u64 wr_id)
  46. {
  47. u32 i;
  48. for (i = 0; i < link->wr_tx_cnt; i++) {
  49. if (link->wr_tx_pends[i].wr_id == wr_id)
  50. return i;
  51. }
  52. return link->wr_tx_cnt;
  53. }
  54. static inline void smc_wr_tx_process_cqe(struct ib_wc *wc)
  55. {
  56. struct smc_wr_tx_pend pnd_snd;
  57. struct smc_link *link;
  58. u32 pnd_snd_idx;
  59. int i;
  60. link = wc->qp->qp_context;
  61. if (wc->opcode == IB_WC_REG_MR) {
  62. if (wc->status)
  63. link->wr_reg_state = FAILED;
  64. else
  65. link->wr_reg_state = CONFIRMED;
  66. wake_up(&link->wr_reg_wait);
  67. return;
  68. }
  69. pnd_snd_idx = smc_wr_tx_find_pending_index(link, wc->wr_id);
  70. if (pnd_snd_idx == link->wr_tx_cnt)
  71. return;
  72. link->wr_tx_pends[pnd_snd_idx].wc_status = wc->status;
  73. memcpy(&pnd_snd, &link->wr_tx_pends[pnd_snd_idx], sizeof(pnd_snd));
  74. /* clear the full struct smc_wr_tx_pend including .priv */
  75. memset(&link->wr_tx_pends[pnd_snd_idx], 0,
  76. sizeof(link->wr_tx_pends[pnd_snd_idx]));
  77. memset(&link->wr_tx_bufs[pnd_snd_idx], 0,
  78. sizeof(link->wr_tx_bufs[pnd_snd_idx]));
  79. if (!test_and_clear_bit(pnd_snd_idx, link->wr_tx_mask))
  80. return;
  81. if (wc->status) {
  82. for_each_set_bit(i, link->wr_tx_mask, link->wr_tx_cnt) {
  83. /* clear full struct smc_wr_tx_pend including .priv */
  84. memset(&link->wr_tx_pends[i], 0,
  85. sizeof(link->wr_tx_pends[i]));
  86. memset(&link->wr_tx_bufs[i], 0,
  87. sizeof(link->wr_tx_bufs[i]));
  88. clear_bit(i, link->wr_tx_mask);
  89. }
  90. /* terminate connections of this link group abnormally */
  91. smc_lgr_terminate(smc_get_lgr(link));
  92. }
  93. if (pnd_snd.handler)
  94. pnd_snd.handler(&pnd_snd.priv, link, wc->status);
  95. wake_up(&link->wr_tx_wait);
  96. }
  97. static void smc_wr_tx_tasklet_fn(unsigned long data)
  98. {
  99. struct smc_ib_device *dev = (struct smc_ib_device *)data;
  100. struct ib_wc wc[SMC_WR_MAX_POLL_CQE];
  101. int i = 0, rc;
  102. int polled = 0;
  103. again:
  104. polled++;
  105. do {
  106. memset(&wc, 0, sizeof(wc));
  107. rc = ib_poll_cq(dev->roce_cq_send, SMC_WR_MAX_POLL_CQE, wc);
  108. if (polled == 1) {
  109. ib_req_notify_cq(dev->roce_cq_send,
  110. IB_CQ_NEXT_COMP |
  111. IB_CQ_REPORT_MISSED_EVENTS);
  112. }
  113. if (!rc)
  114. break;
  115. for (i = 0; i < rc; i++)
  116. smc_wr_tx_process_cqe(&wc[i]);
  117. } while (rc > 0);
  118. if (polled == 1)
  119. goto again;
  120. }
  121. void smc_wr_tx_cq_handler(struct ib_cq *ib_cq, void *cq_context)
  122. {
  123. struct smc_ib_device *dev = (struct smc_ib_device *)cq_context;
  124. tasklet_schedule(&dev->send_tasklet);
  125. }
  126. /*---------------------------- request submission ---------------------------*/
  127. static inline int smc_wr_tx_get_free_slot_index(struct smc_link *link, u32 *idx)
  128. {
  129. *idx = link->wr_tx_cnt;
  130. for_each_clear_bit(*idx, link->wr_tx_mask, link->wr_tx_cnt) {
  131. if (!test_and_set_bit(*idx, link->wr_tx_mask))
  132. return 0;
  133. }
  134. *idx = link->wr_tx_cnt;
  135. return -EBUSY;
  136. }
  137. /**
  138. * smc_wr_tx_get_free_slot() - returns buffer for message assembly,
  139. * and sets info for pending transmit tracking
  140. * @link: Pointer to smc_link used to later send the message.
  141. * @handler: Send completion handler function pointer.
  142. * @wr_buf: Out value returns pointer to message buffer.
  143. * @wr_pend_priv: Out value returns pointer serving as handler context.
  144. *
  145. * Return: 0 on success, or -errno on error.
  146. */
  147. int smc_wr_tx_get_free_slot(struct smc_link *link,
  148. smc_wr_tx_handler handler,
  149. struct smc_wr_buf **wr_buf,
  150. struct smc_wr_tx_pend_priv **wr_pend_priv)
  151. {
  152. struct smc_wr_tx_pend *wr_pend;
  153. u32 idx = link->wr_tx_cnt;
  154. struct ib_send_wr *wr_ib;
  155. u64 wr_id;
  156. int rc;
  157. *wr_buf = NULL;
  158. *wr_pend_priv = NULL;
  159. if (in_softirq()) {
  160. rc = smc_wr_tx_get_free_slot_index(link, &idx);
  161. if (rc)
  162. return rc;
  163. } else {
  164. rc = wait_event_timeout(
  165. link->wr_tx_wait,
  166. link->state == SMC_LNK_INACTIVE ||
  167. (smc_wr_tx_get_free_slot_index(link, &idx) != -EBUSY),
  168. SMC_WR_TX_WAIT_FREE_SLOT_TIME);
  169. if (!rc) {
  170. /* timeout - terminate connections */
  171. smc_lgr_terminate(smc_get_lgr(link));
  172. return -EPIPE;
  173. }
  174. if (idx == link->wr_tx_cnt)
  175. return -EPIPE;
  176. }
  177. wr_id = smc_wr_tx_get_next_wr_id(link);
  178. wr_pend = &link->wr_tx_pends[idx];
  179. wr_pend->wr_id = wr_id;
  180. wr_pend->handler = handler;
  181. wr_pend->link = link;
  182. wr_pend->idx = idx;
  183. wr_ib = &link->wr_tx_ibs[idx];
  184. wr_ib->wr_id = wr_id;
  185. *wr_buf = &link->wr_tx_bufs[idx];
  186. *wr_pend_priv = &wr_pend->priv;
  187. return 0;
  188. }
  189. int smc_wr_tx_put_slot(struct smc_link *link,
  190. struct smc_wr_tx_pend_priv *wr_pend_priv)
  191. {
  192. struct smc_wr_tx_pend *pend;
  193. pend = container_of(wr_pend_priv, struct smc_wr_tx_pend, priv);
  194. if (pend->idx < link->wr_tx_cnt) {
  195. u32 idx = pend->idx;
  196. /* clear the full struct smc_wr_tx_pend including .priv */
  197. memset(&link->wr_tx_pends[pend->idx], 0,
  198. sizeof(link->wr_tx_pends[pend->idx]));
  199. memset(&link->wr_tx_bufs[pend->idx], 0,
  200. sizeof(link->wr_tx_bufs[pend->idx]));
  201. test_and_clear_bit(idx, link->wr_tx_mask);
  202. return 1;
  203. }
  204. return 0;
  205. }
  206. /* Send prepared WR slot via ib_post_send.
  207. * @priv: pointer to smc_wr_tx_pend_priv identifying prepared message buffer
  208. */
  209. int smc_wr_tx_send(struct smc_link *link, struct smc_wr_tx_pend_priv *priv)
  210. {
  211. struct smc_wr_tx_pend *pend;
  212. int rc;
  213. ib_req_notify_cq(link->smcibdev->roce_cq_send,
  214. IB_CQ_NEXT_COMP | IB_CQ_REPORT_MISSED_EVENTS);
  215. pend = container_of(priv, struct smc_wr_tx_pend, priv);
  216. rc = ib_post_send(link->roce_qp, &link->wr_tx_ibs[pend->idx], NULL);
  217. if (rc) {
  218. smc_wr_tx_put_slot(link, priv);
  219. smc_lgr_terminate(smc_get_lgr(link));
  220. }
  221. return rc;
  222. }
  223. /* Register a memory region and wait for result. */
  224. int smc_wr_reg_send(struct smc_link *link, struct ib_mr *mr)
  225. {
  226. int rc;
  227. ib_req_notify_cq(link->smcibdev->roce_cq_send,
  228. IB_CQ_NEXT_COMP | IB_CQ_REPORT_MISSED_EVENTS);
  229. link->wr_reg_state = POSTED;
  230. link->wr_reg.wr.wr_id = (u64)(uintptr_t)mr;
  231. link->wr_reg.mr = mr;
  232. link->wr_reg.key = mr->rkey;
  233. rc = ib_post_send(link->roce_qp, &link->wr_reg.wr, NULL);
  234. if (rc)
  235. return rc;
  236. rc = wait_event_interruptible_timeout(link->wr_reg_wait,
  237. (link->wr_reg_state != POSTED),
  238. SMC_WR_REG_MR_WAIT_TIME);
  239. if (!rc) {
  240. /* timeout - terminate connections */
  241. smc_lgr_terminate(smc_get_lgr(link));
  242. return -EPIPE;
  243. }
  244. if (rc == -ERESTARTSYS)
  245. return -EINTR;
  246. switch (link->wr_reg_state) {
  247. case CONFIRMED:
  248. rc = 0;
  249. break;
  250. case FAILED:
  251. rc = -EIO;
  252. break;
  253. case POSTED:
  254. rc = -EPIPE;
  255. break;
  256. }
  257. return rc;
  258. }
  259. void smc_wr_tx_dismiss_slots(struct smc_link *link, u8 wr_tx_hdr_type,
  260. smc_wr_tx_filter filter,
  261. smc_wr_tx_dismisser dismisser,
  262. unsigned long data)
  263. {
  264. struct smc_wr_tx_pend_priv *tx_pend;
  265. struct smc_wr_rx_hdr *wr_tx;
  266. int i;
  267. for_each_set_bit(i, link->wr_tx_mask, link->wr_tx_cnt) {
  268. wr_tx = (struct smc_wr_rx_hdr *)&link->wr_tx_bufs[i];
  269. if (wr_tx->type != wr_tx_hdr_type)
  270. continue;
  271. tx_pend = &link->wr_tx_pends[i].priv;
  272. if (filter(tx_pend, data))
  273. dismisser(tx_pend);
  274. }
  275. }
  276. /****************************** receive queue ********************************/
  277. int smc_wr_rx_register_handler(struct smc_wr_rx_handler *handler)
  278. {
  279. struct smc_wr_rx_handler *h_iter;
  280. int rc = 0;
  281. spin_lock(&smc_wr_rx_hash_lock);
  282. hash_for_each_possible(smc_wr_rx_hash, h_iter, list, handler->type) {
  283. if (h_iter->type == handler->type) {
  284. rc = -EEXIST;
  285. goto out_unlock;
  286. }
  287. }
  288. hash_add(smc_wr_rx_hash, &handler->list, handler->type);
  289. out_unlock:
  290. spin_unlock(&smc_wr_rx_hash_lock);
  291. return rc;
  292. }
  293. /* Demultiplex a received work request based on the message type to its handler.
  294. * Relies on smc_wr_rx_hash having been completely filled before any IB WRs,
  295. * and not being modified any more afterwards so we don't need to lock it.
  296. */
  297. static inline void smc_wr_rx_demultiplex(struct ib_wc *wc)
  298. {
  299. struct smc_link *link = (struct smc_link *)wc->qp->qp_context;
  300. struct smc_wr_rx_handler *handler;
  301. struct smc_wr_rx_hdr *wr_rx;
  302. u64 temp_wr_id;
  303. u32 index;
  304. if (wc->byte_len < sizeof(*wr_rx))
  305. return; /* short message */
  306. temp_wr_id = wc->wr_id;
  307. index = do_div(temp_wr_id, link->wr_rx_cnt);
  308. wr_rx = (struct smc_wr_rx_hdr *)&link->wr_rx_bufs[index];
  309. hash_for_each_possible(smc_wr_rx_hash, handler, list, wr_rx->type) {
  310. if (handler->type == wr_rx->type)
  311. handler->handler(wc, wr_rx);
  312. }
  313. }
  314. static inline void smc_wr_rx_process_cqes(struct ib_wc wc[], int num)
  315. {
  316. struct smc_link *link;
  317. int i;
  318. for (i = 0; i < num; i++) {
  319. link = wc[i].qp->qp_context;
  320. if (wc[i].status == IB_WC_SUCCESS) {
  321. link->wr_rx_tstamp = jiffies;
  322. smc_wr_rx_demultiplex(&wc[i]);
  323. smc_wr_rx_post(link); /* refill WR RX */
  324. } else {
  325. /* handle status errors */
  326. switch (wc[i].status) {
  327. case IB_WC_RETRY_EXC_ERR:
  328. case IB_WC_RNR_RETRY_EXC_ERR:
  329. case IB_WC_WR_FLUSH_ERR:
  330. /* terminate connections of this link group
  331. * abnormally
  332. */
  333. smc_lgr_terminate(smc_get_lgr(link));
  334. break;
  335. default:
  336. smc_wr_rx_post(link); /* refill WR RX */
  337. break;
  338. }
  339. }
  340. }
  341. }
  342. static void smc_wr_rx_tasklet_fn(unsigned long data)
  343. {
  344. struct smc_ib_device *dev = (struct smc_ib_device *)data;
  345. struct ib_wc wc[SMC_WR_MAX_POLL_CQE];
  346. int polled = 0;
  347. int rc;
  348. again:
  349. polled++;
  350. do {
  351. memset(&wc, 0, sizeof(wc));
  352. rc = ib_poll_cq(dev->roce_cq_recv, SMC_WR_MAX_POLL_CQE, wc);
  353. if (polled == 1) {
  354. ib_req_notify_cq(dev->roce_cq_recv,
  355. IB_CQ_SOLICITED_MASK
  356. | IB_CQ_REPORT_MISSED_EVENTS);
  357. }
  358. if (!rc)
  359. break;
  360. smc_wr_rx_process_cqes(&wc[0], rc);
  361. } while (rc > 0);
  362. if (polled == 1)
  363. goto again;
  364. }
  365. void smc_wr_rx_cq_handler(struct ib_cq *ib_cq, void *cq_context)
  366. {
  367. struct smc_ib_device *dev = (struct smc_ib_device *)cq_context;
  368. tasklet_schedule(&dev->recv_tasklet);
  369. }
  370. int smc_wr_rx_post_init(struct smc_link *link)
  371. {
  372. u32 i;
  373. int rc = 0;
  374. for (i = 0; i < link->wr_rx_cnt; i++)
  375. rc = smc_wr_rx_post(link);
  376. return rc;
  377. }
  378. /***************************** init, exit, misc ******************************/
  379. void smc_wr_remember_qp_attr(struct smc_link *lnk)
  380. {
  381. struct ib_qp_attr *attr = &lnk->qp_attr;
  382. struct ib_qp_init_attr init_attr;
  383. memset(attr, 0, sizeof(*attr));
  384. memset(&init_attr, 0, sizeof(init_attr));
  385. ib_query_qp(lnk->roce_qp, attr,
  386. IB_QP_STATE |
  387. IB_QP_CUR_STATE |
  388. IB_QP_PKEY_INDEX |
  389. IB_QP_PORT |
  390. IB_QP_QKEY |
  391. IB_QP_AV |
  392. IB_QP_PATH_MTU |
  393. IB_QP_TIMEOUT |
  394. IB_QP_RETRY_CNT |
  395. IB_QP_RNR_RETRY |
  396. IB_QP_RQ_PSN |
  397. IB_QP_ALT_PATH |
  398. IB_QP_MIN_RNR_TIMER |
  399. IB_QP_SQ_PSN |
  400. IB_QP_PATH_MIG_STATE |
  401. IB_QP_CAP |
  402. IB_QP_DEST_QPN,
  403. &init_attr);
  404. lnk->wr_tx_cnt = min_t(size_t, SMC_WR_BUF_CNT,
  405. lnk->qp_attr.cap.max_send_wr);
  406. lnk->wr_rx_cnt = min_t(size_t, SMC_WR_BUF_CNT * 3,
  407. lnk->qp_attr.cap.max_recv_wr);
  408. }
  409. static void smc_wr_init_sge(struct smc_link *lnk)
  410. {
  411. u32 i;
  412. for (i = 0; i < lnk->wr_tx_cnt; i++) {
  413. lnk->wr_tx_sges[i].addr =
  414. lnk->wr_tx_dma_addr + i * SMC_WR_BUF_SIZE;
  415. lnk->wr_tx_sges[i].length = SMC_WR_TX_SIZE;
  416. lnk->wr_tx_sges[i].lkey = lnk->roce_pd->local_dma_lkey;
  417. lnk->wr_tx_ibs[i].next = NULL;
  418. lnk->wr_tx_ibs[i].sg_list = &lnk->wr_tx_sges[i];
  419. lnk->wr_tx_ibs[i].num_sge = 1;
  420. lnk->wr_tx_ibs[i].opcode = IB_WR_SEND;
  421. lnk->wr_tx_ibs[i].send_flags =
  422. IB_SEND_SIGNALED | IB_SEND_SOLICITED;
  423. }
  424. for (i = 0; i < lnk->wr_rx_cnt; i++) {
  425. lnk->wr_rx_sges[i].addr =
  426. lnk->wr_rx_dma_addr + i * SMC_WR_BUF_SIZE;
  427. lnk->wr_rx_sges[i].length = SMC_WR_BUF_SIZE;
  428. lnk->wr_rx_sges[i].lkey = lnk->roce_pd->local_dma_lkey;
  429. lnk->wr_rx_ibs[i].next = NULL;
  430. lnk->wr_rx_ibs[i].sg_list = &lnk->wr_rx_sges[i];
  431. lnk->wr_rx_ibs[i].num_sge = 1;
  432. }
  433. lnk->wr_reg.wr.next = NULL;
  434. lnk->wr_reg.wr.num_sge = 0;
  435. lnk->wr_reg.wr.send_flags = IB_SEND_SIGNALED;
  436. lnk->wr_reg.wr.opcode = IB_WR_REG_MR;
  437. lnk->wr_reg.access = IB_ACCESS_LOCAL_WRITE | IB_ACCESS_REMOTE_WRITE;
  438. }
  439. void smc_wr_free_link(struct smc_link *lnk)
  440. {
  441. struct ib_device *ibdev;
  442. memset(lnk->wr_tx_mask, 0,
  443. BITS_TO_LONGS(SMC_WR_BUF_CNT) * sizeof(*lnk->wr_tx_mask));
  444. if (!lnk->smcibdev)
  445. return;
  446. ibdev = lnk->smcibdev->ibdev;
  447. if (lnk->wr_rx_dma_addr) {
  448. ib_dma_unmap_single(ibdev, lnk->wr_rx_dma_addr,
  449. SMC_WR_BUF_SIZE * lnk->wr_rx_cnt,
  450. DMA_FROM_DEVICE);
  451. lnk->wr_rx_dma_addr = 0;
  452. }
  453. if (lnk->wr_tx_dma_addr) {
  454. ib_dma_unmap_single(ibdev, lnk->wr_tx_dma_addr,
  455. SMC_WR_BUF_SIZE * lnk->wr_tx_cnt,
  456. DMA_TO_DEVICE);
  457. lnk->wr_tx_dma_addr = 0;
  458. }
  459. }
  460. void smc_wr_free_link_mem(struct smc_link *lnk)
  461. {
  462. kfree(lnk->wr_tx_pends);
  463. lnk->wr_tx_pends = NULL;
  464. kfree(lnk->wr_tx_mask);
  465. lnk->wr_tx_mask = NULL;
  466. kfree(lnk->wr_tx_sges);
  467. lnk->wr_tx_sges = NULL;
  468. kfree(lnk->wr_rx_sges);
  469. lnk->wr_rx_sges = NULL;
  470. kfree(lnk->wr_rx_ibs);
  471. lnk->wr_rx_ibs = NULL;
  472. kfree(lnk->wr_tx_ibs);
  473. lnk->wr_tx_ibs = NULL;
  474. kfree(lnk->wr_tx_bufs);
  475. lnk->wr_tx_bufs = NULL;
  476. kfree(lnk->wr_rx_bufs);
  477. lnk->wr_rx_bufs = NULL;
  478. }
  479. int smc_wr_alloc_link_mem(struct smc_link *link)
  480. {
  481. /* allocate link related memory */
  482. link->wr_tx_bufs = kcalloc(SMC_WR_BUF_CNT, SMC_WR_BUF_SIZE, GFP_KERNEL);
  483. if (!link->wr_tx_bufs)
  484. goto no_mem;
  485. link->wr_rx_bufs = kcalloc(SMC_WR_BUF_CNT * 3, SMC_WR_BUF_SIZE,
  486. GFP_KERNEL);
  487. if (!link->wr_rx_bufs)
  488. goto no_mem_wr_tx_bufs;
  489. link->wr_tx_ibs = kcalloc(SMC_WR_BUF_CNT, sizeof(link->wr_tx_ibs[0]),
  490. GFP_KERNEL);
  491. if (!link->wr_tx_ibs)
  492. goto no_mem_wr_rx_bufs;
  493. link->wr_rx_ibs = kcalloc(SMC_WR_BUF_CNT * 3,
  494. sizeof(link->wr_rx_ibs[0]),
  495. GFP_KERNEL);
  496. if (!link->wr_rx_ibs)
  497. goto no_mem_wr_tx_ibs;
  498. link->wr_tx_sges = kcalloc(SMC_WR_BUF_CNT, sizeof(link->wr_tx_sges[0]),
  499. GFP_KERNEL);
  500. if (!link->wr_tx_sges)
  501. goto no_mem_wr_rx_ibs;
  502. link->wr_rx_sges = kcalloc(SMC_WR_BUF_CNT * 3,
  503. sizeof(link->wr_rx_sges[0]),
  504. GFP_KERNEL);
  505. if (!link->wr_rx_sges)
  506. goto no_mem_wr_tx_sges;
  507. link->wr_tx_mask = kcalloc(BITS_TO_LONGS(SMC_WR_BUF_CNT),
  508. sizeof(*link->wr_tx_mask),
  509. GFP_KERNEL);
  510. if (!link->wr_tx_mask)
  511. goto no_mem_wr_rx_sges;
  512. link->wr_tx_pends = kcalloc(SMC_WR_BUF_CNT,
  513. sizeof(link->wr_tx_pends[0]),
  514. GFP_KERNEL);
  515. if (!link->wr_tx_pends)
  516. goto no_mem_wr_tx_mask;
  517. return 0;
  518. no_mem_wr_tx_mask:
  519. kfree(link->wr_tx_mask);
  520. no_mem_wr_rx_sges:
  521. kfree(link->wr_rx_sges);
  522. no_mem_wr_tx_sges:
  523. kfree(link->wr_tx_sges);
  524. no_mem_wr_rx_ibs:
  525. kfree(link->wr_rx_ibs);
  526. no_mem_wr_tx_ibs:
  527. kfree(link->wr_tx_ibs);
  528. no_mem_wr_rx_bufs:
  529. kfree(link->wr_rx_bufs);
  530. no_mem_wr_tx_bufs:
  531. kfree(link->wr_tx_bufs);
  532. no_mem:
  533. return -ENOMEM;
  534. }
  535. void smc_wr_remove_dev(struct smc_ib_device *smcibdev)
  536. {
  537. tasklet_kill(&smcibdev->recv_tasklet);
  538. tasklet_kill(&smcibdev->send_tasklet);
  539. }
  540. void smc_wr_add_dev(struct smc_ib_device *smcibdev)
  541. {
  542. tasklet_init(&smcibdev->recv_tasklet, smc_wr_rx_tasklet_fn,
  543. (unsigned long)smcibdev);
  544. tasklet_init(&smcibdev->send_tasklet, smc_wr_tx_tasklet_fn,
  545. (unsigned long)smcibdev);
  546. }
  547. int smc_wr_create_link(struct smc_link *lnk)
  548. {
  549. struct ib_device *ibdev = lnk->smcibdev->ibdev;
  550. int rc = 0;
  551. smc_wr_tx_set_wr_id(&lnk->wr_tx_id, 0);
  552. lnk->wr_rx_id = 0;
  553. lnk->wr_rx_dma_addr = ib_dma_map_single(
  554. ibdev, lnk->wr_rx_bufs, SMC_WR_BUF_SIZE * lnk->wr_rx_cnt,
  555. DMA_FROM_DEVICE);
  556. if (ib_dma_mapping_error(ibdev, lnk->wr_rx_dma_addr)) {
  557. lnk->wr_rx_dma_addr = 0;
  558. rc = -EIO;
  559. goto out;
  560. }
  561. lnk->wr_tx_dma_addr = ib_dma_map_single(
  562. ibdev, lnk->wr_tx_bufs, SMC_WR_BUF_SIZE * lnk->wr_tx_cnt,
  563. DMA_TO_DEVICE);
  564. if (ib_dma_mapping_error(ibdev, lnk->wr_tx_dma_addr)) {
  565. rc = -EIO;
  566. goto dma_unmap;
  567. }
  568. smc_wr_init_sge(lnk);
  569. memset(lnk->wr_tx_mask, 0,
  570. BITS_TO_LONGS(SMC_WR_BUF_CNT) * sizeof(*lnk->wr_tx_mask));
  571. init_waitqueue_head(&lnk->wr_tx_wait);
  572. init_waitqueue_head(&lnk->wr_reg_wait);
  573. return rc;
  574. dma_unmap:
  575. ib_dma_unmap_single(ibdev, lnk->wr_rx_dma_addr,
  576. SMC_WR_BUF_SIZE * lnk->wr_rx_cnt,
  577. DMA_FROM_DEVICE);
  578. lnk->wr_rx_dma_addr = 0;
  579. out:
  580. return rc;
  581. }