debugfs.c 7.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275
  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright 2017 Thomas Gleixner <tglx@linutronix.de>
  3. #include <linux/irqdomain.h>
  4. #include <linux/irq.h>
  5. #include <linux/uaccess.h>
  6. #include "internals.h"
  7. static struct dentry *irq_dir;
  8. struct irq_bit_descr {
  9. unsigned int mask;
  10. char *name;
  11. };
  12. #define BIT_MASK_DESCR(m) { .mask = m, .name = #m }
  13. static void irq_debug_show_bits(struct seq_file *m, int ind, unsigned int state,
  14. const struct irq_bit_descr *sd, int size)
  15. {
  16. int i;
  17. for (i = 0; i < size; i++, sd++) {
  18. if (state & sd->mask)
  19. seq_printf(m, "%*s%s\n", ind + 12, "", sd->name);
  20. }
  21. }
  22. #ifdef CONFIG_SMP
  23. static void irq_debug_show_masks(struct seq_file *m, struct irq_desc *desc)
  24. {
  25. struct irq_data *data = irq_desc_get_irq_data(desc);
  26. struct cpumask *msk;
  27. msk = irq_data_get_affinity_mask(data);
  28. seq_printf(m, "affinity: %*pbl\n", cpumask_pr_args(msk));
  29. #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
  30. msk = irq_data_get_effective_affinity_mask(data);
  31. seq_printf(m, "effectiv: %*pbl\n", cpumask_pr_args(msk));
  32. #endif
  33. #ifdef CONFIG_GENERIC_PENDING_IRQ
  34. msk = desc->pending_mask;
  35. seq_printf(m, "pending: %*pbl\n", cpumask_pr_args(msk));
  36. #endif
  37. }
  38. #else
  39. static void irq_debug_show_masks(struct seq_file *m, struct irq_desc *desc) { }
  40. #endif
  41. static const struct irq_bit_descr irqchip_flags[] = {
  42. BIT_MASK_DESCR(IRQCHIP_SET_TYPE_MASKED),
  43. BIT_MASK_DESCR(IRQCHIP_EOI_IF_HANDLED),
  44. BIT_MASK_DESCR(IRQCHIP_MASK_ON_SUSPEND),
  45. BIT_MASK_DESCR(IRQCHIP_ONOFFLINE_ENABLED),
  46. BIT_MASK_DESCR(IRQCHIP_SKIP_SET_WAKE),
  47. BIT_MASK_DESCR(IRQCHIP_ONESHOT_SAFE),
  48. BIT_MASK_DESCR(IRQCHIP_EOI_THREADED),
  49. BIT_MASK_DESCR(IRQCHIP_SUPPORTS_LEVEL_MSI),
  50. };
  51. static void
  52. irq_debug_show_chip(struct seq_file *m, struct irq_data *data, int ind)
  53. {
  54. struct irq_chip *chip = data->chip;
  55. if (!chip) {
  56. seq_printf(m, "chip: None\n");
  57. return;
  58. }
  59. seq_printf(m, "%*schip: %s\n", ind, "", chip->name);
  60. seq_printf(m, "%*sflags: 0x%lx\n", ind + 1, "", chip->flags);
  61. irq_debug_show_bits(m, ind, chip->flags, irqchip_flags,
  62. ARRAY_SIZE(irqchip_flags));
  63. }
  64. static void
  65. irq_debug_show_data(struct seq_file *m, struct irq_data *data, int ind)
  66. {
  67. seq_printf(m, "%*sdomain: %s\n", ind, "",
  68. data->domain ? data->domain->name : "");
  69. seq_printf(m, "%*shwirq: 0x%lx\n", ind + 1, "", data->hwirq);
  70. irq_debug_show_chip(m, data, ind + 1);
  71. if (data->domain && data->domain->ops && data->domain->ops->debug_show)
  72. data->domain->ops->debug_show(m, NULL, data, ind + 1);
  73. #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
  74. if (!data->parent_data)
  75. return;
  76. seq_printf(m, "%*sparent:\n", ind + 1, "");
  77. irq_debug_show_data(m, data->parent_data, ind + 4);
  78. #endif
  79. }
  80. static const struct irq_bit_descr irqdata_states[] = {
  81. BIT_MASK_DESCR(IRQ_TYPE_EDGE_RISING),
  82. BIT_MASK_DESCR(IRQ_TYPE_EDGE_FALLING),
  83. BIT_MASK_DESCR(IRQ_TYPE_LEVEL_HIGH),
  84. BIT_MASK_DESCR(IRQ_TYPE_LEVEL_LOW),
  85. BIT_MASK_DESCR(IRQD_LEVEL),
  86. BIT_MASK_DESCR(IRQD_ACTIVATED),
  87. BIT_MASK_DESCR(IRQD_IRQ_STARTED),
  88. BIT_MASK_DESCR(IRQD_IRQ_DISABLED),
  89. BIT_MASK_DESCR(IRQD_IRQ_MASKED),
  90. BIT_MASK_DESCR(IRQD_IRQ_INPROGRESS),
  91. BIT_MASK_DESCR(IRQD_PER_CPU),
  92. BIT_MASK_DESCR(IRQD_NO_BALANCING),
  93. BIT_MASK_DESCR(IRQD_SINGLE_TARGET),
  94. BIT_MASK_DESCR(IRQD_MOVE_PCNTXT),
  95. BIT_MASK_DESCR(IRQD_AFFINITY_SET),
  96. BIT_MASK_DESCR(IRQD_SETAFFINITY_PENDING),
  97. BIT_MASK_DESCR(IRQD_AFFINITY_MANAGED),
  98. BIT_MASK_DESCR(IRQD_MANAGED_SHUTDOWN),
  99. BIT_MASK_DESCR(IRQD_CAN_RESERVE),
  100. BIT_MASK_DESCR(IRQD_MSI_NOMASK_QUIRK),
  101. BIT_MASK_DESCR(IRQD_FORWARDED_TO_VCPU),
  102. BIT_MASK_DESCR(IRQD_WAKEUP_STATE),
  103. BIT_MASK_DESCR(IRQD_WAKEUP_ARMED),
  104. };
  105. static const struct irq_bit_descr irqdesc_states[] = {
  106. BIT_MASK_DESCR(_IRQ_NOPROBE),
  107. BIT_MASK_DESCR(_IRQ_NOREQUEST),
  108. BIT_MASK_DESCR(_IRQ_NOTHREAD),
  109. BIT_MASK_DESCR(_IRQ_NOAUTOEN),
  110. BIT_MASK_DESCR(_IRQ_NESTED_THREAD),
  111. BIT_MASK_DESCR(_IRQ_PER_CPU_DEVID),
  112. BIT_MASK_DESCR(_IRQ_IS_POLLED),
  113. BIT_MASK_DESCR(_IRQ_DISABLE_UNLAZY),
  114. };
  115. static const struct irq_bit_descr irqdesc_istates[] = {
  116. BIT_MASK_DESCR(IRQS_AUTODETECT),
  117. BIT_MASK_DESCR(IRQS_SPURIOUS_DISABLED),
  118. BIT_MASK_DESCR(IRQS_POLL_INPROGRESS),
  119. BIT_MASK_DESCR(IRQS_ONESHOT),
  120. BIT_MASK_DESCR(IRQS_REPLAY),
  121. BIT_MASK_DESCR(IRQS_WAITING),
  122. BIT_MASK_DESCR(IRQS_PENDING),
  123. BIT_MASK_DESCR(IRQS_SUSPENDED),
  124. };
  125. static int irq_debug_show(struct seq_file *m, void *p)
  126. {
  127. struct irq_desc *desc = m->private;
  128. struct irq_data *data;
  129. raw_spin_lock_irq(&desc->lock);
  130. data = irq_desc_get_irq_data(desc);
  131. seq_printf(m, "handler: %pf\n", desc->handle_irq);
  132. seq_printf(m, "device: %s\n", desc->dev_name);
  133. seq_printf(m, "status: 0x%08x\n", desc->status_use_accessors);
  134. irq_debug_show_bits(m, 0, desc->status_use_accessors, irqdesc_states,
  135. ARRAY_SIZE(irqdesc_states));
  136. seq_printf(m, "istate: 0x%08x\n", desc->istate);
  137. irq_debug_show_bits(m, 0, desc->istate, irqdesc_istates,
  138. ARRAY_SIZE(irqdesc_istates));
  139. seq_printf(m, "ddepth: %u\n", desc->depth);
  140. seq_printf(m, "wdepth: %u\n", desc->wake_depth);
  141. seq_printf(m, "dstate: 0x%08x\n", irqd_get(data));
  142. irq_debug_show_bits(m, 0, irqd_get(data), irqdata_states,
  143. ARRAY_SIZE(irqdata_states));
  144. seq_printf(m, "node: %d\n", irq_data_get_node(data));
  145. irq_debug_show_masks(m, desc);
  146. irq_debug_show_data(m, data, 0);
  147. raw_spin_unlock_irq(&desc->lock);
  148. return 0;
  149. }
  150. static int irq_debug_open(struct inode *inode, struct file *file)
  151. {
  152. return single_open(file, irq_debug_show, inode->i_private);
  153. }
  154. static ssize_t irq_debug_write(struct file *file, const char __user *user_buf,
  155. size_t count, loff_t *ppos)
  156. {
  157. struct irq_desc *desc = file_inode(file)->i_private;
  158. char buf[8] = { 0, };
  159. size_t size;
  160. size = min(sizeof(buf) - 1, count);
  161. if (copy_from_user(buf, user_buf, size))
  162. return -EFAULT;
  163. if (!strncmp(buf, "trigger", size)) {
  164. unsigned long flags;
  165. int err;
  166. /* Try the HW interface first */
  167. err = irq_set_irqchip_state(irq_desc_get_irq(desc),
  168. IRQCHIP_STATE_PENDING, true);
  169. if (!err)
  170. return count;
  171. /*
  172. * Otherwise, try to inject via the resend interface,
  173. * which may or may not succeed.
  174. */
  175. chip_bus_lock(desc);
  176. raw_spin_lock_irqsave(&desc->lock, flags);
  177. if (irq_settings_is_level(desc)) {
  178. /* Can't do level, sorry */
  179. err = -EINVAL;
  180. } else {
  181. desc->istate |= IRQS_PENDING;
  182. check_irq_resend(desc);
  183. err = 0;
  184. }
  185. raw_spin_unlock_irqrestore(&desc->lock, flags);
  186. chip_bus_sync_unlock(desc);
  187. return err ? err : count;
  188. }
  189. return count;
  190. }
  191. static const struct file_operations dfs_irq_ops = {
  192. .open = irq_debug_open,
  193. .write = irq_debug_write,
  194. .read = seq_read,
  195. .llseek = seq_lseek,
  196. .release = single_release,
  197. };
  198. void irq_debugfs_copy_devname(int irq, struct device *dev)
  199. {
  200. struct irq_desc *desc = irq_to_desc(irq);
  201. const char *name = dev_name(dev);
  202. if (name)
  203. desc->dev_name = kstrdup(name, GFP_KERNEL);
  204. }
  205. void irq_add_debugfs_entry(unsigned int irq, struct irq_desc *desc)
  206. {
  207. char name [10];
  208. if (!irq_dir || !desc || desc->debugfs_file)
  209. return;
  210. sprintf(name, "%d", irq);
  211. desc->debugfs_file = debugfs_create_file(name, 0644, irq_dir, desc,
  212. &dfs_irq_ops);
  213. }
  214. static int __init irq_debugfs_init(void)
  215. {
  216. struct dentry *root_dir;
  217. int irq;
  218. root_dir = debugfs_create_dir("irq", NULL);
  219. if (!root_dir)
  220. return -ENOMEM;
  221. irq_domain_debugfs_init(root_dir);
  222. irq_dir = debugfs_create_dir("irqs", root_dir);
  223. irq_lock_sparse();
  224. for_each_active_irq(irq)
  225. irq_add_debugfs_entry(irq, irq_to_desc(irq));
  226. irq_unlock_sparse();
  227. return 0;
  228. }
  229. __initcall(irq_debugfs_init);