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- /*
- * Copyright (C) 2015 Renesas Electronics Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
- #ifndef __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__
- #define __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__
- #include <dt-bindings/clock/renesas-cpg-mssr.h>
- /* r8a7794 CPG Core Clocks */
- #define R8A7794_CLK_Z2 0
- #define R8A7794_CLK_ZG 1
- #define R8A7794_CLK_ZTR 2
- #define R8A7794_CLK_ZTRD2 3
- #define R8A7794_CLK_ZT 4
- #define R8A7794_CLK_ZX 5
- #define R8A7794_CLK_ZS 6
- #define R8A7794_CLK_HP 7
- #define R8A7794_CLK_I 8
- #define R8A7794_CLK_B 9
- #define R8A7794_CLK_LB 10
- #define R8A7794_CLK_P 11
- #define R8A7794_CLK_CL 12
- #define R8A7794_CLK_CP 13
- #define R8A7794_CLK_M2 14
- #define R8A7794_CLK_ADSP 15
- #define R8A7794_CLK_ZB3 16
- #define R8A7794_CLK_ZB3D2 17
- #define R8A7794_CLK_DDR 18
- #define R8A7794_CLK_SDH 19
- #define R8A7794_CLK_SD0 20
- #define R8A7794_CLK_SD2 21
- #define R8A7794_CLK_SD3 22
- #define R8A7794_CLK_MMC0 23
- #define R8A7794_CLK_MP 24
- #define R8A7794_CLK_QSPI 25
- #define R8A7794_CLK_CPEX 26
- #define R8A7794_CLK_RCAN 27
- #define R8A7794_CLK_R 28
- #define R8A7794_CLK_OSC 29
- #endif /* __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ */
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