qcom,gcc-msm8916.h 6.0 KB

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  1. /*
  2. * Copyright 2015 Linaro Limited
  3. *
  4. * This software is licensed under the terms of the GNU General Public
  5. * License version 2, as published by the Free Software Foundation, and
  6. * may be copied, distributed, and modified under those terms.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #ifndef _DT_BINDINGS_CLK_MSM_GCC_8916_H
  14. #define _DT_BINDINGS_CLK_MSM_GCC_8916_H
  15. #define GPLL0 0
  16. #define GPLL0_VOTE 1
  17. #define BIMC_PLL 2
  18. #define BIMC_PLL_VOTE 3
  19. #define GPLL1 4
  20. #define GPLL1_VOTE 5
  21. #define GPLL2 6
  22. #define GPLL2_VOTE 7
  23. #define PCNOC_BFDCD_CLK_SRC 8
  24. #define SYSTEM_NOC_BFDCD_CLK_SRC 9
  25. #define CAMSS_AHB_CLK_SRC 10
  26. #define APSS_AHB_CLK_SRC 11
  27. #define CSI0_CLK_SRC 12
  28. #define CSI1_CLK_SRC 13
  29. #define GFX3D_CLK_SRC 14
  30. #define VFE0_CLK_SRC 15
  31. #define BLSP1_QUP1_I2C_APPS_CLK_SRC 16
  32. #define BLSP1_QUP1_SPI_APPS_CLK_SRC 17
  33. #define BLSP1_QUP2_I2C_APPS_CLK_SRC 18
  34. #define BLSP1_QUP2_SPI_APPS_CLK_SRC 19
  35. #define BLSP1_QUP3_I2C_APPS_CLK_SRC 20
  36. #define BLSP1_QUP3_SPI_APPS_CLK_SRC 21
  37. #define BLSP1_QUP4_I2C_APPS_CLK_SRC 22
  38. #define BLSP1_QUP4_SPI_APPS_CLK_SRC 23
  39. #define BLSP1_QUP5_I2C_APPS_CLK_SRC 24
  40. #define BLSP1_QUP5_SPI_APPS_CLK_SRC 25
  41. #define BLSP1_QUP6_I2C_APPS_CLK_SRC 26
  42. #define BLSP1_QUP6_SPI_APPS_CLK_SRC 27
  43. #define BLSP1_UART1_APPS_CLK_SRC 28
  44. #define BLSP1_UART2_APPS_CLK_SRC 29
  45. #define CCI_CLK_SRC 30
  46. #define CAMSS_GP0_CLK_SRC 31
  47. #define CAMSS_GP1_CLK_SRC 32
  48. #define JPEG0_CLK_SRC 33
  49. #define MCLK0_CLK_SRC 34
  50. #define MCLK1_CLK_SRC 35
  51. #define CSI0PHYTIMER_CLK_SRC 36
  52. #define CSI1PHYTIMER_CLK_SRC 37
  53. #define CPP_CLK_SRC 38
  54. #define CRYPTO_CLK_SRC 39
  55. #define GP1_CLK_SRC 40
  56. #define GP2_CLK_SRC 41
  57. #define GP3_CLK_SRC 42
  58. #define BYTE0_CLK_SRC 43
  59. #define ESC0_CLK_SRC 44
  60. #define MDP_CLK_SRC 45
  61. #define PCLK0_CLK_SRC 46
  62. #define VSYNC_CLK_SRC 47
  63. #define PDM2_CLK_SRC 48
  64. #define SDCC1_APPS_CLK_SRC 49
  65. #define SDCC2_APPS_CLK_SRC 50
  66. #define APSS_TCU_CLK_SRC 51
  67. #define USB_HS_SYSTEM_CLK_SRC 52
  68. #define VCODEC0_CLK_SRC 53
  69. #define GCC_BLSP1_AHB_CLK 54
  70. #define GCC_BLSP1_SLEEP_CLK 55
  71. #define GCC_BLSP1_QUP1_I2C_APPS_CLK 56
  72. #define GCC_BLSP1_QUP1_SPI_APPS_CLK 57
  73. #define GCC_BLSP1_QUP2_I2C_APPS_CLK 58
  74. #define GCC_BLSP1_QUP2_SPI_APPS_CLK 59
  75. #define GCC_BLSP1_QUP3_I2C_APPS_CLK 60
  76. #define GCC_BLSP1_QUP3_SPI_APPS_CLK 61
  77. #define GCC_BLSP1_QUP4_I2C_APPS_CLK 62
  78. #define GCC_BLSP1_QUP4_SPI_APPS_CLK 63
  79. #define GCC_BLSP1_QUP5_I2C_APPS_CLK 64
  80. #define GCC_BLSP1_QUP5_SPI_APPS_CLK 65
  81. #define GCC_BLSP1_QUP6_I2C_APPS_CLK 66
  82. #define GCC_BLSP1_QUP6_SPI_APPS_CLK 67
  83. #define GCC_BLSP1_UART1_APPS_CLK 68
  84. #define GCC_BLSP1_UART2_APPS_CLK 69
  85. #define GCC_BOOT_ROM_AHB_CLK 70
  86. #define GCC_CAMSS_CCI_AHB_CLK 71
  87. #define GCC_CAMSS_CCI_CLK 72
  88. #define GCC_CAMSS_CSI0_AHB_CLK 73
  89. #define GCC_CAMSS_CSI0_CLK 74
  90. #define GCC_CAMSS_CSI0PHY_CLK 75
  91. #define GCC_CAMSS_CSI0PIX_CLK 76
  92. #define GCC_CAMSS_CSI0RDI_CLK 77
  93. #define GCC_CAMSS_CSI1_AHB_CLK 78
  94. #define GCC_CAMSS_CSI1_CLK 79
  95. #define GCC_CAMSS_CSI1PHY_CLK 80
  96. #define GCC_CAMSS_CSI1PIX_CLK 81
  97. #define GCC_CAMSS_CSI1RDI_CLK 82
  98. #define GCC_CAMSS_CSI_VFE0_CLK 83
  99. #define GCC_CAMSS_GP0_CLK 84
  100. #define GCC_CAMSS_GP1_CLK 85
  101. #define GCC_CAMSS_ISPIF_AHB_CLK 86
  102. #define GCC_CAMSS_JPEG0_CLK 87
  103. #define GCC_CAMSS_JPEG_AHB_CLK 88
  104. #define GCC_CAMSS_JPEG_AXI_CLK 89
  105. #define GCC_CAMSS_MCLK0_CLK 90
  106. #define GCC_CAMSS_MCLK1_CLK 91
  107. #define GCC_CAMSS_MICRO_AHB_CLK 92
  108. #define GCC_CAMSS_CSI0PHYTIMER_CLK 93
  109. #define GCC_CAMSS_CSI1PHYTIMER_CLK 94
  110. #define GCC_CAMSS_AHB_CLK 95
  111. #define GCC_CAMSS_TOP_AHB_CLK 96
  112. #define GCC_CAMSS_CPP_AHB_CLK 97
  113. #define GCC_CAMSS_CPP_CLK 98
  114. #define GCC_CAMSS_VFE0_CLK 99
  115. #define GCC_CAMSS_VFE_AHB_CLK 100
  116. #define GCC_CAMSS_VFE_AXI_CLK 101
  117. #define GCC_CRYPTO_AHB_CLK 102
  118. #define GCC_CRYPTO_AXI_CLK 103
  119. #define GCC_CRYPTO_CLK 104
  120. #define GCC_OXILI_GMEM_CLK 105
  121. #define GCC_GP1_CLK 106
  122. #define GCC_GP2_CLK 107
  123. #define GCC_GP3_CLK 108
  124. #define GCC_MDSS_AHB_CLK 109
  125. #define GCC_MDSS_AXI_CLK 110
  126. #define GCC_MDSS_BYTE0_CLK 111
  127. #define GCC_MDSS_ESC0_CLK 112
  128. #define GCC_MDSS_MDP_CLK 113
  129. #define GCC_MDSS_PCLK0_CLK 114
  130. #define GCC_MDSS_VSYNC_CLK 115
  131. #define GCC_MSS_CFG_AHB_CLK 116
  132. #define GCC_OXILI_AHB_CLK 117
  133. #define GCC_OXILI_GFX3D_CLK 118
  134. #define GCC_PDM2_CLK 119
  135. #define GCC_PDM_AHB_CLK 120
  136. #define GCC_PRNG_AHB_CLK 121
  137. #define GCC_SDCC1_AHB_CLK 122
  138. #define GCC_SDCC1_APPS_CLK 123
  139. #define GCC_SDCC2_AHB_CLK 124
  140. #define GCC_SDCC2_APPS_CLK 125
  141. #define GCC_GTCU_AHB_CLK 126
  142. #define GCC_JPEG_TBU_CLK 127
  143. #define GCC_MDP_TBU_CLK 128
  144. #define GCC_SMMU_CFG_CLK 129
  145. #define GCC_VENUS_TBU_CLK 130
  146. #define GCC_VFE_TBU_CLK 131
  147. #define GCC_USB2A_PHY_SLEEP_CLK 132
  148. #define GCC_USB_HS_AHB_CLK 133
  149. #define GCC_USB_HS_SYSTEM_CLK 134
  150. #define GCC_VENUS0_AHB_CLK 135
  151. #define GCC_VENUS0_AXI_CLK 136
  152. #define GCC_VENUS0_VCODEC0_CLK 137
  153. #define BIMC_DDR_CLK_SRC 138
  154. #define GCC_APSS_TCU_CLK 139
  155. #define GCC_GFX_TCU_CLK 140
  156. #define BIMC_GPU_CLK_SRC 141
  157. #define GCC_BIMC_GFX_CLK 142
  158. #define GCC_BIMC_GPU_CLK 143
  159. #define ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC 144
  160. #define ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC 145
  161. #define ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC 146
  162. #define ULTAUDIO_XO_CLK_SRC 147
  163. #define ULTAUDIO_AHBFABRIC_CLK_SRC 148
  164. #define CODEC_DIGCODEC_CLK_SRC 149
  165. #define GCC_ULTAUDIO_PCNOC_MPORT_CLK 150
  166. #define GCC_ULTAUDIO_PCNOC_SWAY_CLK 151
  167. #define GCC_ULTAUDIO_AVSYNC_XO_CLK 152
  168. #define GCC_ULTAUDIO_STC_XO_CLK 153
  169. #define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK 154
  170. #define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK 155
  171. #define GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK 156
  172. #define GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK 157
  173. #define GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK 158
  174. #define GCC_CODEC_DIGCODEC_CLK 159
  175. #define GCC_MSS_Q6_BIMC_AXI_CLK 160
  176. /* Indexes for GDSCs */
  177. #define BIMC_GDSC 0
  178. #define VENUS_GDSC 1
  179. #define MDSS_GDSC 2
  180. #define JPEG_GDSC 3
  181. #define VFE_GDSC 4
  182. #define OXILI_GDSC 5
  183. #endif