r8a66597-udc.c 48 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * R8A66597 UDC (USB gadget)
  4. *
  5. * Copyright (C) 2006-2009 Renesas Solutions Corp.
  6. *
  7. * Author : Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
  8. */
  9. #include <linux/module.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/delay.h>
  12. #include <linux/io.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/clk.h>
  15. #include <linux/err.h>
  16. #include <linux/slab.h>
  17. #include <linux/dma-mapping.h>
  18. #include <linux/usb/ch9.h>
  19. #include <linux/usb/gadget.h>
  20. #include "r8a66597-udc.h"
  21. #define DRIVER_VERSION "2011-09-26"
  22. static const char udc_name[] = "r8a66597_udc";
  23. static const char *r8a66597_ep_name[] = {
  24. "ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7",
  25. "ep8", "ep9",
  26. };
  27. static void init_controller(struct r8a66597 *r8a66597);
  28. static void disable_controller(struct r8a66597 *r8a66597);
  29. static void irq_ep0_write(struct r8a66597_ep *ep, struct r8a66597_request *req);
  30. static void irq_packet_write(struct r8a66597_ep *ep,
  31. struct r8a66597_request *req);
  32. static int r8a66597_queue(struct usb_ep *_ep, struct usb_request *_req,
  33. gfp_t gfp_flags);
  34. static void transfer_complete(struct r8a66597_ep *ep,
  35. struct r8a66597_request *req, int status);
  36. /*-------------------------------------------------------------------------*/
  37. static inline u16 get_usb_speed(struct r8a66597 *r8a66597)
  38. {
  39. return r8a66597_read(r8a66597, DVSTCTR0) & RHST;
  40. }
  41. static void enable_pipe_irq(struct r8a66597 *r8a66597, u16 pipenum,
  42. unsigned long reg)
  43. {
  44. u16 tmp;
  45. tmp = r8a66597_read(r8a66597, INTENB0);
  46. r8a66597_bclr(r8a66597, BEMPE | NRDYE | BRDYE,
  47. INTENB0);
  48. r8a66597_bset(r8a66597, (1 << pipenum), reg);
  49. r8a66597_write(r8a66597, tmp, INTENB0);
  50. }
  51. static void disable_pipe_irq(struct r8a66597 *r8a66597, u16 pipenum,
  52. unsigned long reg)
  53. {
  54. u16 tmp;
  55. tmp = r8a66597_read(r8a66597, INTENB0);
  56. r8a66597_bclr(r8a66597, BEMPE | NRDYE | BRDYE,
  57. INTENB0);
  58. r8a66597_bclr(r8a66597, (1 << pipenum), reg);
  59. r8a66597_write(r8a66597, tmp, INTENB0);
  60. }
  61. static void r8a66597_usb_connect(struct r8a66597 *r8a66597)
  62. {
  63. r8a66597_bset(r8a66597, CTRE, INTENB0);
  64. r8a66597_bset(r8a66597, BEMPE | BRDYE, INTENB0);
  65. r8a66597_bset(r8a66597, DPRPU, SYSCFG0);
  66. }
  67. static void r8a66597_usb_disconnect(struct r8a66597 *r8a66597)
  68. __releases(r8a66597->lock)
  69. __acquires(r8a66597->lock)
  70. {
  71. r8a66597_bclr(r8a66597, CTRE, INTENB0);
  72. r8a66597_bclr(r8a66597, BEMPE | BRDYE, INTENB0);
  73. r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
  74. r8a66597->gadget.speed = USB_SPEED_UNKNOWN;
  75. spin_unlock(&r8a66597->lock);
  76. r8a66597->driver->disconnect(&r8a66597->gadget);
  77. spin_lock(&r8a66597->lock);
  78. disable_controller(r8a66597);
  79. init_controller(r8a66597);
  80. r8a66597_bset(r8a66597, VBSE, INTENB0);
  81. INIT_LIST_HEAD(&r8a66597->ep[0].queue);
  82. }
  83. static inline u16 control_reg_get_pid(struct r8a66597 *r8a66597, u16 pipenum)
  84. {
  85. u16 pid = 0;
  86. unsigned long offset;
  87. if (pipenum == 0) {
  88. pid = r8a66597_read(r8a66597, DCPCTR) & PID;
  89. } else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  90. offset = get_pipectr_addr(pipenum);
  91. pid = r8a66597_read(r8a66597, offset) & PID;
  92. } else {
  93. dev_err(r8a66597_to_dev(r8a66597), "unexpect pipe num (%d)\n",
  94. pipenum);
  95. }
  96. return pid;
  97. }
  98. static inline void control_reg_set_pid(struct r8a66597 *r8a66597, u16 pipenum,
  99. u16 pid)
  100. {
  101. unsigned long offset;
  102. if (pipenum == 0) {
  103. r8a66597_mdfy(r8a66597, pid, PID, DCPCTR);
  104. } else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  105. offset = get_pipectr_addr(pipenum);
  106. r8a66597_mdfy(r8a66597, pid, PID, offset);
  107. } else {
  108. dev_err(r8a66597_to_dev(r8a66597), "unexpect pipe num (%d)\n",
  109. pipenum);
  110. }
  111. }
  112. static inline void pipe_start(struct r8a66597 *r8a66597, u16 pipenum)
  113. {
  114. control_reg_set_pid(r8a66597, pipenum, PID_BUF);
  115. }
  116. static inline void pipe_stop(struct r8a66597 *r8a66597, u16 pipenum)
  117. {
  118. control_reg_set_pid(r8a66597, pipenum, PID_NAK);
  119. }
  120. static inline void pipe_stall(struct r8a66597 *r8a66597, u16 pipenum)
  121. {
  122. control_reg_set_pid(r8a66597, pipenum, PID_STALL);
  123. }
  124. static inline u16 control_reg_get(struct r8a66597 *r8a66597, u16 pipenum)
  125. {
  126. u16 ret = 0;
  127. unsigned long offset;
  128. if (pipenum == 0) {
  129. ret = r8a66597_read(r8a66597, DCPCTR);
  130. } else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  131. offset = get_pipectr_addr(pipenum);
  132. ret = r8a66597_read(r8a66597, offset);
  133. } else {
  134. dev_err(r8a66597_to_dev(r8a66597), "unexpect pipe num (%d)\n",
  135. pipenum);
  136. }
  137. return ret;
  138. }
  139. static inline void control_reg_sqclr(struct r8a66597 *r8a66597, u16 pipenum)
  140. {
  141. unsigned long offset;
  142. pipe_stop(r8a66597, pipenum);
  143. if (pipenum == 0) {
  144. r8a66597_bset(r8a66597, SQCLR, DCPCTR);
  145. } else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  146. offset = get_pipectr_addr(pipenum);
  147. r8a66597_bset(r8a66597, SQCLR, offset);
  148. } else {
  149. dev_err(r8a66597_to_dev(r8a66597), "unexpect pipe num (%d)\n",
  150. pipenum);
  151. }
  152. }
  153. static void control_reg_sqset(struct r8a66597 *r8a66597, u16 pipenum)
  154. {
  155. unsigned long offset;
  156. pipe_stop(r8a66597, pipenum);
  157. if (pipenum == 0) {
  158. r8a66597_bset(r8a66597, SQSET, DCPCTR);
  159. } else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  160. offset = get_pipectr_addr(pipenum);
  161. r8a66597_bset(r8a66597, SQSET, offset);
  162. } else {
  163. dev_err(r8a66597_to_dev(r8a66597),
  164. "unexpect pipe num(%d)\n", pipenum);
  165. }
  166. }
  167. static u16 control_reg_sqmon(struct r8a66597 *r8a66597, u16 pipenum)
  168. {
  169. unsigned long offset;
  170. if (pipenum == 0) {
  171. return r8a66597_read(r8a66597, DCPCTR) & SQMON;
  172. } else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  173. offset = get_pipectr_addr(pipenum);
  174. return r8a66597_read(r8a66597, offset) & SQMON;
  175. } else {
  176. dev_err(r8a66597_to_dev(r8a66597),
  177. "unexpect pipe num(%d)\n", pipenum);
  178. }
  179. return 0;
  180. }
  181. static u16 save_usb_toggle(struct r8a66597 *r8a66597, u16 pipenum)
  182. {
  183. return control_reg_sqmon(r8a66597, pipenum);
  184. }
  185. static void restore_usb_toggle(struct r8a66597 *r8a66597, u16 pipenum,
  186. u16 toggle)
  187. {
  188. if (toggle)
  189. control_reg_sqset(r8a66597, pipenum);
  190. else
  191. control_reg_sqclr(r8a66597, pipenum);
  192. }
  193. static inline int get_buffer_size(struct r8a66597 *r8a66597, u16 pipenum)
  194. {
  195. u16 tmp;
  196. int size;
  197. if (pipenum == 0) {
  198. tmp = r8a66597_read(r8a66597, DCPCFG);
  199. if ((tmp & R8A66597_CNTMD) != 0)
  200. size = 256;
  201. else {
  202. tmp = r8a66597_read(r8a66597, DCPMAXP);
  203. size = tmp & MAXP;
  204. }
  205. } else {
  206. r8a66597_write(r8a66597, pipenum, PIPESEL);
  207. tmp = r8a66597_read(r8a66597, PIPECFG);
  208. if ((tmp & R8A66597_CNTMD) != 0) {
  209. tmp = r8a66597_read(r8a66597, PIPEBUF);
  210. size = ((tmp >> 10) + 1) * 64;
  211. } else {
  212. tmp = r8a66597_read(r8a66597, PIPEMAXP);
  213. size = tmp & MXPS;
  214. }
  215. }
  216. return size;
  217. }
  218. static inline unsigned short mbw_value(struct r8a66597 *r8a66597)
  219. {
  220. if (r8a66597->pdata->on_chip)
  221. return MBW_32;
  222. else
  223. return MBW_16;
  224. }
  225. static void r8a66597_change_curpipe(struct r8a66597 *r8a66597, u16 pipenum,
  226. u16 isel, u16 fifosel)
  227. {
  228. u16 tmp, mask, loop;
  229. int i = 0;
  230. if (!pipenum) {
  231. mask = ISEL | CURPIPE;
  232. loop = isel;
  233. } else {
  234. mask = CURPIPE;
  235. loop = pipenum;
  236. }
  237. r8a66597_mdfy(r8a66597, loop, mask, fifosel);
  238. do {
  239. tmp = r8a66597_read(r8a66597, fifosel);
  240. if (i++ > 1000000) {
  241. dev_err(r8a66597_to_dev(r8a66597),
  242. "r8a66597: register%x, loop %x "
  243. "is timeout\n", fifosel, loop);
  244. break;
  245. }
  246. ndelay(1);
  247. } while ((tmp & mask) != loop);
  248. }
  249. static void pipe_change(struct r8a66597 *r8a66597, u16 pipenum)
  250. {
  251. struct r8a66597_ep *ep = r8a66597->pipenum2ep[pipenum];
  252. if (ep->use_dma)
  253. r8a66597_bclr(r8a66597, DREQE, ep->fifosel);
  254. r8a66597_mdfy(r8a66597, pipenum, CURPIPE, ep->fifosel);
  255. ndelay(450);
  256. if (r8a66597_is_sudmac(r8a66597) && ep->use_dma)
  257. r8a66597_bclr(r8a66597, mbw_value(r8a66597), ep->fifosel);
  258. else
  259. r8a66597_bset(r8a66597, mbw_value(r8a66597), ep->fifosel);
  260. if (ep->use_dma)
  261. r8a66597_bset(r8a66597, DREQE, ep->fifosel);
  262. }
  263. static int pipe_buffer_setting(struct r8a66597 *r8a66597,
  264. struct r8a66597_pipe_info *info)
  265. {
  266. u16 bufnum = 0, buf_bsize = 0;
  267. u16 pipecfg = 0;
  268. if (info->pipe == 0)
  269. return -EINVAL;
  270. r8a66597_write(r8a66597, info->pipe, PIPESEL);
  271. if (info->dir_in)
  272. pipecfg |= R8A66597_DIR;
  273. pipecfg |= info->type;
  274. pipecfg |= info->epnum;
  275. switch (info->type) {
  276. case R8A66597_INT:
  277. bufnum = 4 + (info->pipe - R8A66597_BASE_PIPENUM_INT);
  278. buf_bsize = 0;
  279. break;
  280. case R8A66597_BULK:
  281. /* isochronous pipes may be used as bulk pipes */
  282. if (info->pipe >= R8A66597_BASE_PIPENUM_BULK)
  283. bufnum = info->pipe - R8A66597_BASE_PIPENUM_BULK;
  284. else
  285. bufnum = info->pipe - R8A66597_BASE_PIPENUM_ISOC;
  286. bufnum = R8A66597_BASE_BUFNUM + (bufnum * 16);
  287. buf_bsize = 7;
  288. pipecfg |= R8A66597_DBLB;
  289. if (!info->dir_in)
  290. pipecfg |= R8A66597_SHTNAK;
  291. break;
  292. case R8A66597_ISO:
  293. bufnum = R8A66597_BASE_BUFNUM +
  294. (info->pipe - R8A66597_BASE_PIPENUM_ISOC) * 16;
  295. buf_bsize = 7;
  296. break;
  297. }
  298. if (buf_bsize && ((bufnum + 16) >= R8A66597_MAX_BUFNUM)) {
  299. pr_err("r8a66597 pipe memory is insufficient\n");
  300. return -ENOMEM;
  301. }
  302. r8a66597_write(r8a66597, pipecfg, PIPECFG);
  303. r8a66597_write(r8a66597, (buf_bsize << 10) | (bufnum), PIPEBUF);
  304. r8a66597_write(r8a66597, info->maxpacket, PIPEMAXP);
  305. if (info->interval)
  306. info->interval--;
  307. r8a66597_write(r8a66597, info->interval, PIPEPERI);
  308. return 0;
  309. }
  310. static void pipe_buffer_release(struct r8a66597 *r8a66597,
  311. struct r8a66597_pipe_info *info)
  312. {
  313. if (info->pipe == 0)
  314. return;
  315. if (is_bulk_pipe(info->pipe)) {
  316. r8a66597->bulk--;
  317. } else if (is_interrupt_pipe(info->pipe)) {
  318. r8a66597->interrupt--;
  319. } else if (is_isoc_pipe(info->pipe)) {
  320. r8a66597->isochronous--;
  321. if (info->type == R8A66597_BULK)
  322. r8a66597->bulk--;
  323. } else {
  324. dev_err(r8a66597_to_dev(r8a66597),
  325. "ep_release: unexpect pipenum (%d)\n", info->pipe);
  326. }
  327. }
  328. static void pipe_initialize(struct r8a66597_ep *ep)
  329. {
  330. struct r8a66597 *r8a66597 = ep->r8a66597;
  331. r8a66597_mdfy(r8a66597, 0, CURPIPE, ep->fifosel);
  332. r8a66597_write(r8a66597, ACLRM, ep->pipectr);
  333. r8a66597_write(r8a66597, 0, ep->pipectr);
  334. r8a66597_write(r8a66597, SQCLR, ep->pipectr);
  335. if (ep->use_dma) {
  336. r8a66597_mdfy(r8a66597, ep->pipenum, CURPIPE, ep->fifosel);
  337. ndelay(450);
  338. r8a66597_bset(r8a66597, mbw_value(r8a66597), ep->fifosel);
  339. }
  340. }
  341. static void r8a66597_ep_setting(struct r8a66597 *r8a66597,
  342. struct r8a66597_ep *ep,
  343. const struct usb_endpoint_descriptor *desc,
  344. u16 pipenum, int dma)
  345. {
  346. ep->use_dma = 0;
  347. ep->fifoaddr = CFIFO;
  348. ep->fifosel = CFIFOSEL;
  349. ep->fifoctr = CFIFOCTR;
  350. ep->pipectr = get_pipectr_addr(pipenum);
  351. if (is_bulk_pipe(pipenum) || is_isoc_pipe(pipenum)) {
  352. ep->pipetre = get_pipetre_addr(pipenum);
  353. ep->pipetrn = get_pipetrn_addr(pipenum);
  354. } else {
  355. ep->pipetre = 0;
  356. ep->pipetrn = 0;
  357. }
  358. ep->pipenum = pipenum;
  359. ep->ep.maxpacket = usb_endpoint_maxp(desc);
  360. r8a66597->pipenum2ep[pipenum] = ep;
  361. r8a66597->epaddr2ep[usb_endpoint_num(desc)]
  362. = ep;
  363. INIT_LIST_HEAD(&ep->queue);
  364. }
  365. static void r8a66597_ep_release(struct r8a66597_ep *ep)
  366. {
  367. struct r8a66597 *r8a66597 = ep->r8a66597;
  368. u16 pipenum = ep->pipenum;
  369. if (pipenum == 0)
  370. return;
  371. if (ep->use_dma)
  372. r8a66597->num_dma--;
  373. ep->pipenum = 0;
  374. ep->busy = 0;
  375. ep->use_dma = 0;
  376. }
  377. static int alloc_pipe_config(struct r8a66597_ep *ep,
  378. const struct usb_endpoint_descriptor *desc)
  379. {
  380. struct r8a66597 *r8a66597 = ep->r8a66597;
  381. struct r8a66597_pipe_info info;
  382. int dma = 0;
  383. unsigned char *counter;
  384. int ret;
  385. ep->ep.desc = desc;
  386. if (ep->pipenum) /* already allocated pipe */
  387. return 0;
  388. switch (usb_endpoint_type(desc)) {
  389. case USB_ENDPOINT_XFER_BULK:
  390. if (r8a66597->bulk >= R8A66597_MAX_NUM_BULK) {
  391. if (r8a66597->isochronous >= R8A66597_MAX_NUM_ISOC) {
  392. dev_err(r8a66597_to_dev(r8a66597),
  393. "bulk pipe is insufficient\n");
  394. return -ENODEV;
  395. } else {
  396. info.pipe = R8A66597_BASE_PIPENUM_ISOC
  397. + r8a66597->isochronous;
  398. counter = &r8a66597->isochronous;
  399. }
  400. } else {
  401. info.pipe = R8A66597_BASE_PIPENUM_BULK + r8a66597->bulk;
  402. counter = &r8a66597->bulk;
  403. }
  404. info.type = R8A66597_BULK;
  405. dma = 1;
  406. break;
  407. case USB_ENDPOINT_XFER_INT:
  408. if (r8a66597->interrupt >= R8A66597_MAX_NUM_INT) {
  409. dev_err(r8a66597_to_dev(r8a66597),
  410. "interrupt pipe is insufficient\n");
  411. return -ENODEV;
  412. }
  413. info.pipe = R8A66597_BASE_PIPENUM_INT + r8a66597->interrupt;
  414. info.type = R8A66597_INT;
  415. counter = &r8a66597->interrupt;
  416. break;
  417. case USB_ENDPOINT_XFER_ISOC:
  418. if (r8a66597->isochronous >= R8A66597_MAX_NUM_ISOC) {
  419. dev_err(r8a66597_to_dev(r8a66597),
  420. "isochronous pipe is insufficient\n");
  421. return -ENODEV;
  422. }
  423. info.pipe = R8A66597_BASE_PIPENUM_ISOC + r8a66597->isochronous;
  424. info.type = R8A66597_ISO;
  425. counter = &r8a66597->isochronous;
  426. break;
  427. default:
  428. dev_err(r8a66597_to_dev(r8a66597), "unexpect xfer type\n");
  429. return -EINVAL;
  430. }
  431. ep->type = info.type;
  432. info.epnum = usb_endpoint_num(desc);
  433. info.maxpacket = usb_endpoint_maxp(desc);
  434. info.interval = desc->bInterval;
  435. if (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK)
  436. info.dir_in = 1;
  437. else
  438. info.dir_in = 0;
  439. ret = pipe_buffer_setting(r8a66597, &info);
  440. if (ret < 0) {
  441. dev_err(r8a66597_to_dev(r8a66597),
  442. "pipe_buffer_setting fail\n");
  443. return ret;
  444. }
  445. (*counter)++;
  446. if ((counter == &r8a66597->isochronous) && info.type == R8A66597_BULK)
  447. r8a66597->bulk++;
  448. r8a66597_ep_setting(r8a66597, ep, desc, info.pipe, dma);
  449. pipe_initialize(ep);
  450. return 0;
  451. }
  452. static int free_pipe_config(struct r8a66597_ep *ep)
  453. {
  454. struct r8a66597 *r8a66597 = ep->r8a66597;
  455. struct r8a66597_pipe_info info;
  456. info.pipe = ep->pipenum;
  457. info.type = ep->type;
  458. pipe_buffer_release(r8a66597, &info);
  459. r8a66597_ep_release(ep);
  460. return 0;
  461. }
  462. /*-------------------------------------------------------------------------*/
  463. static void pipe_irq_enable(struct r8a66597 *r8a66597, u16 pipenum)
  464. {
  465. enable_irq_ready(r8a66597, pipenum);
  466. enable_irq_nrdy(r8a66597, pipenum);
  467. }
  468. static void pipe_irq_disable(struct r8a66597 *r8a66597, u16 pipenum)
  469. {
  470. disable_irq_ready(r8a66597, pipenum);
  471. disable_irq_nrdy(r8a66597, pipenum);
  472. }
  473. /* if complete is true, gadget driver complete function is not call */
  474. static void control_end(struct r8a66597 *r8a66597, unsigned ccpl)
  475. {
  476. r8a66597->ep[0].internal_ccpl = ccpl;
  477. pipe_start(r8a66597, 0);
  478. r8a66597_bset(r8a66597, CCPL, DCPCTR);
  479. }
  480. static void start_ep0_write(struct r8a66597_ep *ep,
  481. struct r8a66597_request *req)
  482. {
  483. struct r8a66597 *r8a66597 = ep->r8a66597;
  484. pipe_change(r8a66597, ep->pipenum);
  485. r8a66597_mdfy(r8a66597, ISEL, (ISEL | CURPIPE), CFIFOSEL);
  486. r8a66597_write(r8a66597, BCLR, ep->fifoctr);
  487. if (req->req.length == 0) {
  488. r8a66597_bset(r8a66597, BVAL, ep->fifoctr);
  489. pipe_start(r8a66597, 0);
  490. transfer_complete(ep, req, 0);
  491. } else {
  492. r8a66597_write(r8a66597, ~BEMP0, BEMPSTS);
  493. irq_ep0_write(ep, req);
  494. }
  495. }
  496. static void disable_fifosel(struct r8a66597 *r8a66597, u16 pipenum,
  497. u16 fifosel)
  498. {
  499. u16 tmp;
  500. tmp = r8a66597_read(r8a66597, fifosel) & CURPIPE;
  501. if (tmp == pipenum)
  502. r8a66597_change_curpipe(r8a66597, 0, 0, fifosel);
  503. }
  504. static void change_bfre_mode(struct r8a66597 *r8a66597, u16 pipenum,
  505. int enable)
  506. {
  507. struct r8a66597_ep *ep = r8a66597->pipenum2ep[pipenum];
  508. u16 tmp, toggle;
  509. /* check current BFRE bit */
  510. r8a66597_write(r8a66597, pipenum, PIPESEL);
  511. tmp = r8a66597_read(r8a66597, PIPECFG) & R8A66597_BFRE;
  512. if ((enable && tmp) || (!enable && !tmp))
  513. return;
  514. /* change BFRE bit */
  515. pipe_stop(r8a66597, pipenum);
  516. disable_fifosel(r8a66597, pipenum, CFIFOSEL);
  517. disable_fifosel(r8a66597, pipenum, D0FIFOSEL);
  518. disable_fifosel(r8a66597, pipenum, D1FIFOSEL);
  519. toggle = save_usb_toggle(r8a66597, pipenum);
  520. r8a66597_write(r8a66597, pipenum, PIPESEL);
  521. if (enable)
  522. r8a66597_bset(r8a66597, R8A66597_BFRE, PIPECFG);
  523. else
  524. r8a66597_bclr(r8a66597, R8A66597_BFRE, PIPECFG);
  525. /* initialize for internal BFRE flag */
  526. r8a66597_bset(r8a66597, ACLRM, ep->pipectr);
  527. r8a66597_bclr(r8a66597, ACLRM, ep->pipectr);
  528. restore_usb_toggle(r8a66597, pipenum, toggle);
  529. }
  530. static int sudmac_alloc_channel(struct r8a66597 *r8a66597,
  531. struct r8a66597_ep *ep,
  532. struct r8a66597_request *req)
  533. {
  534. struct r8a66597_dma *dma;
  535. if (!r8a66597_is_sudmac(r8a66597))
  536. return -ENODEV;
  537. /* Check transfer type */
  538. if (!is_bulk_pipe(ep->pipenum))
  539. return -EIO;
  540. if (r8a66597->dma.used)
  541. return -EBUSY;
  542. /* set SUDMAC parameters */
  543. dma = &r8a66597->dma;
  544. dma->used = 1;
  545. if (ep->ep.desc->bEndpointAddress & USB_DIR_IN) {
  546. dma->dir = 1;
  547. } else {
  548. dma->dir = 0;
  549. change_bfre_mode(r8a66597, ep->pipenum, 1);
  550. }
  551. /* set r8a66597_ep paramters */
  552. ep->use_dma = 1;
  553. ep->dma = dma;
  554. ep->fifoaddr = D0FIFO;
  555. ep->fifosel = D0FIFOSEL;
  556. ep->fifoctr = D0FIFOCTR;
  557. /* dma mapping */
  558. return usb_gadget_map_request(&r8a66597->gadget, &req->req, dma->dir);
  559. }
  560. static void sudmac_free_channel(struct r8a66597 *r8a66597,
  561. struct r8a66597_ep *ep,
  562. struct r8a66597_request *req)
  563. {
  564. if (!r8a66597_is_sudmac(r8a66597))
  565. return;
  566. usb_gadget_unmap_request(&r8a66597->gadget, &req->req, ep->dma->dir);
  567. r8a66597_bclr(r8a66597, DREQE, ep->fifosel);
  568. r8a66597_change_curpipe(r8a66597, 0, 0, ep->fifosel);
  569. ep->dma->used = 0;
  570. ep->use_dma = 0;
  571. ep->fifoaddr = CFIFO;
  572. ep->fifosel = CFIFOSEL;
  573. ep->fifoctr = CFIFOCTR;
  574. }
  575. static void sudmac_start(struct r8a66597 *r8a66597, struct r8a66597_ep *ep,
  576. struct r8a66597_request *req)
  577. {
  578. BUG_ON(req->req.length == 0);
  579. r8a66597_sudmac_write(r8a66597, LBA_WAIT, CH0CFG);
  580. r8a66597_sudmac_write(r8a66597, req->req.dma, CH0BA);
  581. r8a66597_sudmac_write(r8a66597, req->req.length, CH0BBC);
  582. r8a66597_sudmac_write(r8a66597, CH0ENDE, DINTCTRL);
  583. r8a66597_sudmac_write(r8a66597, DEN, CH0DEN);
  584. }
  585. static void start_packet_write(struct r8a66597_ep *ep,
  586. struct r8a66597_request *req)
  587. {
  588. struct r8a66597 *r8a66597 = ep->r8a66597;
  589. u16 tmp;
  590. pipe_change(r8a66597, ep->pipenum);
  591. disable_irq_empty(r8a66597, ep->pipenum);
  592. pipe_start(r8a66597, ep->pipenum);
  593. if (req->req.length == 0) {
  594. transfer_complete(ep, req, 0);
  595. } else {
  596. r8a66597_write(r8a66597, ~(1 << ep->pipenum), BRDYSTS);
  597. if (sudmac_alloc_channel(r8a66597, ep, req) < 0) {
  598. /* PIO mode */
  599. pipe_change(r8a66597, ep->pipenum);
  600. disable_irq_empty(r8a66597, ep->pipenum);
  601. pipe_start(r8a66597, ep->pipenum);
  602. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  603. if (unlikely((tmp & FRDY) == 0))
  604. pipe_irq_enable(r8a66597, ep->pipenum);
  605. else
  606. irq_packet_write(ep, req);
  607. } else {
  608. /* DMA mode */
  609. pipe_change(r8a66597, ep->pipenum);
  610. disable_irq_nrdy(r8a66597, ep->pipenum);
  611. pipe_start(r8a66597, ep->pipenum);
  612. enable_irq_nrdy(r8a66597, ep->pipenum);
  613. sudmac_start(r8a66597, ep, req);
  614. }
  615. }
  616. }
  617. static void start_packet_read(struct r8a66597_ep *ep,
  618. struct r8a66597_request *req)
  619. {
  620. struct r8a66597 *r8a66597 = ep->r8a66597;
  621. u16 pipenum = ep->pipenum;
  622. if (ep->pipenum == 0) {
  623. r8a66597_mdfy(r8a66597, 0, (ISEL | CURPIPE), CFIFOSEL);
  624. r8a66597_write(r8a66597, BCLR, ep->fifoctr);
  625. pipe_start(r8a66597, pipenum);
  626. pipe_irq_enable(r8a66597, pipenum);
  627. } else {
  628. pipe_stop(r8a66597, pipenum);
  629. if (ep->pipetre) {
  630. enable_irq_nrdy(r8a66597, pipenum);
  631. r8a66597_write(r8a66597, TRCLR, ep->pipetre);
  632. r8a66597_write(r8a66597,
  633. DIV_ROUND_UP(req->req.length, ep->ep.maxpacket),
  634. ep->pipetrn);
  635. r8a66597_bset(r8a66597, TRENB, ep->pipetre);
  636. }
  637. if (sudmac_alloc_channel(r8a66597, ep, req) < 0) {
  638. /* PIO mode */
  639. change_bfre_mode(r8a66597, ep->pipenum, 0);
  640. pipe_start(r8a66597, pipenum); /* trigger once */
  641. pipe_irq_enable(r8a66597, pipenum);
  642. } else {
  643. pipe_change(r8a66597, pipenum);
  644. sudmac_start(r8a66597, ep, req);
  645. pipe_start(r8a66597, pipenum); /* trigger once */
  646. }
  647. }
  648. }
  649. static void start_packet(struct r8a66597_ep *ep, struct r8a66597_request *req)
  650. {
  651. if (ep->ep.desc->bEndpointAddress & USB_DIR_IN)
  652. start_packet_write(ep, req);
  653. else
  654. start_packet_read(ep, req);
  655. }
  656. static void start_ep0(struct r8a66597_ep *ep, struct r8a66597_request *req)
  657. {
  658. u16 ctsq;
  659. ctsq = r8a66597_read(ep->r8a66597, INTSTS0) & CTSQ;
  660. switch (ctsq) {
  661. case CS_RDDS:
  662. start_ep0_write(ep, req);
  663. break;
  664. case CS_WRDS:
  665. start_packet_read(ep, req);
  666. break;
  667. case CS_WRND:
  668. control_end(ep->r8a66597, 0);
  669. break;
  670. default:
  671. dev_err(r8a66597_to_dev(ep->r8a66597),
  672. "start_ep0: unexpect ctsq(%x)\n", ctsq);
  673. break;
  674. }
  675. }
  676. static void init_controller(struct r8a66597 *r8a66597)
  677. {
  678. u16 vif = r8a66597->pdata->vif ? LDRV : 0;
  679. u16 irq_sense = r8a66597->irq_sense_low ? INTL : 0;
  680. u16 endian = r8a66597->pdata->endian ? BIGEND : 0;
  681. if (r8a66597->pdata->on_chip) {
  682. if (r8a66597->pdata->buswait)
  683. r8a66597_write(r8a66597, r8a66597->pdata->buswait,
  684. SYSCFG1);
  685. else
  686. r8a66597_write(r8a66597, 0x0f, SYSCFG1);
  687. r8a66597_bset(r8a66597, HSE, SYSCFG0);
  688. r8a66597_bclr(r8a66597, USBE, SYSCFG0);
  689. r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
  690. r8a66597_bset(r8a66597, USBE, SYSCFG0);
  691. r8a66597_bset(r8a66597, SCKE, SYSCFG0);
  692. r8a66597_bset(r8a66597, irq_sense, INTENB1);
  693. r8a66597_write(r8a66597, BURST | CPU_ADR_RD_WR,
  694. DMA0CFG);
  695. } else {
  696. r8a66597_bset(r8a66597, vif | endian, PINCFG);
  697. r8a66597_bset(r8a66597, HSE, SYSCFG0); /* High spd */
  698. r8a66597_mdfy(r8a66597, get_xtal_from_pdata(r8a66597->pdata),
  699. XTAL, SYSCFG0);
  700. r8a66597_bclr(r8a66597, USBE, SYSCFG0);
  701. r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
  702. r8a66597_bset(r8a66597, USBE, SYSCFG0);
  703. r8a66597_bset(r8a66597, XCKE, SYSCFG0);
  704. mdelay(3);
  705. r8a66597_bset(r8a66597, PLLC, SYSCFG0);
  706. mdelay(1);
  707. r8a66597_bset(r8a66597, SCKE, SYSCFG0);
  708. r8a66597_bset(r8a66597, irq_sense, INTENB1);
  709. r8a66597_write(r8a66597, BURST | CPU_ADR_RD_WR,
  710. DMA0CFG);
  711. }
  712. }
  713. static void disable_controller(struct r8a66597 *r8a66597)
  714. {
  715. if (r8a66597->pdata->on_chip) {
  716. r8a66597_bset(r8a66597, SCKE, SYSCFG0);
  717. r8a66597_bclr(r8a66597, UTST, TESTMODE);
  718. /* disable interrupts */
  719. r8a66597_write(r8a66597, 0, INTENB0);
  720. r8a66597_write(r8a66597, 0, INTENB1);
  721. r8a66597_write(r8a66597, 0, BRDYENB);
  722. r8a66597_write(r8a66597, 0, BEMPENB);
  723. r8a66597_write(r8a66597, 0, NRDYENB);
  724. /* clear status */
  725. r8a66597_write(r8a66597, 0, BRDYSTS);
  726. r8a66597_write(r8a66597, 0, NRDYSTS);
  727. r8a66597_write(r8a66597, 0, BEMPSTS);
  728. r8a66597_bclr(r8a66597, USBE, SYSCFG0);
  729. r8a66597_bclr(r8a66597, SCKE, SYSCFG0);
  730. } else {
  731. r8a66597_bclr(r8a66597, UTST, TESTMODE);
  732. r8a66597_bclr(r8a66597, SCKE, SYSCFG0);
  733. udelay(1);
  734. r8a66597_bclr(r8a66597, PLLC, SYSCFG0);
  735. udelay(1);
  736. udelay(1);
  737. r8a66597_bclr(r8a66597, XCKE, SYSCFG0);
  738. }
  739. }
  740. static void r8a66597_start_xclock(struct r8a66597 *r8a66597)
  741. {
  742. u16 tmp;
  743. if (!r8a66597->pdata->on_chip) {
  744. tmp = r8a66597_read(r8a66597, SYSCFG0);
  745. if (!(tmp & XCKE))
  746. r8a66597_bset(r8a66597, XCKE, SYSCFG0);
  747. }
  748. }
  749. static struct r8a66597_request *get_request_from_ep(struct r8a66597_ep *ep)
  750. {
  751. return list_entry(ep->queue.next, struct r8a66597_request, queue);
  752. }
  753. /*-------------------------------------------------------------------------*/
  754. static void transfer_complete(struct r8a66597_ep *ep,
  755. struct r8a66597_request *req, int status)
  756. __releases(r8a66597->lock)
  757. __acquires(r8a66597->lock)
  758. {
  759. int restart = 0;
  760. if (unlikely(ep->pipenum == 0)) {
  761. if (ep->internal_ccpl) {
  762. ep->internal_ccpl = 0;
  763. return;
  764. }
  765. }
  766. list_del_init(&req->queue);
  767. if (ep->r8a66597->gadget.speed == USB_SPEED_UNKNOWN)
  768. req->req.status = -ESHUTDOWN;
  769. else
  770. req->req.status = status;
  771. if (!list_empty(&ep->queue))
  772. restart = 1;
  773. if (ep->use_dma)
  774. sudmac_free_channel(ep->r8a66597, ep, req);
  775. spin_unlock(&ep->r8a66597->lock);
  776. usb_gadget_giveback_request(&ep->ep, &req->req);
  777. spin_lock(&ep->r8a66597->lock);
  778. if (restart) {
  779. req = get_request_from_ep(ep);
  780. if (ep->ep.desc)
  781. start_packet(ep, req);
  782. }
  783. }
  784. static void irq_ep0_write(struct r8a66597_ep *ep, struct r8a66597_request *req)
  785. {
  786. int i;
  787. u16 tmp;
  788. unsigned bufsize;
  789. size_t size;
  790. void *buf;
  791. u16 pipenum = ep->pipenum;
  792. struct r8a66597 *r8a66597 = ep->r8a66597;
  793. pipe_change(r8a66597, pipenum);
  794. r8a66597_bset(r8a66597, ISEL, ep->fifosel);
  795. i = 0;
  796. do {
  797. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  798. if (i++ > 100000) {
  799. dev_err(r8a66597_to_dev(r8a66597),
  800. "pipe0 is busy. maybe cpu i/o bus "
  801. "conflict. please power off this controller.");
  802. return;
  803. }
  804. ndelay(1);
  805. } while ((tmp & FRDY) == 0);
  806. /* prepare parameters */
  807. bufsize = get_buffer_size(r8a66597, pipenum);
  808. buf = req->req.buf + req->req.actual;
  809. size = min(bufsize, req->req.length - req->req.actual);
  810. /* write fifo */
  811. if (req->req.buf) {
  812. if (size > 0)
  813. r8a66597_write_fifo(r8a66597, ep, buf, size);
  814. if ((size == 0) || ((size % ep->ep.maxpacket) != 0))
  815. r8a66597_bset(r8a66597, BVAL, ep->fifoctr);
  816. }
  817. /* update parameters */
  818. req->req.actual += size;
  819. /* check transfer finish */
  820. if ((!req->req.zero && (req->req.actual == req->req.length))
  821. || (size % ep->ep.maxpacket)
  822. || (size == 0)) {
  823. disable_irq_ready(r8a66597, pipenum);
  824. disable_irq_empty(r8a66597, pipenum);
  825. } else {
  826. disable_irq_ready(r8a66597, pipenum);
  827. enable_irq_empty(r8a66597, pipenum);
  828. }
  829. pipe_start(r8a66597, pipenum);
  830. }
  831. static void irq_packet_write(struct r8a66597_ep *ep,
  832. struct r8a66597_request *req)
  833. {
  834. u16 tmp;
  835. unsigned bufsize;
  836. size_t size;
  837. void *buf;
  838. u16 pipenum = ep->pipenum;
  839. struct r8a66597 *r8a66597 = ep->r8a66597;
  840. pipe_change(r8a66597, pipenum);
  841. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  842. if (unlikely((tmp & FRDY) == 0)) {
  843. pipe_stop(r8a66597, pipenum);
  844. pipe_irq_disable(r8a66597, pipenum);
  845. dev_err(r8a66597_to_dev(r8a66597),
  846. "write fifo not ready. pipnum=%d\n", pipenum);
  847. return;
  848. }
  849. /* prepare parameters */
  850. bufsize = get_buffer_size(r8a66597, pipenum);
  851. buf = req->req.buf + req->req.actual;
  852. size = min(bufsize, req->req.length - req->req.actual);
  853. /* write fifo */
  854. if (req->req.buf) {
  855. r8a66597_write_fifo(r8a66597, ep, buf, size);
  856. if ((size == 0)
  857. || ((size % ep->ep.maxpacket) != 0)
  858. || ((bufsize != ep->ep.maxpacket)
  859. && (bufsize > size)))
  860. r8a66597_bset(r8a66597, BVAL, ep->fifoctr);
  861. }
  862. /* update parameters */
  863. req->req.actual += size;
  864. /* check transfer finish */
  865. if ((!req->req.zero && (req->req.actual == req->req.length))
  866. || (size % ep->ep.maxpacket)
  867. || (size == 0)) {
  868. disable_irq_ready(r8a66597, pipenum);
  869. enable_irq_empty(r8a66597, pipenum);
  870. } else {
  871. disable_irq_empty(r8a66597, pipenum);
  872. pipe_irq_enable(r8a66597, pipenum);
  873. }
  874. }
  875. static void irq_packet_read(struct r8a66597_ep *ep,
  876. struct r8a66597_request *req)
  877. {
  878. u16 tmp;
  879. int rcv_len, bufsize, req_len;
  880. int size;
  881. void *buf;
  882. u16 pipenum = ep->pipenum;
  883. struct r8a66597 *r8a66597 = ep->r8a66597;
  884. int finish = 0;
  885. pipe_change(r8a66597, pipenum);
  886. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  887. if (unlikely((tmp & FRDY) == 0)) {
  888. req->req.status = -EPIPE;
  889. pipe_stop(r8a66597, pipenum);
  890. pipe_irq_disable(r8a66597, pipenum);
  891. dev_err(r8a66597_to_dev(r8a66597), "read fifo not ready");
  892. return;
  893. }
  894. /* prepare parameters */
  895. rcv_len = tmp & DTLN;
  896. bufsize = get_buffer_size(r8a66597, pipenum);
  897. buf = req->req.buf + req->req.actual;
  898. req_len = req->req.length - req->req.actual;
  899. if (rcv_len < bufsize)
  900. size = min(rcv_len, req_len);
  901. else
  902. size = min(bufsize, req_len);
  903. /* update parameters */
  904. req->req.actual += size;
  905. /* check transfer finish */
  906. if ((!req->req.zero && (req->req.actual == req->req.length))
  907. || (size % ep->ep.maxpacket)
  908. || (size == 0)) {
  909. pipe_stop(r8a66597, pipenum);
  910. pipe_irq_disable(r8a66597, pipenum);
  911. finish = 1;
  912. }
  913. /* read fifo */
  914. if (req->req.buf) {
  915. if (size == 0)
  916. r8a66597_write(r8a66597, BCLR, ep->fifoctr);
  917. else
  918. r8a66597_read_fifo(r8a66597, ep->fifoaddr, buf, size);
  919. }
  920. if ((ep->pipenum != 0) && finish)
  921. transfer_complete(ep, req, 0);
  922. }
  923. static void irq_pipe_ready(struct r8a66597 *r8a66597, u16 status, u16 enb)
  924. {
  925. u16 check;
  926. u16 pipenum;
  927. struct r8a66597_ep *ep;
  928. struct r8a66597_request *req;
  929. if ((status & BRDY0) && (enb & BRDY0)) {
  930. r8a66597_write(r8a66597, ~BRDY0, BRDYSTS);
  931. r8a66597_mdfy(r8a66597, 0, CURPIPE, CFIFOSEL);
  932. ep = &r8a66597->ep[0];
  933. req = get_request_from_ep(ep);
  934. irq_packet_read(ep, req);
  935. } else {
  936. for (pipenum = 1; pipenum < R8A66597_MAX_NUM_PIPE; pipenum++) {
  937. check = 1 << pipenum;
  938. if ((status & check) && (enb & check)) {
  939. r8a66597_write(r8a66597, ~check, BRDYSTS);
  940. ep = r8a66597->pipenum2ep[pipenum];
  941. req = get_request_from_ep(ep);
  942. if (ep->ep.desc->bEndpointAddress & USB_DIR_IN)
  943. irq_packet_write(ep, req);
  944. else
  945. irq_packet_read(ep, req);
  946. }
  947. }
  948. }
  949. }
  950. static void irq_pipe_empty(struct r8a66597 *r8a66597, u16 status, u16 enb)
  951. {
  952. u16 tmp;
  953. u16 check;
  954. u16 pipenum;
  955. struct r8a66597_ep *ep;
  956. struct r8a66597_request *req;
  957. if ((status & BEMP0) && (enb & BEMP0)) {
  958. r8a66597_write(r8a66597, ~BEMP0, BEMPSTS);
  959. ep = &r8a66597->ep[0];
  960. req = get_request_from_ep(ep);
  961. irq_ep0_write(ep, req);
  962. } else {
  963. for (pipenum = 1; pipenum < R8A66597_MAX_NUM_PIPE; pipenum++) {
  964. check = 1 << pipenum;
  965. if ((status & check) && (enb & check)) {
  966. r8a66597_write(r8a66597, ~check, BEMPSTS);
  967. tmp = control_reg_get(r8a66597, pipenum);
  968. if ((tmp & INBUFM) == 0) {
  969. disable_irq_empty(r8a66597, pipenum);
  970. pipe_irq_disable(r8a66597, pipenum);
  971. pipe_stop(r8a66597, pipenum);
  972. ep = r8a66597->pipenum2ep[pipenum];
  973. req = get_request_from_ep(ep);
  974. if (!list_empty(&ep->queue))
  975. transfer_complete(ep, req, 0);
  976. }
  977. }
  978. }
  979. }
  980. }
  981. static void get_status(struct r8a66597 *r8a66597, struct usb_ctrlrequest *ctrl)
  982. __releases(r8a66597->lock)
  983. __acquires(r8a66597->lock)
  984. {
  985. struct r8a66597_ep *ep;
  986. u16 pid;
  987. u16 status = 0;
  988. u16 w_index = le16_to_cpu(ctrl->wIndex);
  989. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  990. case USB_RECIP_DEVICE:
  991. status = r8a66597->device_status;
  992. break;
  993. case USB_RECIP_INTERFACE:
  994. status = 0;
  995. break;
  996. case USB_RECIP_ENDPOINT:
  997. ep = r8a66597->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  998. pid = control_reg_get_pid(r8a66597, ep->pipenum);
  999. if (pid == PID_STALL)
  1000. status = 1 << USB_ENDPOINT_HALT;
  1001. else
  1002. status = 0;
  1003. break;
  1004. default:
  1005. pipe_stall(r8a66597, 0);
  1006. return; /* exit */
  1007. }
  1008. r8a66597->ep0_data = cpu_to_le16(status);
  1009. r8a66597->ep0_req->buf = &r8a66597->ep0_data;
  1010. r8a66597->ep0_req->length = 2;
  1011. /* AV: what happens if we get called again before that gets through? */
  1012. spin_unlock(&r8a66597->lock);
  1013. r8a66597_queue(r8a66597->gadget.ep0, r8a66597->ep0_req, GFP_ATOMIC);
  1014. spin_lock(&r8a66597->lock);
  1015. }
  1016. static void clear_feature(struct r8a66597 *r8a66597,
  1017. struct usb_ctrlrequest *ctrl)
  1018. {
  1019. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  1020. case USB_RECIP_DEVICE:
  1021. control_end(r8a66597, 1);
  1022. break;
  1023. case USB_RECIP_INTERFACE:
  1024. control_end(r8a66597, 1);
  1025. break;
  1026. case USB_RECIP_ENDPOINT: {
  1027. struct r8a66597_ep *ep;
  1028. struct r8a66597_request *req;
  1029. u16 w_index = le16_to_cpu(ctrl->wIndex);
  1030. ep = r8a66597->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  1031. if (!ep->wedge) {
  1032. pipe_stop(r8a66597, ep->pipenum);
  1033. control_reg_sqclr(r8a66597, ep->pipenum);
  1034. spin_unlock(&r8a66597->lock);
  1035. usb_ep_clear_halt(&ep->ep);
  1036. spin_lock(&r8a66597->lock);
  1037. }
  1038. control_end(r8a66597, 1);
  1039. req = get_request_from_ep(ep);
  1040. if (ep->busy) {
  1041. ep->busy = 0;
  1042. if (list_empty(&ep->queue))
  1043. break;
  1044. start_packet(ep, req);
  1045. } else if (!list_empty(&ep->queue))
  1046. pipe_start(r8a66597, ep->pipenum);
  1047. }
  1048. break;
  1049. default:
  1050. pipe_stall(r8a66597, 0);
  1051. break;
  1052. }
  1053. }
  1054. static void set_feature(struct r8a66597 *r8a66597, struct usb_ctrlrequest *ctrl)
  1055. {
  1056. u16 tmp;
  1057. int timeout = 3000;
  1058. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  1059. case USB_RECIP_DEVICE:
  1060. switch (le16_to_cpu(ctrl->wValue)) {
  1061. case USB_DEVICE_TEST_MODE:
  1062. control_end(r8a66597, 1);
  1063. /* Wait for the completion of status stage */
  1064. do {
  1065. tmp = r8a66597_read(r8a66597, INTSTS0) & CTSQ;
  1066. udelay(1);
  1067. } while (tmp != CS_IDST || timeout-- > 0);
  1068. if (tmp == CS_IDST)
  1069. r8a66597_bset(r8a66597,
  1070. le16_to_cpu(ctrl->wIndex >> 8),
  1071. TESTMODE);
  1072. break;
  1073. default:
  1074. pipe_stall(r8a66597, 0);
  1075. break;
  1076. }
  1077. break;
  1078. case USB_RECIP_INTERFACE:
  1079. control_end(r8a66597, 1);
  1080. break;
  1081. case USB_RECIP_ENDPOINT: {
  1082. struct r8a66597_ep *ep;
  1083. u16 w_index = le16_to_cpu(ctrl->wIndex);
  1084. ep = r8a66597->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  1085. pipe_stall(r8a66597, ep->pipenum);
  1086. control_end(r8a66597, 1);
  1087. }
  1088. break;
  1089. default:
  1090. pipe_stall(r8a66597, 0);
  1091. break;
  1092. }
  1093. }
  1094. /* if return value is true, call class driver's setup() */
  1095. static int setup_packet(struct r8a66597 *r8a66597, struct usb_ctrlrequest *ctrl)
  1096. {
  1097. u16 *p = (u16 *)ctrl;
  1098. unsigned long offset = USBREQ;
  1099. int i, ret = 0;
  1100. /* read fifo */
  1101. r8a66597_write(r8a66597, ~VALID, INTSTS0);
  1102. for (i = 0; i < 4; i++)
  1103. p[i] = r8a66597_read(r8a66597, offset + i*2);
  1104. /* check request */
  1105. if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
  1106. switch (ctrl->bRequest) {
  1107. case USB_REQ_GET_STATUS:
  1108. get_status(r8a66597, ctrl);
  1109. break;
  1110. case USB_REQ_CLEAR_FEATURE:
  1111. clear_feature(r8a66597, ctrl);
  1112. break;
  1113. case USB_REQ_SET_FEATURE:
  1114. set_feature(r8a66597, ctrl);
  1115. break;
  1116. default:
  1117. ret = 1;
  1118. break;
  1119. }
  1120. } else
  1121. ret = 1;
  1122. return ret;
  1123. }
  1124. static void r8a66597_update_usb_speed(struct r8a66597 *r8a66597)
  1125. {
  1126. u16 speed = get_usb_speed(r8a66597);
  1127. switch (speed) {
  1128. case HSMODE:
  1129. r8a66597->gadget.speed = USB_SPEED_HIGH;
  1130. break;
  1131. case FSMODE:
  1132. r8a66597->gadget.speed = USB_SPEED_FULL;
  1133. break;
  1134. default:
  1135. r8a66597->gadget.speed = USB_SPEED_UNKNOWN;
  1136. dev_err(r8a66597_to_dev(r8a66597), "USB speed unknown\n");
  1137. }
  1138. }
  1139. static void irq_device_state(struct r8a66597 *r8a66597)
  1140. {
  1141. u16 dvsq;
  1142. dvsq = r8a66597_read(r8a66597, INTSTS0) & DVSQ;
  1143. r8a66597_write(r8a66597, ~DVST, INTSTS0);
  1144. if (dvsq == DS_DFLT) {
  1145. /* bus reset */
  1146. spin_unlock(&r8a66597->lock);
  1147. usb_gadget_udc_reset(&r8a66597->gadget, r8a66597->driver);
  1148. spin_lock(&r8a66597->lock);
  1149. r8a66597_update_usb_speed(r8a66597);
  1150. }
  1151. if (r8a66597->old_dvsq == DS_CNFG && dvsq != DS_CNFG)
  1152. r8a66597_update_usb_speed(r8a66597);
  1153. if ((dvsq == DS_CNFG || dvsq == DS_ADDS)
  1154. && r8a66597->gadget.speed == USB_SPEED_UNKNOWN)
  1155. r8a66597_update_usb_speed(r8a66597);
  1156. r8a66597->old_dvsq = dvsq;
  1157. }
  1158. static void irq_control_stage(struct r8a66597 *r8a66597)
  1159. __releases(r8a66597->lock)
  1160. __acquires(r8a66597->lock)
  1161. {
  1162. struct usb_ctrlrequest ctrl;
  1163. u16 ctsq;
  1164. ctsq = r8a66597_read(r8a66597, INTSTS0) & CTSQ;
  1165. r8a66597_write(r8a66597, ~CTRT, INTSTS0);
  1166. switch (ctsq) {
  1167. case CS_IDST: {
  1168. struct r8a66597_ep *ep;
  1169. struct r8a66597_request *req;
  1170. ep = &r8a66597->ep[0];
  1171. req = get_request_from_ep(ep);
  1172. transfer_complete(ep, req, 0);
  1173. }
  1174. break;
  1175. case CS_RDDS:
  1176. case CS_WRDS:
  1177. case CS_WRND:
  1178. if (setup_packet(r8a66597, &ctrl)) {
  1179. spin_unlock(&r8a66597->lock);
  1180. if (r8a66597->driver->setup(&r8a66597->gadget, &ctrl)
  1181. < 0)
  1182. pipe_stall(r8a66597, 0);
  1183. spin_lock(&r8a66597->lock);
  1184. }
  1185. break;
  1186. case CS_RDSS:
  1187. case CS_WRSS:
  1188. control_end(r8a66597, 0);
  1189. break;
  1190. default:
  1191. dev_err(r8a66597_to_dev(r8a66597),
  1192. "ctrl_stage: unexpect ctsq(%x)\n", ctsq);
  1193. break;
  1194. }
  1195. }
  1196. static void sudmac_finish(struct r8a66597 *r8a66597, struct r8a66597_ep *ep)
  1197. {
  1198. u16 pipenum;
  1199. struct r8a66597_request *req;
  1200. u32 len;
  1201. int i = 0;
  1202. pipenum = ep->pipenum;
  1203. pipe_change(r8a66597, pipenum);
  1204. while (!(r8a66597_read(r8a66597, ep->fifoctr) & FRDY)) {
  1205. udelay(1);
  1206. if (unlikely(i++ >= 10000)) { /* timeout = 10 msec */
  1207. dev_err(r8a66597_to_dev(r8a66597),
  1208. "%s: FRDY was not set (%d)\n",
  1209. __func__, pipenum);
  1210. return;
  1211. }
  1212. }
  1213. r8a66597_bset(r8a66597, BCLR, ep->fifoctr);
  1214. req = get_request_from_ep(ep);
  1215. /* prepare parameters */
  1216. len = r8a66597_sudmac_read(r8a66597, CH0CBC);
  1217. req->req.actual += len;
  1218. /* clear */
  1219. r8a66597_sudmac_write(r8a66597, CH0STCLR, DSTSCLR);
  1220. /* check transfer finish */
  1221. if ((!req->req.zero && (req->req.actual == req->req.length))
  1222. || (len % ep->ep.maxpacket)) {
  1223. if (ep->dma->dir) {
  1224. disable_irq_ready(r8a66597, pipenum);
  1225. enable_irq_empty(r8a66597, pipenum);
  1226. } else {
  1227. /* Clear the interrupt flag for next transfer */
  1228. r8a66597_write(r8a66597, ~(1 << pipenum), BRDYSTS);
  1229. transfer_complete(ep, req, 0);
  1230. }
  1231. }
  1232. }
  1233. static void r8a66597_sudmac_irq(struct r8a66597 *r8a66597)
  1234. {
  1235. u32 irqsts;
  1236. struct r8a66597_ep *ep;
  1237. u16 pipenum;
  1238. irqsts = r8a66597_sudmac_read(r8a66597, DINTSTS);
  1239. if (irqsts & CH0ENDS) {
  1240. r8a66597_sudmac_write(r8a66597, CH0ENDC, DINTSTSCLR);
  1241. pipenum = (r8a66597_read(r8a66597, D0FIFOSEL) & CURPIPE);
  1242. ep = r8a66597->pipenum2ep[pipenum];
  1243. sudmac_finish(r8a66597, ep);
  1244. }
  1245. }
  1246. static irqreturn_t r8a66597_irq(int irq, void *_r8a66597)
  1247. {
  1248. struct r8a66597 *r8a66597 = _r8a66597;
  1249. u16 intsts0;
  1250. u16 intenb0;
  1251. u16 savepipe;
  1252. u16 mask0;
  1253. spin_lock(&r8a66597->lock);
  1254. if (r8a66597_is_sudmac(r8a66597))
  1255. r8a66597_sudmac_irq(r8a66597);
  1256. intsts0 = r8a66597_read(r8a66597, INTSTS0);
  1257. intenb0 = r8a66597_read(r8a66597, INTENB0);
  1258. savepipe = r8a66597_read(r8a66597, CFIFOSEL);
  1259. mask0 = intsts0 & intenb0;
  1260. if (mask0) {
  1261. u16 brdysts = r8a66597_read(r8a66597, BRDYSTS);
  1262. u16 bempsts = r8a66597_read(r8a66597, BEMPSTS);
  1263. u16 brdyenb = r8a66597_read(r8a66597, BRDYENB);
  1264. u16 bempenb = r8a66597_read(r8a66597, BEMPENB);
  1265. if (mask0 & VBINT) {
  1266. r8a66597_write(r8a66597, 0xffff & ~VBINT,
  1267. INTSTS0);
  1268. r8a66597_start_xclock(r8a66597);
  1269. /* start vbus sampling */
  1270. r8a66597->old_vbus = r8a66597_read(r8a66597, INTSTS0)
  1271. & VBSTS;
  1272. r8a66597->scount = R8A66597_MAX_SAMPLING;
  1273. mod_timer(&r8a66597->timer,
  1274. jiffies + msecs_to_jiffies(50));
  1275. }
  1276. if (intsts0 & DVSQ)
  1277. irq_device_state(r8a66597);
  1278. if ((intsts0 & BRDY) && (intenb0 & BRDYE)
  1279. && (brdysts & brdyenb))
  1280. irq_pipe_ready(r8a66597, brdysts, brdyenb);
  1281. if ((intsts0 & BEMP) && (intenb0 & BEMPE)
  1282. && (bempsts & bempenb))
  1283. irq_pipe_empty(r8a66597, bempsts, bempenb);
  1284. if (intsts0 & CTRT)
  1285. irq_control_stage(r8a66597);
  1286. }
  1287. r8a66597_write(r8a66597, savepipe, CFIFOSEL);
  1288. spin_unlock(&r8a66597->lock);
  1289. return IRQ_HANDLED;
  1290. }
  1291. static void r8a66597_timer(struct timer_list *t)
  1292. {
  1293. struct r8a66597 *r8a66597 = from_timer(r8a66597, t, timer);
  1294. unsigned long flags;
  1295. u16 tmp;
  1296. spin_lock_irqsave(&r8a66597->lock, flags);
  1297. tmp = r8a66597_read(r8a66597, SYSCFG0);
  1298. if (r8a66597->scount > 0) {
  1299. tmp = r8a66597_read(r8a66597, INTSTS0) & VBSTS;
  1300. if (tmp == r8a66597->old_vbus) {
  1301. r8a66597->scount--;
  1302. if (r8a66597->scount == 0) {
  1303. if (tmp == VBSTS)
  1304. r8a66597_usb_connect(r8a66597);
  1305. else
  1306. r8a66597_usb_disconnect(r8a66597);
  1307. } else {
  1308. mod_timer(&r8a66597->timer,
  1309. jiffies + msecs_to_jiffies(50));
  1310. }
  1311. } else {
  1312. r8a66597->scount = R8A66597_MAX_SAMPLING;
  1313. r8a66597->old_vbus = tmp;
  1314. mod_timer(&r8a66597->timer,
  1315. jiffies + msecs_to_jiffies(50));
  1316. }
  1317. }
  1318. spin_unlock_irqrestore(&r8a66597->lock, flags);
  1319. }
  1320. /*-------------------------------------------------------------------------*/
  1321. static int r8a66597_enable(struct usb_ep *_ep,
  1322. const struct usb_endpoint_descriptor *desc)
  1323. {
  1324. struct r8a66597_ep *ep;
  1325. ep = container_of(_ep, struct r8a66597_ep, ep);
  1326. return alloc_pipe_config(ep, desc);
  1327. }
  1328. static int r8a66597_disable(struct usb_ep *_ep)
  1329. {
  1330. struct r8a66597_ep *ep;
  1331. struct r8a66597_request *req;
  1332. unsigned long flags;
  1333. ep = container_of(_ep, struct r8a66597_ep, ep);
  1334. BUG_ON(!ep);
  1335. while (!list_empty(&ep->queue)) {
  1336. req = get_request_from_ep(ep);
  1337. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1338. transfer_complete(ep, req, -ECONNRESET);
  1339. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1340. }
  1341. pipe_irq_disable(ep->r8a66597, ep->pipenum);
  1342. return free_pipe_config(ep);
  1343. }
  1344. static struct usb_request *r8a66597_alloc_request(struct usb_ep *_ep,
  1345. gfp_t gfp_flags)
  1346. {
  1347. struct r8a66597_request *req;
  1348. req = kzalloc(sizeof(struct r8a66597_request), gfp_flags);
  1349. if (!req)
  1350. return NULL;
  1351. INIT_LIST_HEAD(&req->queue);
  1352. return &req->req;
  1353. }
  1354. static void r8a66597_free_request(struct usb_ep *_ep, struct usb_request *_req)
  1355. {
  1356. struct r8a66597_request *req;
  1357. req = container_of(_req, struct r8a66597_request, req);
  1358. kfree(req);
  1359. }
  1360. static int r8a66597_queue(struct usb_ep *_ep, struct usb_request *_req,
  1361. gfp_t gfp_flags)
  1362. {
  1363. struct r8a66597_ep *ep;
  1364. struct r8a66597_request *req;
  1365. unsigned long flags;
  1366. int request = 0;
  1367. ep = container_of(_ep, struct r8a66597_ep, ep);
  1368. req = container_of(_req, struct r8a66597_request, req);
  1369. if (ep->r8a66597->gadget.speed == USB_SPEED_UNKNOWN)
  1370. return -ESHUTDOWN;
  1371. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1372. if (list_empty(&ep->queue))
  1373. request = 1;
  1374. list_add_tail(&req->queue, &ep->queue);
  1375. req->req.actual = 0;
  1376. req->req.status = -EINPROGRESS;
  1377. if (ep->ep.desc == NULL) /* control */
  1378. start_ep0(ep, req);
  1379. else {
  1380. if (request && !ep->busy)
  1381. start_packet(ep, req);
  1382. }
  1383. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1384. return 0;
  1385. }
  1386. static int r8a66597_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  1387. {
  1388. struct r8a66597_ep *ep;
  1389. struct r8a66597_request *req;
  1390. unsigned long flags;
  1391. ep = container_of(_ep, struct r8a66597_ep, ep);
  1392. req = container_of(_req, struct r8a66597_request, req);
  1393. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1394. if (!list_empty(&ep->queue))
  1395. transfer_complete(ep, req, -ECONNRESET);
  1396. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1397. return 0;
  1398. }
  1399. static int r8a66597_set_halt(struct usb_ep *_ep, int value)
  1400. {
  1401. struct r8a66597_ep *ep = container_of(_ep, struct r8a66597_ep, ep);
  1402. unsigned long flags;
  1403. int ret = 0;
  1404. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1405. if (!list_empty(&ep->queue)) {
  1406. ret = -EAGAIN;
  1407. } else if (value) {
  1408. ep->busy = 1;
  1409. pipe_stall(ep->r8a66597, ep->pipenum);
  1410. } else {
  1411. ep->busy = 0;
  1412. ep->wedge = 0;
  1413. pipe_stop(ep->r8a66597, ep->pipenum);
  1414. }
  1415. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1416. return ret;
  1417. }
  1418. static int r8a66597_set_wedge(struct usb_ep *_ep)
  1419. {
  1420. struct r8a66597_ep *ep;
  1421. unsigned long flags;
  1422. ep = container_of(_ep, struct r8a66597_ep, ep);
  1423. if (!ep || !ep->ep.desc)
  1424. return -EINVAL;
  1425. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1426. ep->wedge = 1;
  1427. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1428. return usb_ep_set_halt(_ep);
  1429. }
  1430. static void r8a66597_fifo_flush(struct usb_ep *_ep)
  1431. {
  1432. struct r8a66597_ep *ep;
  1433. unsigned long flags;
  1434. ep = container_of(_ep, struct r8a66597_ep, ep);
  1435. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1436. if (list_empty(&ep->queue) && !ep->busy) {
  1437. pipe_stop(ep->r8a66597, ep->pipenum);
  1438. r8a66597_bclr(ep->r8a66597, BCLR, ep->fifoctr);
  1439. r8a66597_write(ep->r8a66597, ACLRM, ep->pipectr);
  1440. r8a66597_write(ep->r8a66597, 0, ep->pipectr);
  1441. }
  1442. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1443. }
  1444. static const struct usb_ep_ops r8a66597_ep_ops = {
  1445. .enable = r8a66597_enable,
  1446. .disable = r8a66597_disable,
  1447. .alloc_request = r8a66597_alloc_request,
  1448. .free_request = r8a66597_free_request,
  1449. .queue = r8a66597_queue,
  1450. .dequeue = r8a66597_dequeue,
  1451. .set_halt = r8a66597_set_halt,
  1452. .set_wedge = r8a66597_set_wedge,
  1453. .fifo_flush = r8a66597_fifo_flush,
  1454. };
  1455. /*-------------------------------------------------------------------------*/
  1456. static int r8a66597_start(struct usb_gadget *gadget,
  1457. struct usb_gadget_driver *driver)
  1458. {
  1459. struct r8a66597 *r8a66597 = gadget_to_r8a66597(gadget);
  1460. if (!driver
  1461. || driver->max_speed < USB_SPEED_HIGH
  1462. || !driver->setup)
  1463. return -EINVAL;
  1464. if (!r8a66597)
  1465. return -ENODEV;
  1466. /* hook up the driver */
  1467. r8a66597->driver = driver;
  1468. init_controller(r8a66597);
  1469. r8a66597_bset(r8a66597, VBSE, INTENB0);
  1470. if (r8a66597_read(r8a66597, INTSTS0) & VBSTS) {
  1471. r8a66597_start_xclock(r8a66597);
  1472. /* start vbus sampling */
  1473. r8a66597->old_vbus = r8a66597_read(r8a66597,
  1474. INTSTS0) & VBSTS;
  1475. r8a66597->scount = R8A66597_MAX_SAMPLING;
  1476. mod_timer(&r8a66597->timer, jiffies + msecs_to_jiffies(50));
  1477. }
  1478. return 0;
  1479. }
  1480. static int r8a66597_stop(struct usb_gadget *gadget)
  1481. {
  1482. struct r8a66597 *r8a66597 = gadget_to_r8a66597(gadget);
  1483. unsigned long flags;
  1484. spin_lock_irqsave(&r8a66597->lock, flags);
  1485. r8a66597_bclr(r8a66597, VBSE, INTENB0);
  1486. disable_controller(r8a66597);
  1487. spin_unlock_irqrestore(&r8a66597->lock, flags);
  1488. r8a66597->driver = NULL;
  1489. return 0;
  1490. }
  1491. /*-------------------------------------------------------------------------*/
  1492. static int r8a66597_get_frame(struct usb_gadget *_gadget)
  1493. {
  1494. struct r8a66597 *r8a66597 = gadget_to_r8a66597(_gadget);
  1495. return r8a66597_read(r8a66597, FRMNUM) & 0x03FF;
  1496. }
  1497. static int r8a66597_pullup(struct usb_gadget *gadget, int is_on)
  1498. {
  1499. struct r8a66597 *r8a66597 = gadget_to_r8a66597(gadget);
  1500. unsigned long flags;
  1501. spin_lock_irqsave(&r8a66597->lock, flags);
  1502. if (is_on)
  1503. r8a66597_bset(r8a66597, DPRPU, SYSCFG0);
  1504. else
  1505. r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
  1506. spin_unlock_irqrestore(&r8a66597->lock, flags);
  1507. return 0;
  1508. }
  1509. static int r8a66597_set_selfpowered(struct usb_gadget *gadget, int is_self)
  1510. {
  1511. struct r8a66597 *r8a66597 = gadget_to_r8a66597(gadget);
  1512. gadget->is_selfpowered = (is_self != 0);
  1513. if (is_self)
  1514. r8a66597->device_status |= 1 << USB_DEVICE_SELF_POWERED;
  1515. else
  1516. r8a66597->device_status &= ~(1 << USB_DEVICE_SELF_POWERED);
  1517. return 0;
  1518. }
  1519. static const struct usb_gadget_ops r8a66597_gadget_ops = {
  1520. .get_frame = r8a66597_get_frame,
  1521. .udc_start = r8a66597_start,
  1522. .udc_stop = r8a66597_stop,
  1523. .pullup = r8a66597_pullup,
  1524. .set_selfpowered = r8a66597_set_selfpowered,
  1525. };
  1526. static int r8a66597_remove(struct platform_device *pdev)
  1527. {
  1528. struct r8a66597 *r8a66597 = platform_get_drvdata(pdev);
  1529. usb_del_gadget_udc(&r8a66597->gadget);
  1530. del_timer_sync(&r8a66597->timer);
  1531. r8a66597_free_request(&r8a66597->ep[0].ep, r8a66597->ep0_req);
  1532. if (r8a66597->pdata->on_chip) {
  1533. clk_disable_unprepare(r8a66597->clk);
  1534. }
  1535. return 0;
  1536. }
  1537. static void nop_completion(struct usb_ep *ep, struct usb_request *r)
  1538. {
  1539. }
  1540. static int r8a66597_sudmac_ioremap(struct r8a66597 *r8a66597,
  1541. struct platform_device *pdev)
  1542. {
  1543. struct resource *res;
  1544. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sudmac");
  1545. r8a66597->sudmac_reg = devm_ioremap_resource(&pdev->dev, res);
  1546. return PTR_ERR_OR_ZERO(r8a66597->sudmac_reg);
  1547. }
  1548. static int r8a66597_probe(struct platform_device *pdev)
  1549. {
  1550. struct device *dev = &pdev->dev;
  1551. char clk_name[8];
  1552. struct resource *res, *ires;
  1553. int irq;
  1554. void __iomem *reg = NULL;
  1555. struct r8a66597 *r8a66597 = NULL;
  1556. int ret = 0;
  1557. int i;
  1558. unsigned long irq_trigger;
  1559. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1560. reg = devm_ioremap_resource(&pdev->dev, res);
  1561. if (IS_ERR(reg))
  1562. return PTR_ERR(reg);
  1563. ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1564. irq = ires->start;
  1565. irq_trigger = ires->flags & IRQF_TRIGGER_MASK;
  1566. if (irq < 0) {
  1567. dev_err(dev, "platform_get_irq error.\n");
  1568. return -ENODEV;
  1569. }
  1570. /* initialize ucd */
  1571. r8a66597 = devm_kzalloc(dev, sizeof(struct r8a66597), GFP_KERNEL);
  1572. if (r8a66597 == NULL)
  1573. return -ENOMEM;
  1574. spin_lock_init(&r8a66597->lock);
  1575. platform_set_drvdata(pdev, r8a66597);
  1576. r8a66597->pdata = dev_get_platdata(dev);
  1577. r8a66597->irq_sense_low = irq_trigger == IRQF_TRIGGER_LOW;
  1578. r8a66597->gadget.ops = &r8a66597_gadget_ops;
  1579. r8a66597->gadget.max_speed = USB_SPEED_HIGH;
  1580. r8a66597->gadget.name = udc_name;
  1581. timer_setup(&r8a66597->timer, r8a66597_timer, 0);
  1582. r8a66597->reg = reg;
  1583. if (r8a66597->pdata->on_chip) {
  1584. snprintf(clk_name, sizeof(clk_name), "usb%d", pdev->id);
  1585. r8a66597->clk = devm_clk_get(dev, clk_name);
  1586. if (IS_ERR(r8a66597->clk)) {
  1587. dev_err(dev, "cannot get clock \"%s\"\n", clk_name);
  1588. return PTR_ERR(r8a66597->clk);
  1589. }
  1590. clk_prepare_enable(r8a66597->clk);
  1591. }
  1592. if (r8a66597->pdata->sudmac) {
  1593. ret = r8a66597_sudmac_ioremap(r8a66597, pdev);
  1594. if (ret < 0)
  1595. goto clean_up2;
  1596. }
  1597. disable_controller(r8a66597); /* make sure controller is disabled */
  1598. ret = devm_request_irq(dev, irq, r8a66597_irq, IRQF_SHARED,
  1599. udc_name, r8a66597);
  1600. if (ret < 0) {
  1601. dev_err(dev, "request_irq error (%d)\n", ret);
  1602. goto clean_up2;
  1603. }
  1604. INIT_LIST_HEAD(&r8a66597->gadget.ep_list);
  1605. r8a66597->gadget.ep0 = &r8a66597->ep[0].ep;
  1606. INIT_LIST_HEAD(&r8a66597->gadget.ep0->ep_list);
  1607. for (i = 0; i < R8A66597_MAX_NUM_PIPE; i++) {
  1608. struct r8a66597_ep *ep = &r8a66597->ep[i];
  1609. if (i != 0) {
  1610. INIT_LIST_HEAD(&r8a66597->ep[i].ep.ep_list);
  1611. list_add_tail(&r8a66597->ep[i].ep.ep_list,
  1612. &r8a66597->gadget.ep_list);
  1613. }
  1614. ep->r8a66597 = r8a66597;
  1615. INIT_LIST_HEAD(&ep->queue);
  1616. ep->ep.name = r8a66597_ep_name[i];
  1617. ep->ep.ops = &r8a66597_ep_ops;
  1618. usb_ep_set_maxpacket_limit(&ep->ep, 512);
  1619. if (i == 0) {
  1620. ep->ep.caps.type_control = true;
  1621. } else {
  1622. ep->ep.caps.type_iso = true;
  1623. ep->ep.caps.type_bulk = true;
  1624. ep->ep.caps.type_int = true;
  1625. }
  1626. ep->ep.caps.dir_in = true;
  1627. ep->ep.caps.dir_out = true;
  1628. }
  1629. usb_ep_set_maxpacket_limit(&r8a66597->ep[0].ep, 64);
  1630. r8a66597->ep[0].pipenum = 0;
  1631. r8a66597->ep[0].fifoaddr = CFIFO;
  1632. r8a66597->ep[0].fifosel = CFIFOSEL;
  1633. r8a66597->ep[0].fifoctr = CFIFOCTR;
  1634. r8a66597->ep[0].pipectr = get_pipectr_addr(0);
  1635. r8a66597->pipenum2ep[0] = &r8a66597->ep[0];
  1636. r8a66597->epaddr2ep[0] = &r8a66597->ep[0];
  1637. r8a66597->ep0_req = r8a66597_alloc_request(&r8a66597->ep[0].ep,
  1638. GFP_KERNEL);
  1639. if (r8a66597->ep0_req == NULL) {
  1640. ret = -ENOMEM;
  1641. goto clean_up2;
  1642. }
  1643. r8a66597->ep0_req->complete = nop_completion;
  1644. ret = usb_add_gadget_udc(dev, &r8a66597->gadget);
  1645. if (ret)
  1646. goto err_add_udc;
  1647. dev_info(dev, "version %s\n", DRIVER_VERSION);
  1648. return 0;
  1649. err_add_udc:
  1650. r8a66597_free_request(&r8a66597->ep[0].ep, r8a66597->ep0_req);
  1651. clean_up2:
  1652. if (r8a66597->pdata->on_chip)
  1653. clk_disable_unprepare(r8a66597->clk);
  1654. if (r8a66597->ep0_req)
  1655. r8a66597_free_request(&r8a66597->ep[0].ep, r8a66597->ep0_req);
  1656. return ret;
  1657. }
  1658. /*-------------------------------------------------------------------------*/
  1659. static struct platform_driver r8a66597_driver = {
  1660. .remove = r8a66597_remove,
  1661. .driver = {
  1662. .name = (char *) udc_name,
  1663. },
  1664. };
  1665. module_platform_driver_probe(r8a66597_driver, r8a66597_probe);
  1666. MODULE_DESCRIPTION("R8A66597 USB gadget driver");
  1667. MODULE_LICENSE("GPL");
  1668. MODULE_AUTHOR("Yoshihiro Shimoda");
  1669. MODULE_ALIAS("platform:r8a66597_udc");