fsl_qe_udc.c 62 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * driver/usb/gadget/fsl_qe_udc.c
  4. *
  5. * Copyright (c) 2006-2008 Freescale Semiconductor, Inc. All rights reserved.
  6. *
  7. * Xie Xiaobo <X.Xie@freescale.com>
  8. * Li Yang <leoli@freescale.com>
  9. * Based on bareboard code from Shlomi Gridish.
  10. *
  11. * Description:
  12. * Freescle QE/CPM USB Pheripheral Controller Driver
  13. * The controller can be found on MPC8360, MPC8272, and etc.
  14. * MPC8360 Rev 1.1 may need QE mircocode update
  15. */
  16. #undef USB_TRACE
  17. #include <linux/module.h>
  18. #include <linux/kernel.h>
  19. #include <linux/ioport.h>
  20. #include <linux/types.h>
  21. #include <linux/errno.h>
  22. #include <linux/err.h>
  23. #include <linux/slab.h>
  24. #include <linux/list.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/io.h>
  27. #include <linux/moduleparam.h>
  28. #include <linux/of_address.h>
  29. #include <linux/of_irq.h>
  30. #include <linux/of_platform.h>
  31. #include <linux/dma-mapping.h>
  32. #include <linux/usb/ch9.h>
  33. #include <linux/usb/gadget.h>
  34. #include <linux/usb/otg.h>
  35. #include <soc/fsl/qe/qe.h>
  36. #include <asm/cpm.h>
  37. #include <asm/dma.h>
  38. #include <asm/reg.h>
  39. #include "fsl_qe_udc.h"
  40. #define DRIVER_DESC "Freescale QE/CPM USB Device Controller driver"
  41. #define DRIVER_AUTHOR "Xie XiaoBo"
  42. #define DRIVER_VERSION "1.0"
  43. #define DMA_ADDR_INVALID (~(dma_addr_t)0)
  44. static const char driver_name[] = "fsl_qe_udc";
  45. static const char driver_desc[] = DRIVER_DESC;
  46. /*ep name is important in gadget, it should obey the convention of ep_match()*/
  47. static const char *const ep_name[] = {
  48. "ep0-control", /* everyone has ep0 */
  49. /* 3 configurable endpoints */
  50. "ep1",
  51. "ep2",
  52. "ep3",
  53. };
  54. static const struct usb_endpoint_descriptor qe_ep0_desc = {
  55. .bLength = USB_DT_ENDPOINT_SIZE,
  56. .bDescriptorType = USB_DT_ENDPOINT,
  57. .bEndpointAddress = 0,
  58. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  59. .wMaxPacketSize = USB_MAX_CTRL_PAYLOAD,
  60. };
  61. /********************************************************************
  62. * Internal Used Function Start
  63. ********************************************************************/
  64. /*-----------------------------------------------------------------
  65. * done() - retire a request; caller blocked irqs
  66. *--------------------------------------------------------------*/
  67. static void done(struct qe_ep *ep, struct qe_req *req, int status)
  68. {
  69. struct qe_udc *udc = ep->udc;
  70. unsigned char stopped = ep->stopped;
  71. /* the req->queue pointer is used by ep_queue() func, in which
  72. * the request will be added into a udc_ep->queue 'd tail
  73. * so here the req will be dropped from the ep->queue
  74. */
  75. list_del_init(&req->queue);
  76. /* req.status should be set as -EINPROGRESS in ep_queue() */
  77. if (req->req.status == -EINPROGRESS)
  78. req->req.status = status;
  79. else
  80. status = req->req.status;
  81. if (req->mapped) {
  82. dma_unmap_single(udc->gadget.dev.parent,
  83. req->req.dma, req->req.length,
  84. ep_is_in(ep)
  85. ? DMA_TO_DEVICE
  86. : DMA_FROM_DEVICE);
  87. req->req.dma = DMA_ADDR_INVALID;
  88. req->mapped = 0;
  89. } else
  90. dma_sync_single_for_cpu(udc->gadget.dev.parent,
  91. req->req.dma, req->req.length,
  92. ep_is_in(ep)
  93. ? DMA_TO_DEVICE
  94. : DMA_FROM_DEVICE);
  95. if (status && (status != -ESHUTDOWN))
  96. dev_vdbg(udc->dev, "complete %s req %p stat %d len %u/%u\n",
  97. ep->ep.name, &req->req, status,
  98. req->req.actual, req->req.length);
  99. /* don't modify queue heads during completion callback */
  100. ep->stopped = 1;
  101. spin_unlock(&udc->lock);
  102. usb_gadget_giveback_request(&ep->ep, &req->req);
  103. spin_lock(&udc->lock);
  104. ep->stopped = stopped;
  105. }
  106. /*-----------------------------------------------------------------
  107. * nuke(): delete all requests related to this ep
  108. *--------------------------------------------------------------*/
  109. static void nuke(struct qe_ep *ep, int status)
  110. {
  111. /* Whether this eq has request linked */
  112. while (!list_empty(&ep->queue)) {
  113. struct qe_req *req = NULL;
  114. req = list_entry(ep->queue.next, struct qe_req, queue);
  115. done(ep, req, status);
  116. }
  117. }
  118. /*---------------------------------------------------------------------------*
  119. * USB and Endpoint manipulate process, include parameter and register *
  120. *---------------------------------------------------------------------------*/
  121. /* @value: 1--set stall 0--clean stall */
  122. static int qe_eprx_stall_change(struct qe_ep *ep, int value)
  123. {
  124. u16 tem_usep;
  125. u8 epnum = ep->epnum;
  126. struct qe_udc *udc = ep->udc;
  127. tem_usep = in_be16(&udc->usb_regs->usb_usep[epnum]);
  128. tem_usep = tem_usep & ~USB_RHS_MASK;
  129. if (value == 1)
  130. tem_usep |= USB_RHS_STALL;
  131. else if (ep->dir == USB_DIR_IN)
  132. tem_usep |= USB_RHS_IGNORE_OUT;
  133. out_be16(&udc->usb_regs->usb_usep[epnum], tem_usep);
  134. return 0;
  135. }
  136. static int qe_eptx_stall_change(struct qe_ep *ep, int value)
  137. {
  138. u16 tem_usep;
  139. u8 epnum = ep->epnum;
  140. struct qe_udc *udc = ep->udc;
  141. tem_usep = in_be16(&udc->usb_regs->usb_usep[epnum]);
  142. tem_usep = tem_usep & ~USB_THS_MASK;
  143. if (value == 1)
  144. tem_usep |= USB_THS_STALL;
  145. else if (ep->dir == USB_DIR_OUT)
  146. tem_usep |= USB_THS_IGNORE_IN;
  147. out_be16(&udc->usb_regs->usb_usep[epnum], tem_usep);
  148. return 0;
  149. }
  150. static int qe_ep0_stall(struct qe_udc *udc)
  151. {
  152. qe_eptx_stall_change(&udc->eps[0], 1);
  153. qe_eprx_stall_change(&udc->eps[0], 1);
  154. udc->ep0_state = WAIT_FOR_SETUP;
  155. udc->ep0_dir = 0;
  156. return 0;
  157. }
  158. static int qe_eprx_nack(struct qe_ep *ep)
  159. {
  160. u8 epnum = ep->epnum;
  161. struct qe_udc *udc = ep->udc;
  162. if (ep->state == EP_STATE_IDLE) {
  163. /* Set the ep's nack */
  164. clrsetbits_be16(&udc->usb_regs->usb_usep[epnum],
  165. USB_RHS_MASK, USB_RHS_NACK);
  166. /* Mask Rx and Busy interrupts */
  167. clrbits16(&udc->usb_regs->usb_usbmr,
  168. (USB_E_RXB_MASK | USB_E_BSY_MASK));
  169. ep->state = EP_STATE_NACK;
  170. }
  171. return 0;
  172. }
  173. static int qe_eprx_normal(struct qe_ep *ep)
  174. {
  175. struct qe_udc *udc = ep->udc;
  176. if (ep->state == EP_STATE_NACK) {
  177. clrsetbits_be16(&udc->usb_regs->usb_usep[ep->epnum],
  178. USB_RTHS_MASK, USB_THS_IGNORE_IN);
  179. /* Unmask RX interrupts */
  180. out_be16(&udc->usb_regs->usb_usber,
  181. USB_E_BSY_MASK | USB_E_RXB_MASK);
  182. setbits16(&udc->usb_regs->usb_usbmr,
  183. (USB_E_RXB_MASK | USB_E_BSY_MASK));
  184. ep->state = EP_STATE_IDLE;
  185. ep->has_data = 0;
  186. }
  187. return 0;
  188. }
  189. static int qe_ep_cmd_stoptx(struct qe_ep *ep)
  190. {
  191. if (ep->udc->soc_type == PORT_CPM)
  192. cpm_command(CPM_USB_STOP_TX | (ep->epnum << CPM_USB_EP_SHIFT),
  193. CPM_USB_STOP_TX_OPCODE);
  194. else
  195. qe_issue_cmd(QE_USB_STOP_TX, QE_CR_SUBBLOCK_USB,
  196. ep->epnum, 0);
  197. return 0;
  198. }
  199. static int qe_ep_cmd_restarttx(struct qe_ep *ep)
  200. {
  201. if (ep->udc->soc_type == PORT_CPM)
  202. cpm_command(CPM_USB_RESTART_TX | (ep->epnum <<
  203. CPM_USB_EP_SHIFT), CPM_USB_RESTART_TX_OPCODE);
  204. else
  205. qe_issue_cmd(QE_USB_RESTART_TX, QE_CR_SUBBLOCK_USB,
  206. ep->epnum, 0);
  207. return 0;
  208. }
  209. static int qe_ep_flushtxfifo(struct qe_ep *ep)
  210. {
  211. struct qe_udc *udc = ep->udc;
  212. int i;
  213. i = (int)ep->epnum;
  214. qe_ep_cmd_stoptx(ep);
  215. out_8(&udc->usb_regs->usb_uscom,
  216. USB_CMD_FLUSH_FIFO | (USB_CMD_EP_MASK & (ep->epnum)));
  217. out_be16(&udc->ep_param[i]->tbptr, in_be16(&udc->ep_param[i]->tbase));
  218. out_be32(&udc->ep_param[i]->tstate, 0);
  219. out_be16(&udc->ep_param[i]->tbcnt, 0);
  220. ep->c_txbd = ep->txbase;
  221. ep->n_txbd = ep->txbase;
  222. qe_ep_cmd_restarttx(ep);
  223. return 0;
  224. }
  225. static int qe_ep_filltxfifo(struct qe_ep *ep)
  226. {
  227. struct qe_udc *udc = ep->udc;
  228. out_8(&udc->usb_regs->usb_uscom,
  229. USB_CMD_STR_FIFO | (USB_CMD_EP_MASK & (ep->epnum)));
  230. return 0;
  231. }
  232. static int qe_epbds_reset(struct qe_udc *udc, int pipe_num)
  233. {
  234. struct qe_ep *ep;
  235. u32 bdring_len;
  236. struct qe_bd __iomem *bd;
  237. int i;
  238. ep = &udc->eps[pipe_num];
  239. if (ep->dir == USB_DIR_OUT)
  240. bdring_len = USB_BDRING_LEN_RX;
  241. else
  242. bdring_len = USB_BDRING_LEN;
  243. bd = ep->rxbase;
  244. for (i = 0; i < (bdring_len - 1); i++) {
  245. out_be32((u32 __iomem *)bd, R_E | R_I);
  246. bd++;
  247. }
  248. out_be32((u32 __iomem *)bd, R_E | R_I | R_W);
  249. bd = ep->txbase;
  250. for (i = 0; i < USB_BDRING_LEN_TX - 1; i++) {
  251. out_be32(&bd->buf, 0);
  252. out_be32((u32 __iomem *)bd, 0);
  253. bd++;
  254. }
  255. out_be32((u32 __iomem *)bd, T_W);
  256. return 0;
  257. }
  258. static int qe_ep_reset(struct qe_udc *udc, int pipe_num)
  259. {
  260. struct qe_ep *ep;
  261. u16 tmpusep;
  262. ep = &udc->eps[pipe_num];
  263. tmpusep = in_be16(&udc->usb_regs->usb_usep[pipe_num]);
  264. tmpusep &= ~USB_RTHS_MASK;
  265. switch (ep->dir) {
  266. case USB_DIR_BOTH:
  267. qe_ep_flushtxfifo(ep);
  268. break;
  269. case USB_DIR_OUT:
  270. tmpusep |= USB_THS_IGNORE_IN;
  271. break;
  272. case USB_DIR_IN:
  273. qe_ep_flushtxfifo(ep);
  274. tmpusep |= USB_RHS_IGNORE_OUT;
  275. break;
  276. default:
  277. break;
  278. }
  279. out_be16(&udc->usb_regs->usb_usep[pipe_num], tmpusep);
  280. qe_epbds_reset(udc, pipe_num);
  281. return 0;
  282. }
  283. static int qe_ep_toggledata01(struct qe_ep *ep)
  284. {
  285. ep->data01 ^= 0x1;
  286. return 0;
  287. }
  288. static int qe_ep_bd_init(struct qe_udc *udc, unsigned char pipe_num)
  289. {
  290. struct qe_ep *ep = &udc->eps[pipe_num];
  291. unsigned long tmp_addr = 0;
  292. struct usb_ep_para __iomem *epparam;
  293. int i;
  294. struct qe_bd __iomem *bd;
  295. int bdring_len;
  296. if (ep->dir == USB_DIR_OUT)
  297. bdring_len = USB_BDRING_LEN_RX;
  298. else
  299. bdring_len = USB_BDRING_LEN;
  300. epparam = udc->ep_param[pipe_num];
  301. /* alloc multi-ram for BD rings and set the ep parameters */
  302. tmp_addr = cpm_muram_alloc(sizeof(struct qe_bd) * (bdring_len +
  303. USB_BDRING_LEN_TX), QE_ALIGNMENT_OF_BD);
  304. if (IS_ERR_VALUE(tmp_addr))
  305. return -ENOMEM;
  306. out_be16(&epparam->rbase, (u16)tmp_addr);
  307. out_be16(&epparam->tbase, (u16)(tmp_addr +
  308. (sizeof(struct qe_bd) * bdring_len)));
  309. out_be16(&epparam->rbptr, in_be16(&epparam->rbase));
  310. out_be16(&epparam->tbptr, in_be16(&epparam->tbase));
  311. ep->rxbase = cpm_muram_addr(tmp_addr);
  312. ep->txbase = cpm_muram_addr(tmp_addr + (sizeof(struct qe_bd)
  313. * bdring_len));
  314. ep->n_rxbd = ep->rxbase;
  315. ep->e_rxbd = ep->rxbase;
  316. ep->n_txbd = ep->txbase;
  317. ep->c_txbd = ep->txbase;
  318. ep->data01 = 0; /* data0 */
  319. /* Init TX and RX bds */
  320. bd = ep->rxbase;
  321. for (i = 0; i < bdring_len - 1; i++) {
  322. out_be32(&bd->buf, 0);
  323. out_be32((u32 __iomem *)bd, 0);
  324. bd++;
  325. }
  326. out_be32(&bd->buf, 0);
  327. out_be32((u32 __iomem *)bd, R_W);
  328. bd = ep->txbase;
  329. for (i = 0; i < USB_BDRING_LEN_TX - 1; i++) {
  330. out_be32(&bd->buf, 0);
  331. out_be32((u32 __iomem *)bd, 0);
  332. bd++;
  333. }
  334. out_be32(&bd->buf, 0);
  335. out_be32((u32 __iomem *)bd, T_W);
  336. return 0;
  337. }
  338. static int qe_ep_rxbd_update(struct qe_ep *ep)
  339. {
  340. unsigned int size;
  341. int i;
  342. unsigned int tmp;
  343. struct qe_bd __iomem *bd;
  344. unsigned int bdring_len;
  345. if (ep->rxbase == NULL)
  346. return -EINVAL;
  347. bd = ep->rxbase;
  348. ep->rxframe = kmalloc(sizeof(*ep->rxframe), GFP_ATOMIC);
  349. if (!ep->rxframe)
  350. return -ENOMEM;
  351. qe_frame_init(ep->rxframe);
  352. if (ep->dir == USB_DIR_OUT)
  353. bdring_len = USB_BDRING_LEN_RX;
  354. else
  355. bdring_len = USB_BDRING_LEN;
  356. size = (ep->ep.maxpacket + USB_CRC_SIZE + 2) * (bdring_len + 1);
  357. ep->rxbuffer = kzalloc(size, GFP_ATOMIC);
  358. if (!ep->rxbuffer) {
  359. kfree(ep->rxframe);
  360. return -ENOMEM;
  361. }
  362. ep->rxbuf_d = virt_to_phys((void *)ep->rxbuffer);
  363. if (ep->rxbuf_d == DMA_ADDR_INVALID) {
  364. ep->rxbuf_d = dma_map_single(ep->udc->gadget.dev.parent,
  365. ep->rxbuffer,
  366. size,
  367. DMA_FROM_DEVICE);
  368. ep->rxbufmap = 1;
  369. } else {
  370. dma_sync_single_for_device(ep->udc->gadget.dev.parent,
  371. ep->rxbuf_d, size,
  372. DMA_FROM_DEVICE);
  373. ep->rxbufmap = 0;
  374. }
  375. size = ep->ep.maxpacket + USB_CRC_SIZE + 2;
  376. tmp = ep->rxbuf_d;
  377. tmp = (u32)(((tmp >> 2) << 2) + 4);
  378. for (i = 0; i < bdring_len - 1; i++) {
  379. out_be32(&bd->buf, tmp);
  380. out_be32((u32 __iomem *)bd, (R_E | R_I));
  381. tmp = tmp + size;
  382. bd++;
  383. }
  384. out_be32(&bd->buf, tmp);
  385. out_be32((u32 __iomem *)bd, (R_E | R_I | R_W));
  386. return 0;
  387. }
  388. static int qe_ep_register_init(struct qe_udc *udc, unsigned char pipe_num)
  389. {
  390. struct qe_ep *ep = &udc->eps[pipe_num];
  391. struct usb_ep_para __iomem *epparam;
  392. u16 usep, logepnum;
  393. u16 tmp;
  394. u8 rtfcr = 0;
  395. epparam = udc->ep_param[pipe_num];
  396. usep = 0;
  397. logepnum = (ep->ep.desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK);
  398. usep |= (logepnum << USB_EPNUM_SHIFT);
  399. switch (ep->ep.desc->bmAttributes & 0x03) {
  400. case USB_ENDPOINT_XFER_BULK:
  401. usep |= USB_TRANS_BULK;
  402. break;
  403. case USB_ENDPOINT_XFER_ISOC:
  404. usep |= USB_TRANS_ISO;
  405. break;
  406. case USB_ENDPOINT_XFER_INT:
  407. usep |= USB_TRANS_INT;
  408. break;
  409. default:
  410. usep |= USB_TRANS_CTR;
  411. break;
  412. }
  413. switch (ep->dir) {
  414. case USB_DIR_OUT:
  415. usep |= USB_THS_IGNORE_IN;
  416. break;
  417. case USB_DIR_IN:
  418. usep |= USB_RHS_IGNORE_OUT;
  419. break;
  420. default:
  421. break;
  422. }
  423. out_be16(&udc->usb_regs->usb_usep[pipe_num], usep);
  424. rtfcr = 0x30;
  425. out_8(&epparam->rbmr, rtfcr);
  426. out_8(&epparam->tbmr, rtfcr);
  427. tmp = (u16)(ep->ep.maxpacket + USB_CRC_SIZE);
  428. /* MRBLR must be divisble by 4 */
  429. tmp = (u16)(((tmp >> 2) << 2) + 4);
  430. out_be16(&epparam->mrblr, tmp);
  431. return 0;
  432. }
  433. static int qe_ep_init(struct qe_udc *udc,
  434. unsigned char pipe_num,
  435. const struct usb_endpoint_descriptor *desc)
  436. {
  437. struct qe_ep *ep = &udc->eps[pipe_num];
  438. unsigned long flags;
  439. int reval = 0;
  440. u16 max = 0;
  441. max = usb_endpoint_maxp(desc);
  442. /* check the max package size validate for this endpoint */
  443. /* Refer to USB2.0 spec table 9-13,
  444. */
  445. if (pipe_num != 0) {
  446. switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
  447. case USB_ENDPOINT_XFER_BULK:
  448. if (strstr(ep->ep.name, "-iso")
  449. || strstr(ep->ep.name, "-int"))
  450. goto en_done;
  451. switch (udc->gadget.speed) {
  452. case USB_SPEED_HIGH:
  453. if ((max == 128) || (max == 256) || (max == 512))
  454. break;
  455. default:
  456. switch (max) {
  457. case 4:
  458. case 8:
  459. case 16:
  460. case 32:
  461. case 64:
  462. break;
  463. default:
  464. case USB_SPEED_LOW:
  465. goto en_done;
  466. }
  467. }
  468. break;
  469. case USB_ENDPOINT_XFER_INT:
  470. if (strstr(ep->ep.name, "-iso")) /* bulk is ok */
  471. goto en_done;
  472. switch (udc->gadget.speed) {
  473. case USB_SPEED_HIGH:
  474. if (max <= 1024)
  475. break;
  476. case USB_SPEED_FULL:
  477. if (max <= 64)
  478. break;
  479. default:
  480. if (max <= 8)
  481. break;
  482. goto en_done;
  483. }
  484. break;
  485. case USB_ENDPOINT_XFER_ISOC:
  486. if (strstr(ep->ep.name, "-bulk")
  487. || strstr(ep->ep.name, "-int"))
  488. goto en_done;
  489. switch (udc->gadget.speed) {
  490. case USB_SPEED_HIGH:
  491. if (max <= 1024)
  492. break;
  493. case USB_SPEED_FULL:
  494. if (max <= 1023)
  495. break;
  496. default:
  497. goto en_done;
  498. }
  499. break;
  500. case USB_ENDPOINT_XFER_CONTROL:
  501. if (strstr(ep->ep.name, "-iso")
  502. || strstr(ep->ep.name, "-int"))
  503. goto en_done;
  504. switch (udc->gadget.speed) {
  505. case USB_SPEED_HIGH:
  506. case USB_SPEED_FULL:
  507. switch (max) {
  508. case 1:
  509. case 2:
  510. case 4:
  511. case 8:
  512. case 16:
  513. case 32:
  514. case 64:
  515. break;
  516. default:
  517. goto en_done;
  518. }
  519. case USB_SPEED_LOW:
  520. switch (max) {
  521. case 1:
  522. case 2:
  523. case 4:
  524. case 8:
  525. break;
  526. default:
  527. goto en_done;
  528. }
  529. default:
  530. goto en_done;
  531. }
  532. break;
  533. default:
  534. goto en_done;
  535. }
  536. } /* if ep0*/
  537. spin_lock_irqsave(&udc->lock, flags);
  538. /* initialize ep structure */
  539. ep->ep.maxpacket = max;
  540. ep->tm = (u8)(desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK);
  541. ep->ep.desc = desc;
  542. ep->stopped = 0;
  543. ep->init = 1;
  544. if (pipe_num == 0) {
  545. ep->dir = USB_DIR_BOTH;
  546. udc->ep0_dir = USB_DIR_OUT;
  547. udc->ep0_state = WAIT_FOR_SETUP;
  548. } else {
  549. switch (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) {
  550. case USB_DIR_OUT:
  551. ep->dir = USB_DIR_OUT;
  552. break;
  553. case USB_DIR_IN:
  554. ep->dir = USB_DIR_IN;
  555. default:
  556. break;
  557. }
  558. }
  559. /* hardware special operation */
  560. qe_ep_bd_init(udc, pipe_num);
  561. if ((ep->tm == USBP_TM_CTL) || (ep->dir == USB_DIR_OUT)) {
  562. reval = qe_ep_rxbd_update(ep);
  563. if (reval)
  564. goto en_done1;
  565. }
  566. if ((ep->tm == USBP_TM_CTL) || (ep->dir == USB_DIR_IN)) {
  567. ep->txframe = kmalloc(sizeof(*ep->txframe), GFP_ATOMIC);
  568. if (!ep->txframe)
  569. goto en_done2;
  570. qe_frame_init(ep->txframe);
  571. }
  572. qe_ep_register_init(udc, pipe_num);
  573. /* Now HW will be NAKing transfers to that EP,
  574. * until a buffer is queued to it. */
  575. spin_unlock_irqrestore(&udc->lock, flags);
  576. return 0;
  577. en_done2:
  578. kfree(ep->rxbuffer);
  579. kfree(ep->rxframe);
  580. en_done1:
  581. spin_unlock_irqrestore(&udc->lock, flags);
  582. en_done:
  583. dev_err(udc->dev, "failed to initialize %s\n", ep->ep.name);
  584. return -ENODEV;
  585. }
  586. static inline void qe_usb_enable(struct qe_udc *udc)
  587. {
  588. setbits8(&udc->usb_regs->usb_usmod, USB_MODE_EN);
  589. }
  590. static inline void qe_usb_disable(struct qe_udc *udc)
  591. {
  592. clrbits8(&udc->usb_regs->usb_usmod, USB_MODE_EN);
  593. }
  594. /*----------------------------------------------------------------------------*
  595. * USB and EP basic manipulate function end *
  596. *----------------------------------------------------------------------------*/
  597. /******************************************************************************
  598. UDC transmit and receive process
  599. ******************************************************************************/
  600. static void recycle_one_rxbd(struct qe_ep *ep)
  601. {
  602. u32 bdstatus;
  603. bdstatus = in_be32((u32 __iomem *)ep->e_rxbd);
  604. bdstatus = R_I | R_E | (bdstatus & R_W);
  605. out_be32((u32 __iomem *)ep->e_rxbd, bdstatus);
  606. if (bdstatus & R_W)
  607. ep->e_rxbd = ep->rxbase;
  608. else
  609. ep->e_rxbd++;
  610. }
  611. static void recycle_rxbds(struct qe_ep *ep, unsigned char stopatnext)
  612. {
  613. u32 bdstatus;
  614. struct qe_bd __iomem *bd, *nextbd;
  615. unsigned char stop = 0;
  616. nextbd = ep->n_rxbd;
  617. bd = ep->e_rxbd;
  618. bdstatus = in_be32((u32 __iomem *)bd);
  619. while (!(bdstatus & R_E) && !(bdstatus & BD_LENGTH_MASK) && !stop) {
  620. bdstatus = R_E | R_I | (bdstatus & R_W);
  621. out_be32((u32 __iomem *)bd, bdstatus);
  622. if (bdstatus & R_W)
  623. bd = ep->rxbase;
  624. else
  625. bd++;
  626. bdstatus = in_be32((u32 __iomem *)bd);
  627. if (stopatnext && (bd == nextbd))
  628. stop = 1;
  629. }
  630. ep->e_rxbd = bd;
  631. }
  632. static void ep_recycle_rxbds(struct qe_ep *ep)
  633. {
  634. struct qe_bd __iomem *bd = ep->n_rxbd;
  635. u32 bdstatus;
  636. u8 epnum = ep->epnum;
  637. struct qe_udc *udc = ep->udc;
  638. bdstatus = in_be32((u32 __iomem *)bd);
  639. if (!(bdstatus & R_E) && !(bdstatus & BD_LENGTH_MASK)) {
  640. bd = ep->rxbase +
  641. ((in_be16(&udc->ep_param[epnum]->rbptr) -
  642. in_be16(&udc->ep_param[epnum]->rbase))
  643. >> 3);
  644. bdstatus = in_be32((u32 __iomem *)bd);
  645. if (bdstatus & R_W)
  646. bd = ep->rxbase;
  647. else
  648. bd++;
  649. ep->e_rxbd = bd;
  650. recycle_rxbds(ep, 0);
  651. ep->e_rxbd = ep->n_rxbd;
  652. } else
  653. recycle_rxbds(ep, 1);
  654. if (in_be16(&udc->usb_regs->usb_usber) & USB_E_BSY_MASK)
  655. out_be16(&udc->usb_regs->usb_usber, USB_E_BSY_MASK);
  656. if (ep->has_data <= 0 && (!list_empty(&ep->queue)))
  657. qe_eprx_normal(ep);
  658. ep->localnack = 0;
  659. }
  660. static void setup_received_handle(struct qe_udc *udc,
  661. struct usb_ctrlrequest *setup);
  662. static int qe_ep_rxframe_handle(struct qe_ep *ep);
  663. static void ep0_req_complete(struct qe_udc *udc, struct qe_req *req);
  664. /* when BD PID is setup, handle the packet */
  665. static int ep0_setup_handle(struct qe_udc *udc)
  666. {
  667. struct qe_ep *ep = &udc->eps[0];
  668. struct qe_frame *pframe;
  669. unsigned int fsize;
  670. u8 *cp;
  671. pframe = ep->rxframe;
  672. if ((frame_get_info(pframe) & PID_SETUP)
  673. && (udc->ep0_state == WAIT_FOR_SETUP)) {
  674. fsize = frame_get_length(pframe);
  675. if (unlikely(fsize != 8))
  676. return -EINVAL;
  677. cp = (u8 *)&udc->local_setup_buff;
  678. memcpy(cp, pframe->data, fsize);
  679. ep->data01 = 1;
  680. /* handle the usb command base on the usb_ctrlrequest */
  681. setup_received_handle(udc, &udc->local_setup_buff);
  682. return 0;
  683. }
  684. return -EINVAL;
  685. }
  686. static int qe_ep0_rx(struct qe_udc *udc)
  687. {
  688. struct qe_ep *ep = &udc->eps[0];
  689. struct qe_frame *pframe;
  690. struct qe_bd __iomem *bd;
  691. u32 bdstatus, length;
  692. u32 vaddr;
  693. pframe = ep->rxframe;
  694. if (ep->dir == USB_DIR_IN) {
  695. dev_err(udc->dev, "ep0 not a control endpoint\n");
  696. return -EINVAL;
  697. }
  698. bd = ep->n_rxbd;
  699. bdstatus = in_be32((u32 __iomem *)bd);
  700. length = bdstatus & BD_LENGTH_MASK;
  701. while (!(bdstatus & R_E) && length) {
  702. if ((bdstatus & R_F) && (bdstatus & R_L)
  703. && !(bdstatus & R_ERROR)) {
  704. if (length == USB_CRC_SIZE) {
  705. udc->ep0_state = WAIT_FOR_SETUP;
  706. dev_vdbg(udc->dev,
  707. "receive a ZLP in status phase\n");
  708. } else {
  709. qe_frame_clean(pframe);
  710. vaddr = (u32)phys_to_virt(in_be32(&bd->buf));
  711. frame_set_data(pframe, (u8 *)vaddr);
  712. frame_set_length(pframe,
  713. (length - USB_CRC_SIZE));
  714. frame_set_status(pframe, FRAME_OK);
  715. switch (bdstatus & R_PID) {
  716. case R_PID_SETUP:
  717. frame_set_info(pframe, PID_SETUP);
  718. break;
  719. case R_PID_DATA1:
  720. frame_set_info(pframe, PID_DATA1);
  721. break;
  722. default:
  723. frame_set_info(pframe, PID_DATA0);
  724. break;
  725. }
  726. if ((bdstatus & R_PID) == R_PID_SETUP)
  727. ep0_setup_handle(udc);
  728. else
  729. qe_ep_rxframe_handle(ep);
  730. }
  731. } else {
  732. dev_err(udc->dev, "The receive frame with error!\n");
  733. }
  734. /* note: don't clear the rxbd's buffer address */
  735. recycle_one_rxbd(ep);
  736. /* Get next BD */
  737. if (bdstatus & R_W)
  738. bd = ep->rxbase;
  739. else
  740. bd++;
  741. bdstatus = in_be32((u32 __iomem *)bd);
  742. length = bdstatus & BD_LENGTH_MASK;
  743. }
  744. ep->n_rxbd = bd;
  745. return 0;
  746. }
  747. static int qe_ep_rxframe_handle(struct qe_ep *ep)
  748. {
  749. struct qe_frame *pframe;
  750. u8 framepid = 0;
  751. unsigned int fsize;
  752. u8 *cp;
  753. struct qe_req *req;
  754. pframe = ep->rxframe;
  755. if (frame_get_info(pframe) & PID_DATA1)
  756. framepid = 0x1;
  757. if (framepid != ep->data01) {
  758. dev_err(ep->udc->dev, "the data01 error!\n");
  759. return -EIO;
  760. }
  761. fsize = frame_get_length(pframe);
  762. if (list_empty(&ep->queue)) {
  763. dev_err(ep->udc->dev, "the %s have no requeue!\n", ep->name);
  764. } else {
  765. req = list_entry(ep->queue.next, struct qe_req, queue);
  766. cp = (u8 *)(req->req.buf) + req->req.actual;
  767. if (cp) {
  768. memcpy(cp, pframe->data, fsize);
  769. req->req.actual += fsize;
  770. if ((fsize < ep->ep.maxpacket) ||
  771. (req->req.actual >= req->req.length)) {
  772. if (ep->epnum == 0)
  773. ep0_req_complete(ep->udc, req);
  774. else
  775. done(ep, req, 0);
  776. if (list_empty(&ep->queue) && ep->epnum != 0)
  777. qe_eprx_nack(ep);
  778. }
  779. }
  780. }
  781. qe_ep_toggledata01(ep);
  782. return 0;
  783. }
  784. static void ep_rx_tasklet(unsigned long data)
  785. {
  786. struct qe_udc *udc = (struct qe_udc *)data;
  787. struct qe_ep *ep;
  788. struct qe_frame *pframe;
  789. struct qe_bd __iomem *bd;
  790. unsigned long flags;
  791. u32 bdstatus, length;
  792. u32 vaddr, i;
  793. spin_lock_irqsave(&udc->lock, flags);
  794. for (i = 1; i < USB_MAX_ENDPOINTS; i++) {
  795. ep = &udc->eps[i];
  796. if (ep->dir == USB_DIR_IN || ep->enable_tasklet == 0) {
  797. dev_dbg(udc->dev,
  798. "This is a transmit ep or disable tasklet!\n");
  799. continue;
  800. }
  801. pframe = ep->rxframe;
  802. bd = ep->n_rxbd;
  803. bdstatus = in_be32((u32 __iomem *)bd);
  804. length = bdstatus & BD_LENGTH_MASK;
  805. while (!(bdstatus & R_E) && length) {
  806. if (list_empty(&ep->queue)) {
  807. qe_eprx_nack(ep);
  808. dev_dbg(udc->dev,
  809. "The rxep have noreq %d\n",
  810. ep->has_data);
  811. break;
  812. }
  813. if ((bdstatus & R_F) && (bdstatus & R_L)
  814. && !(bdstatus & R_ERROR)) {
  815. qe_frame_clean(pframe);
  816. vaddr = (u32)phys_to_virt(in_be32(&bd->buf));
  817. frame_set_data(pframe, (u8 *)vaddr);
  818. frame_set_length(pframe,
  819. (length - USB_CRC_SIZE));
  820. frame_set_status(pframe, FRAME_OK);
  821. switch (bdstatus & R_PID) {
  822. case R_PID_DATA1:
  823. frame_set_info(pframe, PID_DATA1);
  824. break;
  825. case R_PID_SETUP:
  826. frame_set_info(pframe, PID_SETUP);
  827. break;
  828. default:
  829. frame_set_info(pframe, PID_DATA0);
  830. break;
  831. }
  832. /* handle the rx frame */
  833. qe_ep_rxframe_handle(ep);
  834. } else {
  835. dev_err(udc->dev,
  836. "error in received frame\n");
  837. }
  838. /* note: don't clear the rxbd's buffer address */
  839. /*clear the length */
  840. out_be32((u32 __iomem *)bd, bdstatus & BD_STATUS_MASK);
  841. ep->has_data--;
  842. if (!(ep->localnack))
  843. recycle_one_rxbd(ep);
  844. /* Get next BD */
  845. if (bdstatus & R_W)
  846. bd = ep->rxbase;
  847. else
  848. bd++;
  849. bdstatus = in_be32((u32 __iomem *)bd);
  850. length = bdstatus & BD_LENGTH_MASK;
  851. }
  852. ep->n_rxbd = bd;
  853. if (ep->localnack)
  854. ep_recycle_rxbds(ep);
  855. ep->enable_tasklet = 0;
  856. } /* for i=1 */
  857. spin_unlock_irqrestore(&udc->lock, flags);
  858. }
  859. static int qe_ep_rx(struct qe_ep *ep)
  860. {
  861. struct qe_udc *udc;
  862. struct qe_frame *pframe;
  863. struct qe_bd __iomem *bd;
  864. u16 swoffs, ucoffs, emptybds;
  865. udc = ep->udc;
  866. pframe = ep->rxframe;
  867. if (ep->dir == USB_DIR_IN) {
  868. dev_err(udc->dev, "transmit ep in rx function\n");
  869. return -EINVAL;
  870. }
  871. bd = ep->n_rxbd;
  872. swoffs = (u16)(bd - ep->rxbase);
  873. ucoffs = (u16)((in_be16(&udc->ep_param[ep->epnum]->rbptr) -
  874. in_be16(&udc->ep_param[ep->epnum]->rbase)) >> 3);
  875. if (swoffs < ucoffs)
  876. emptybds = USB_BDRING_LEN_RX - ucoffs + swoffs;
  877. else
  878. emptybds = swoffs - ucoffs;
  879. if (emptybds < MIN_EMPTY_BDS) {
  880. qe_eprx_nack(ep);
  881. ep->localnack = 1;
  882. dev_vdbg(udc->dev, "%d empty bds, send NACK\n", emptybds);
  883. }
  884. ep->has_data = USB_BDRING_LEN_RX - emptybds;
  885. if (list_empty(&ep->queue)) {
  886. qe_eprx_nack(ep);
  887. dev_vdbg(udc->dev, "The rxep have no req queued with %d BDs\n",
  888. ep->has_data);
  889. return 0;
  890. }
  891. tasklet_schedule(&udc->rx_tasklet);
  892. ep->enable_tasklet = 1;
  893. return 0;
  894. }
  895. /* send data from a frame, no matter what tx_req */
  896. static int qe_ep_tx(struct qe_ep *ep, struct qe_frame *frame)
  897. {
  898. struct qe_udc *udc = ep->udc;
  899. struct qe_bd __iomem *bd;
  900. u16 saveusbmr;
  901. u32 bdstatus, pidmask;
  902. u32 paddr;
  903. if (ep->dir == USB_DIR_OUT) {
  904. dev_err(udc->dev, "receive ep passed to tx function\n");
  905. return -EINVAL;
  906. }
  907. /* Disable the Tx interrupt */
  908. saveusbmr = in_be16(&udc->usb_regs->usb_usbmr);
  909. out_be16(&udc->usb_regs->usb_usbmr,
  910. saveusbmr & ~(USB_E_TXB_MASK | USB_E_TXE_MASK));
  911. bd = ep->n_txbd;
  912. bdstatus = in_be32((u32 __iomem *)bd);
  913. if (!(bdstatus & (T_R | BD_LENGTH_MASK))) {
  914. if (frame_get_length(frame) == 0) {
  915. frame_set_data(frame, udc->nullbuf);
  916. frame_set_length(frame, 2);
  917. frame->info |= (ZLP | NO_CRC);
  918. dev_vdbg(udc->dev, "the frame size = 0\n");
  919. }
  920. paddr = virt_to_phys((void *)frame->data);
  921. out_be32(&bd->buf, paddr);
  922. bdstatus = (bdstatus&T_W);
  923. if (!(frame_get_info(frame) & NO_CRC))
  924. bdstatus |= T_R | T_I | T_L | T_TC
  925. | frame_get_length(frame);
  926. else
  927. bdstatus |= T_R | T_I | T_L | frame_get_length(frame);
  928. /* if the packet is a ZLP in status phase */
  929. if ((ep->epnum == 0) && (udc->ep0_state == DATA_STATE_NEED_ZLP))
  930. ep->data01 = 0x1;
  931. if (ep->data01) {
  932. pidmask = T_PID_DATA1;
  933. frame->info |= PID_DATA1;
  934. } else {
  935. pidmask = T_PID_DATA0;
  936. frame->info |= PID_DATA0;
  937. }
  938. bdstatus |= T_CNF;
  939. bdstatus |= pidmask;
  940. out_be32((u32 __iomem *)bd, bdstatus);
  941. qe_ep_filltxfifo(ep);
  942. /* enable the TX interrupt */
  943. out_be16(&udc->usb_regs->usb_usbmr, saveusbmr);
  944. qe_ep_toggledata01(ep);
  945. if (bdstatus & T_W)
  946. ep->n_txbd = ep->txbase;
  947. else
  948. ep->n_txbd++;
  949. return 0;
  950. } else {
  951. out_be16(&udc->usb_regs->usb_usbmr, saveusbmr);
  952. dev_vdbg(udc->dev, "The tx bd is not ready!\n");
  953. return -EBUSY;
  954. }
  955. }
  956. /* when a bd was transmitted, the function can
  957. * handle the tx_req, not include ep0 */
  958. static int txcomplete(struct qe_ep *ep, unsigned char restart)
  959. {
  960. if (ep->tx_req != NULL) {
  961. struct qe_req *req = ep->tx_req;
  962. unsigned zlp = 0, last_len = 0;
  963. last_len = min_t(unsigned, req->req.length - ep->sent,
  964. ep->ep.maxpacket);
  965. if (!restart) {
  966. int asent = ep->last;
  967. ep->sent += asent;
  968. ep->last -= asent;
  969. } else {
  970. ep->last = 0;
  971. }
  972. /* zlp needed when req->re.zero is set */
  973. if (req->req.zero) {
  974. if (last_len == 0 ||
  975. (req->req.length % ep->ep.maxpacket) != 0)
  976. zlp = 0;
  977. else
  978. zlp = 1;
  979. } else
  980. zlp = 0;
  981. /* a request already were transmitted completely */
  982. if (((ep->tx_req->req.length - ep->sent) <= 0) && !zlp) {
  983. done(ep, ep->tx_req, 0);
  984. ep->tx_req = NULL;
  985. ep->last = 0;
  986. ep->sent = 0;
  987. }
  988. }
  989. /* we should gain a new tx_req fot this endpoint */
  990. if (ep->tx_req == NULL) {
  991. if (!list_empty(&ep->queue)) {
  992. ep->tx_req = list_entry(ep->queue.next, struct qe_req,
  993. queue);
  994. ep->last = 0;
  995. ep->sent = 0;
  996. }
  997. }
  998. return 0;
  999. }
  1000. /* give a frame and a tx_req, send some data */
  1001. static int qe_usb_senddata(struct qe_ep *ep, struct qe_frame *frame)
  1002. {
  1003. unsigned int size;
  1004. u8 *buf;
  1005. qe_frame_clean(frame);
  1006. size = min_t(u32, (ep->tx_req->req.length - ep->sent),
  1007. ep->ep.maxpacket);
  1008. buf = (u8 *)ep->tx_req->req.buf + ep->sent;
  1009. if (buf && size) {
  1010. ep->last = size;
  1011. ep->tx_req->req.actual += size;
  1012. frame_set_data(frame, buf);
  1013. frame_set_length(frame, size);
  1014. frame_set_status(frame, FRAME_OK);
  1015. frame_set_info(frame, 0);
  1016. return qe_ep_tx(ep, frame);
  1017. }
  1018. return -EIO;
  1019. }
  1020. /* give a frame struct,send a ZLP */
  1021. static int sendnulldata(struct qe_ep *ep, struct qe_frame *frame, uint infor)
  1022. {
  1023. struct qe_udc *udc = ep->udc;
  1024. if (frame == NULL)
  1025. return -ENODEV;
  1026. qe_frame_clean(frame);
  1027. frame_set_data(frame, (u8 *)udc->nullbuf);
  1028. frame_set_length(frame, 2);
  1029. frame_set_status(frame, FRAME_OK);
  1030. frame_set_info(frame, (ZLP | NO_CRC | infor));
  1031. return qe_ep_tx(ep, frame);
  1032. }
  1033. static int frame_create_tx(struct qe_ep *ep, struct qe_frame *frame)
  1034. {
  1035. struct qe_req *req = ep->tx_req;
  1036. int reval;
  1037. if (req == NULL)
  1038. return -ENODEV;
  1039. if ((req->req.length - ep->sent) > 0)
  1040. reval = qe_usb_senddata(ep, frame);
  1041. else
  1042. reval = sendnulldata(ep, frame, 0);
  1043. return reval;
  1044. }
  1045. /* if direction is DIR_IN, the status is Device->Host
  1046. * if direction is DIR_OUT, the status transaction is Device<-Host
  1047. * in status phase, udc create a request and gain status */
  1048. static int ep0_prime_status(struct qe_udc *udc, int direction)
  1049. {
  1050. struct qe_ep *ep = &udc->eps[0];
  1051. if (direction == USB_DIR_IN) {
  1052. udc->ep0_state = DATA_STATE_NEED_ZLP;
  1053. udc->ep0_dir = USB_DIR_IN;
  1054. sendnulldata(ep, ep->txframe, SETUP_STATUS | NO_REQ);
  1055. } else {
  1056. udc->ep0_dir = USB_DIR_OUT;
  1057. udc->ep0_state = WAIT_FOR_OUT_STATUS;
  1058. }
  1059. return 0;
  1060. }
  1061. /* a request complete in ep0, whether gadget request or udc request */
  1062. static void ep0_req_complete(struct qe_udc *udc, struct qe_req *req)
  1063. {
  1064. struct qe_ep *ep = &udc->eps[0];
  1065. /* because usb and ep's status already been set in ch9setaddress() */
  1066. switch (udc->ep0_state) {
  1067. case DATA_STATE_XMIT:
  1068. done(ep, req, 0);
  1069. /* receive status phase */
  1070. if (ep0_prime_status(udc, USB_DIR_OUT))
  1071. qe_ep0_stall(udc);
  1072. break;
  1073. case DATA_STATE_NEED_ZLP:
  1074. done(ep, req, 0);
  1075. udc->ep0_state = WAIT_FOR_SETUP;
  1076. break;
  1077. case DATA_STATE_RECV:
  1078. done(ep, req, 0);
  1079. /* send status phase */
  1080. if (ep0_prime_status(udc, USB_DIR_IN))
  1081. qe_ep0_stall(udc);
  1082. break;
  1083. case WAIT_FOR_OUT_STATUS:
  1084. done(ep, req, 0);
  1085. udc->ep0_state = WAIT_FOR_SETUP;
  1086. break;
  1087. case WAIT_FOR_SETUP:
  1088. dev_vdbg(udc->dev, "Unexpected interrupt\n");
  1089. break;
  1090. default:
  1091. qe_ep0_stall(udc);
  1092. break;
  1093. }
  1094. }
  1095. static int ep0_txcomplete(struct qe_ep *ep, unsigned char restart)
  1096. {
  1097. struct qe_req *tx_req = NULL;
  1098. struct qe_frame *frame = ep->txframe;
  1099. if ((frame_get_info(frame) & (ZLP | NO_REQ)) == (ZLP | NO_REQ)) {
  1100. if (!restart)
  1101. ep->udc->ep0_state = WAIT_FOR_SETUP;
  1102. else
  1103. sendnulldata(ep, ep->txframe, SETUP_STATUS | NO_REQ);
  1104. return 0;
  1105. }
  1106. tx_req = ep->tx_req;
  1107. if (tx_req != NULL) {
  1108. if (!restart) {
  1109. int asent = ep->last;
  1110. ep->sent += asent;
  1111. ep->last -= asent;
  1112. } else {
  1113. ep->last = 0;
  1114. }
  1115. /* a request already were transmitted completely */
  1116. if ((ep->tx_req->req.length - ep->sent) <= 0) {
  1117. ep->tx_req->req.actual = (unsigned int)ep->sent;
  1118. ep0_req_complete(ep->udc, ep->tx_req);
  1119. ep->tx_req = NULL;
  1120. ep->last = 0;
  1121. ep->sent = 0;
  1122. }
  1123. } else {
  1124. dev_vdbg(ep->udc->dev, "the ep0_controller have no req\n");
  1125. }
  1126. return 0;
  1127. }
  1128. static int ep0_txframe_handle(struct qe_ep *ep)
  1129. {
  1130. /* if have error, transmit again */
  1131. if (frame_get_status(ep->txframe) & FRAME_ERROR) {
  1132. qe_ep_flushtxfifo(ep);
  1133. dev_vdbg(ep->udc->dev, "The EP0 transmit data have error!\n");
  1134. if (frame_get_info(ep->txframe) & PID_DATA0)
  1135. ep->data01 = 0;
  1136. else
  1137. ep->data01 = 1;
  1138. ep0_txcomplete(ep, 1);
  1139. } else
  1140. ep0_txcomplete(ep, 0);
  1141. frame_create_tx(ep, ep->txframe);
  1142. return 0;
  1143. }
  1144. static int qe_ep0_txconf(struct qe_ep *ep)
  1145. {
  1146. struct qe_bd __iomem *bd;
  1147. struct qe_frame *pframe;
  1148. u32 bdstatus;
  1149. bd = ep->c_txbd;
  1150. bdstatus = in_be32((u32 __iomem *)bd);
  1151. while (!(bdstatus & T_R) && (bdstatus & ~T_W)) {
  1152. pframe = ep->txframe;
  1153. /* clear and recycle the BD */
  1154. out_be32((u32 __iomem *)bd, bdstatus & T_W);
  1155. out_be32(&bd->buf, 0);
  1156. if (bdstatus & T_W)
  1157. ep->c_txbd = ep->txbase;
  1158. else
  1159. ep->c_txbd++;
  1160. if (ep->c_txbd == ep->n_txbd) {
  1161. if (bdstatus & DEVICE_T_ERROR) {
  1162. frame_set_status(pframe, FRAME_ERROR);
  1163. if (bdstatus & T_TO)
  1164. pframe->status |= TX_ER_TIMEOUT;
  1165. if (bdstatus & T_UN)
  1166. pframe->status |= TX_ER_UNDERUN;
  1167. }
  1168. ep0_txframe_handle(ep);
  1169. }
  1170. bd = ep->c_txbd;
  1171. bdstatus = in_be32((u32 __iomem *)bd);
  1172. }
  1173. return 0;
  1174. }
  1175. static int ep_txframe_handle(struct qe_ep *ep)
  1176. {
  1177. if (frame_get_status(ep->txframe) & FRAME_ERROR) {
  1178. qe_ep_flushtxfifo(ep);
  1179. dev_vdbg(ep->udc->dev, "The EP0 transmit data have error!\n");
  1180. if (frame_get_info(ep->txframe) & PID_DATA0)
  1181. ep->data01 = 0;
  1182. else
  1183. ep->data01 = 1;
  1184. txcomplete(ep, 1);
  1185. } else
  1186. txcomplete(ep, 0);
  1187. frame_create_tx(ep, ep->txframe); /* send the data */
  1188. return 0;
  1189. }
  1190. /* confirm the already trainsmited bd */
  1191. static int qe_ep_txconf(struct qe_ep *ep)
  1192. {
  1193. struct qe_bd __iomem *bd;
  1194. struct qe_frame *pframe = NULL;
  1195. u32 bdstatus;
  1196. unsigned char breakonrxinterrupt = 0;
  1197. bd = ep->c_txbd;
  1198. bdstatus = in_be32((u32 __iomem *)bd);
  1199. while (!(bdstatus & T_R) && (bdstatus & ~T_W)) {
  1200. pframe = ep->txframe;
  1201. if (bdstatus & DEVICE_T_ERROR) {
  1202. frame_set_status(pframe, FRAME_ERROR);
  1203. if (bdstatus & T_TO)
  1204. pframe->status |= TX_ER_TIMEOUT;
  1205. if (bdstatus & T_UN)
  1206. pframe->status |= TX_ER_UNDERUN;
  1207. }
  1208. /* clear and recycle the BD */
  1209. out_be32((u32 __iomem *)bd, bdstatus & T_W);
  1210. out_be32(&bd->buf, 0);
  1211. if (bdstatus & T_W)
  1212. ep->c_txbd = ep->txbase;
  1213. else
  1214. ep->c_txbd++;
  1215. /* handle the tx frame */
  1216. ep_txframe_handle(ep);
  1217. bd = ep->c_txbd;
  1218. bdstatus = in_be32((u32 __iomem *)bd);
  1219. }
  1220. if (breakonrxinterrupt)
  1221. return -EIO;
  1222. else
  1223. return 0;
  1224. }
  1225. /* Add a request in queue, and try to transmit a packet */
  1226. static int ep_req_send(struct qe_ep *ep, struct qe_req *req)
  1227. {
  1228. int reval = 0;
  1229. if (ep->tx_req == NULL) {
  1230. ep->sent = 0;
  1231. ep->last = 0;
  1232. txcomplete(ep, 0); /* can gain a new tx_req */
  1233. reval = frame_create_tx(ep, ep->txframe);
  1234. }
  1235. return reval;
  1236. }
  1237. /* Maybe this is a good ideal */
  1238. static int ep_req_rx(struct qe_ep *ep, struct qe_req *req)
  1239. {
  1240. struct qe_udc *udc = ep->udc;
  1241. struct qe_frame *pframe = NULL;
  1242. struct qe_bd __iomem *bd;
  1243. u32 bdstatus, length;
  1244. u32 vaddr, fsize;
  1245. u8 *cp;
  1246. u8 finish_req = 0;
  1247. u8 framepid;
  1248. if (list_empty(&ep->queue)) {
  1249. dev_vdbg(udc->dev, "the req already finish!\n");
  1250. return 0;
  1251. }
  1252. pframe = ep->rxframe;
  1253. bd = ep->n_rxbd;
  1254. bdstatus = in_be32((u32 __iomem *)bd);
  1255. length = bdstatus & BD_LENGTH_MASK;
  1256. while (!(bdstatus & R_E) && length) {
  1257. if (finish_req)
  1258. break;
  1259. if ((bdstatus & R_F) && (bdstatus & R_L)
  1260. && !(bdstatus & R_ERROR)) {
  1261. qe_frame_clean(pframe);
  1262. vaddr = (u32)phys_to_virt(in_be32(&bd->buf));
  1263. frame_set_data(pframe, (u8 *)vaddr);
  1264. frame_set_length(pframe, (length - USB_CRC_SIZE));
  1265. frame_set_status(pframe, FRAME_OK);
  1266. switch (bdstatus & R_PID) {
  1267. case R_PID_DATA1:
  1268. frame_set_info(pframe, PID_DATA1); break;
  1269. default:
  1270. frame_set_info(pframe, PID_DATA0); break;
  1271. }
  1272. /* handle the rx frame */
  1273. if (frame_get_info(pframe) & PID_DATA1)
  1274. framepid = 0x1;
  1275. else
  1276. framepid = 0;
  1277. if (framepid != ep->data01) {
  1278. dev_vdbg(udc->dev, "the data01 error!\n");
  1279. } else {
  1280. fsize = frame_get_length(pframe);
  1281. cp = (u8 *)(req->req.buf) + req->req.actual;
  1282. if (cp) {
  1283. memcpy(cp, pframe->data, fsize);
  1284. req->req.actual += fsize;
  1285. if ((fsize < ep->ep.maxpacket)
  1286. || (req->req.actual >=
  1287. req->req.length)) {
  1288. finish_req = 1;
  1289. done(ep, req, 0);
  1290. if (list_empty(&ep->queue))
  1291. qe_eprx_nack(ep);
  1292. }
  1293. }
  1294. qe_ep_toggledata01(ep);
  1295. }
  1296. } else {
  1297. dev_err(udc->dev, "The receive frame with error!\n");
  1298. }
  1299. /* note: don't clear the rxbd's buffer address *
  1300. * only Clear the length */
  1301. out_be32((u32 __iomem *)bd, (bdstatus & BD_STATUS_MASK));
  1302. ep->has_data--;
  1303. /* Get next BD */
  1304. if (bdstatus & R_W)
  1305. bd = ep->rxbase;
  1306. else
  1307. bd++;
  1308. bdstatus = in_be32((u32 __iomem *)bd);
  1309. length = bdstatus & BD_LENGTH_MASK;
  1310. }
  1311. ep->n_rxbd = bd;
  1312. ep_recycle_rxbds(ep);
  1313. return 0;
  1314. }
  1315. /* only add the request in queue */
  1316. static int ep_req_receive(struct qe_ep *ep, struct qe_req *req)
  1317. {
  1318. if (ep->state == EP_STATE_NACK) {
  1319. if (ep->has_data <= 0) {
  1320. /* Enable rx and unmask rx interrupt */
  1321. qe_eprx_normal(ep);
  1322. } else {
  1323. /* Copy the exist BD data */
  1324. ep_req_rx(ep, req);
  1325. }
  1326. }
  1327. return 0;
  1328. }
  1329. /********************************************************************
  1330. Internal Used Function End
  1331. ********************************************************************/
  1332. /*-----------------------------------------------------------------------
  1333. Endpoint Management Functions For Gadget
  1334. -----------------------------------------------------------------------*/
  1335. static int qe_ep_enable(struct usb_ep *_ep,
  1336. const struct usb_endpoint_descriptor *desc)
  1337. {
  1338. struct qe_udc *udc;
  1339. struct qe_ep *ep;
  1340. int retval = 0;
  1341. unsigned char epnum;
  1342. ep = container_of(_ep, struct qe_ep, ep);
  1343. /* catch various bogus parameters */
  1344. if (!_ep || !desc || _ep->name == ep_name[0] ||
  1345. (desc->bDescriptorType != USB_DT_ENDPOINT))
  1346. return -EINVAL;
  1347. udc = ep->udc;
  1348. if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN))
  1349. return -ESHUTDOWN;
  1350. epnum = (u8)desc->bEndpointAddress & 0xF;
  1351. retval = qe_ep_init(udc, epnum, desc);
  1352. if (retval != 0) {
  1353. cpm_muram_free(cpm_muram_offset(ep->rxbase));
  1354. dev_dbg(udc->dev, "enable ep%d failed\n", ep->epnum);
  1355. return -EINVAL;
  1356. }
  1357. dev_dbg(udc->dev, "enable ep%d successful\n", ep->epnum);
  1358. return 0;
  1359. }
  1360. static int qe_ep_disable(struct usb_ep *_ep)
  1361. {
  1362. struct qe_udc *udc;
  1363. struct qe_ep *ep;
  1364. unsigned long flags;
  1365. unsigned int size;
  1366. ep = container_of(_ep, struct qe_ep, ep);
  1367. udc = ep->udc;
  1368. if (!_ep || !ep->ep.desc) {
  1369. dev_dbg(udc->dev, "%s not enabled\n", _ep ? ep->ep.name : NULL);
  1370. return -EINVAL;
  1371. }
  1372. spin_lock_irqsave(&udc->lock, flags);
  1373. /* Nuke all pending requests (does flush) */
  1374. nuke(ep, -ESHUTDOWN);
  1375. ep->ep.desc = NULL;
  1376. ep->stopped = 1;
  1377. ep->tx_req = NULL;
  1378. qe_ep_reset(udc, ep->epnum);
  1379. spin_unlock_irqrestore(&udc->lock, flags);
  1380. cpm_muram_free(cpm_muram_offset(ep->rxbase));
  1381. if (ep->dir == USB_DIR_OUT)
  1382. size = (ep->ep.maxpacket + USB_CRC_SIZE + 2) *
  1383. (USB_BDRING_LEN_RX + 1);
  1384. else
  1385. size = (ep->ep.maxpacket + USB_CRC_SIZE + 2) *
  1386. (USB_BDRING_LEN + 1);
  1387. if (ep->dir != USB_DIR_IN) {
  1388. kfree(ep->rxframe);
  1389. if (ep->rxbufmap) {
  1390. dma_unmap_single(udc->gadget.dev.parent,
  1391. ep->rxbuf_d, size,
  1392. DMA_FROM_DEVICE);
  1393. ep->rxbuf_d = DMA_ADDR_INVALID;
  1394. } else {
  1395. dma_sync_single_for_cpu(
  1396. udc->gadget.dev.parent,
  1397. ep->rxbuf_d, size,
  1398. DMA_FROM_DEVICE);
  1399. }
  1400. kfree(ep->rxbuffer);
  1401. }
  1402. if (ep->dir != USB_DIR_OUT)
  1403. kfree(ep->txframe);
  1404. dev_dbg(udc->dev, "disabled %s OK\n", _ep->name);
  1405. return 0;
  1406. }
  1407. static struct usb_request *qe_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
  1408. {
  1409. struct qe_req *req;
  1410. req = kzalloc(sizeof(*req), gfp_flags);
  1411. if (!req)
  1412. return NULL;
  1413. req->req.dma = DMA_ADDR_INVALID;
  1414. INIT_LIST_HEAD(&req->queue);
  1415. return &req->req;
  1416. }
  1417. static void qe_free_request(struct usb_ep *_ep, struct usb_request *_req)
  1418. {
  1419. struct qe_req *req;
  1420. req = container_of(_req, struct qe_req, req);
  1421. if (_req)
  1422. kfree(req);
  1423. }
  1424. static int __qe_ep_queue(struct usb_ep *_ep, struct usb_request *_req)
  1425. {
  1426. struct qe_ep *ep = container_of(_ep, struct qe_ep, ep);
  1427. struct qe_req *req = container_of(_req, struct qe_req, req);
  1428. struct qe_udc *udc;
  1429. int reval;
  1430. udc = ep->udc;
  1431. /* catch various bogus parameters */
  1432. if (!_req || !req->req.complete || !req->req.buf
  1433. || !list_empty(&req->queue)) {
  1434. dev_dbg(udc->dev, "bad params\n");
  1435. return -EINVAL;
  1436. }
  1437. if (!_ep || (!ep->ep.desc && ep_index(ep))) {
  1438. dev_dbg(udc->dev, "bad ep\n");
  1439. return -EINVAL;
  1440. }
  1441. if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
  1442. return -ESHUTDOWN;
  1443. req->ep = ep;
  1444. /* map virtual address to hardware */
  1445. if (req->req.dma == DMA_ADDR_INVALID) {
  1446. req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
  1447. req->req.buf,
  1448. req->req.length,
  1449. ep_is_in(ep)
  1450. ? DMA_TO_DEVICE :
  1451. DMA_FROM_DEVICE);
  1452. req->mapped = 1;
  1453. } else {
  1454. dma_sync_single_for_device(ep->udc->gadget.dev.parent,
  1455. req->req.dma, req->req.length,
  1456. ep_is_in(ep)
  1457. ? DMA_TO_DEVICE :
  1458. DMA_FROM_DEVICE);
  1459. req->mapped = 0;
  1460. }
  1461. req->req.status = -EINPROGRESS;
  1462. req->req.actual = 0;
  1463. list_add_tail(&req->queue, &ep->queue);
  1464. dev_vdbg(udc->dev, "gadget have request in %s! %d\n",
  1465. ep->name, req->req.length);
  1466. /* push the request to device */
  1467. if (ep_is_in(ep))
  1468. reval = ep_req_send(ep, req);
  1469. /* EP0 */
  1470. if (ep_index(ep) == 0 && req->req.length > 0) {
  1471. if (ep_is_in(ep))
  1472. udc->ep0_state = DATA_STATE_XMIT;
  1473. else
  1474. udc->ep0_state = DATA_STATE_RECV;
  1475. }
  1476. if (ep->dir == USB_DIR_OUT)
  1477. reval = ep_req_receive(ep, req);
  1478. return 0;
  1479. }
  1480. /* queues (submits) an I/O request to an endpoint */
  1481. static int qe_ep_queue(struct usb_ep *_ep, struct usb_request *_req,
  1482. gfp_t gfp_flags)
  1483. {
  1484. struct qe_ep *ep = container_of(_ep, struct qe_ep, ep);
  1485. struct qe_udc *udc = ep->udc;
  1486. unsigned long flags;
  1487. int ret;
  1488. spin_lock_irqsave(&udc->lock, flags);
  1489. ret = __qe_ep_queue(_ep, _req);
  1490. spin_unlock_irqrestore(&udc->lock, flags);
  1491. return ret;
  1492. }
  1493. /* dequeues (cancels, unlinks) an I/O request from an endpoint */
  1494. static int qe_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  1495. {
  1496. struct qe_ep *ep = container_of(_ep, struct qe_ep, ep);
  1497. struct qe_req *req;
  1498. unsigned long flags;
  1499. if (!_ep || !_req)
  1500. return -EINVAL;
  1501. spin_lock_irqsave(&ep->udc->lock, flags);
  1502. /* make sure it's actually queued on this endpoint */
  1503. list_for_each_entry(req, &ep->queue, queue) {
  1504. if (&req->req == _req)
  1505. break;
  1506. }
  1507. if (&req->req != _req) {
  1508. spin_unlock_irqrestore(&ep->udc->lock, flags);
  1509. return -EINVAL;
  1510. }
  1511. done(ep, req, -ECONNRESET);
  1512. spin_unlock_irqrestore(&ep->udc->lock, flags);
  1513. return 0;
  1514. }
  1515. /*-----------------------------------------------------------------
  1516. * modify the endpoint halt feature
  1517. * @ep: the non-isochronous endpoint being stalled
  1518. * @value: 1--set halt 0--clear halt
  1519. * Returns zero, or a negative error code.
  1520. *----------------------------------------------------------------*/
  1521. static int qe_ep_set_halt(struct usb_ep *_ep, int value)
  1522. {
  1523. struct qe_ep *ep;
  1524. unsigned long flags;
  1525. int status = -EOPNOTSUPP;
  1526. struct qe_udc *udc;
  1527. ep = container_of(_ep, struct qe_ep, ep);
  1528. if (!_ep || !ep->ep.desc) {
  1529. status = -EINVAL;
  1530. goto out;
  1531. }
  1532. udc = ep->udc;
  1533. /* Attempt to halt IN ep will fail if any transfer requests
  1534. * are still queue */
  1535. if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
  1536. status = -EAGAIN;
  1537. goto out;
  1538. }
  1539. status = 0;
  1540. spin_lock_irqsave(&ep->udc->lock, flags);
  1541. qe_eptx_stall_change(ep, value);
  1542. qe_eprx_stall_change(ep, value);
  1543. spin_unlock_irqrestore(&ep->udc->lock, flags);
  1544. if (ep->epnum == 0) {
  1545. udc->ep0_state = WAIT_FOR_SETUP;
  1546. udc->ep0_dir = 0;
  1547. }
  1548. /* set data toggle to DATA0 on clear halt */
  1549. if (value == 0)
  1550. ep->data01 = 0;
  1551. out:
  1552. dev_vdbg(udc->dev, "%s %s halt stat %d\n", ep->ep.name,
  1553. value ? "set" : "clear", status);
  1554. return status;
  1555. }
  1556. static const struct usb_ep_ops qe_ep_ops = {
  1557. .enable = qe_ep_enable,
  1558. .disable = qe_ep_disable,
  1559. .alloc_request = qe_alloc_request,
  1560. .free_request = qe_free_request,
  1561. .queue = qe_ep_queue,
  1562. .dequeue = qe_ep_dequeue,
  1563. .set_halt = qe_ep_set_halt,
  1564. };
  1565. /*------------------------------------------------------------------------
  1566. Gadget Driver Layer Operations
  1567. ------------------------------------------------------------------------*/
  1568. /* Get the current frame number */
  1569. static int qe_get_frame(struct usb_gadget *gadget)
  1570. {
  1571. struct qe_udc *udc = container_of(gadget, struct qe_udc, gadget);
  1572. u16 tmp;
  1573. tmp = in_be16(&udc->usb_param->frame_n);
  1574. if (tmp & 0x8000)
  1575. return tmp & 0x07ff;
  1576. return -EINVAL;
  1577. }
  1578. static int fsl_qe_start(struct usb_gadget *gadget,
  1579. struct usb_gadget_driver *driver);
  1580. static int fsl_qe_stop(struct usb_gadget *gadget);
  1581. /* defined in usb_gadget.h */
  1582. static const struct usb_gadget_ops qe_gadget_ops = {
  1583. .get_frame = qe_get_frame,
  1584. .udc_start = fsl_qe_start,
  1585. .udc_stop = fsl_qe_stop,
  1586. };
  1587. /*-------------------------------------------------------------------------
  1588. USB ep0 Setup process in BUS Enumeration
  1589. -------------------------------------------------------------------------*/
  1590. static int udc_reset_ep_queue(struct qe_udc *udc, u8 pipe)
  1591. {
  1592. struct qe_ep *ep = &udc->eps[pipe];
  1593. nuke(ep, -ECONNRESET);
  1594. ep->tx_req = NULL;
  1595. return 0;
  1596. }
  1597. static int reset_queues(struct qe_udc *udc)
  1598. {
  1599. u8 pipe;
  1600. for (pipe = 0; pipe < USB_MAX_ENDPOINTS; pipe++)
  1601. udc_reset_ep_queue(udc, pipe);
  1602. /* report disconnect; the driver is already quiesced */
  1603. spin_unlock(&udc->lock);
  1604. usb_gadget_udc_reset(&udc->gadget, udc->driver);
  1605. spin_lock(&udc->lock);
  1606. return 0;
  1607. }
  1608. static void ch9setaddress(struct qe_udc *udc, u16 value, u16 index,
  1609. u16 length)
  1610. {
  1611. /* Save the new address to device struct */
  1612. udc->device_address = (u8) value;
  1613. /* Update usb state */
  1614. udc->usb_state = USB_STATE_ADDRESS;
  1615. /* Status phase , send a ZLP */
  1616. if (ep0_prime_status(udc, USB_DIR_IN))
  1617. qe_ep0_stall(udc);
  1618. }
  1619. static void ownercomplete(struct usb_ep *_ep, struct usb_request *_req)
  1620. {
  1621. struct qe_req *req = container_of(_req, struct qe_req, req);
  1622. req->req.buf = NULL;
  1623. kfree(req);
  1624. }
  1625. static void ch9getstatus(struct qe_udc *udc, u8 request_type, u16 value,
  1626. u16 index, u16 length)
  1627. {
  1628. u16 usb_status = 0;
  1629. struct qe_req *req;
  1630. struct qe_ep *ep;
  1631. int status = 0;
  1632. ep = &udc->eps[0];
  1633. if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
  1634. /* Get device status */
  1635. usb_status = 1 << USB_DEVICE_SELF_POWERED;
  1636. } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
  1637. /* Get interface status */
  1638. /* We don't have interface information in udc driver */
  1639. usb_status = 0;
  1640. } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
  1641. /* Get endpoint status */
  1642. int pipe = index & USB_ENDPOINT_NUMBER_MASK;
  1643. struct qe_ep *target_ep = &udc->eps[pipe];
  1644. u16 usep;
  1645. /* stall if endpoint doesn't exist */
  1646. if (!target_ep->ep.desc)
  1647. goto stall;
  1648. usep = in_be16(&udc->usb_regs->usb_usep[pipe]);
  1649. if (index & USB_DIR_IN) {
  1650. if (target_ep->dir != USB_DIR_IN)
  1651. goto stall;
  1652. if ((usep & USB_THS_MASK) == USB_THS_STALL)
  1653. usb_status = 1 << USB_ENDPOINT_HALT;
  1654. } else {
  1655. if (target_ep->dir != USB_DIR_OUT)
  1656. goto stall;
  1657. if ((usep & USB_RHS_MASK) == USB_RHS_STALL)
  1658. usb_status = 1 << USB_ENDPOINT_HALT;
  1659. }
  1660. }
  1661. req = container_of(qe_alloc_request(&ep->ep, GFP_KERNEL),
  1662. struct qe_req, req);
  1663. req->req.length = 2;
  1664. req->req.buf = udc->statusbuf;
  1665. *(u16 *)req->req.buf = cpu_to_le16(usb_status);
  1666. req->req.status = -EINPROGRESS;
  1667. req->req.actual = 0;
  1668. req->req.complete = ownercomplete;
  1669. udc->ep0_dir = USB_DIR_IN;
  1670. /* data phase */
  1671. status = __qe_ep_queue(&ep->ep, &req->req);
  1672. if (status == 0)
  1673. return;
  1674. stall:
  1675. dev_err(udc->dev, "Can't respond to getstatus request \n");
  1676. qe_ep0_stall(udc);
  1677. }
  1678. /* only handle the setup request, suppose the device in normal status */
  1679. static void setup_received_handle(struct qe_udc *udc,
  1680. struct usb_ctrlrequest *setup)
  1681. {
  1682. /* Fix Endian (udc->local_setup_buff is cpu Endian now)*/
  1683. u16 wValue = le16_to_cpu(setup->wValue);
  1684. u16 wIndex = le16_to_cpu(setup->wIndex);
  1685. u16 wLength = le16_to_cpu(setup->wLength);
  1686. /* clear the previous request in the ep0 */
  1687. udc_reset_ep_queue(udc, 0);
  1688. if (setup->bRequestType & USB_DIR_IN)
  1689. udc->ep0_dir = USB_DIR_IN;
  1690. else
  1691. udc->ep0_dir = USB_DIR_OUT;
  1692. switch (setup->bRequest) {
  1693. case USB_REQ_GET_STATUS:
  1694. /* Data+Status phase form udc */
  1695. if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
  1696. != (USB_DIR_IN | USB_TYPE_STANDARD))
  1697. break;
  1698. ch9getstatus(udc, setup->bRequestType, wValue, wIndex,
  1699. wLength);
  1700. return;
  1701. case USB_REQ_SET_ADDRESS:
  1702. /* Status phase from udc */
  1703. if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD |
  1704. USB_RECIP_DEVICE))
  1705. break;
  1706. ch9setaddress(udc, wValue, wIndex, wLength);
  1707. return;
  1708. case USB_REQ_CLEAR_FEATURE:
  1709. case USB_REQ_SET_FEATURE:
  1710. /* Requests with no data phase, status phase from udc */
  1711. if ((setup->bRequestType & USB_TYPE_MASK)
  1712. != USB_TYPE_STANDARD)
  1713. break;
  1714. if ((setup->bRequestType & USB_RECIP_MASK)
  1715. == USB_RECIP_ENDPOINT) {
  1716. int pipe = wIndex & USB_ENDPOINT_NUMBER_MASK;
  1717. struct qe_ep *ep;
  1718. if (wValue != 0 || wLength != 0
  1719. || pipe >= USB_MAX_ENDPOINTS)
  1720. break;
  1721. ep = &udc->eps[pipe];
  1722. spin_unlock(&udc->lock);
  1723. qe_ep_set_halt(&ep->ep,
  1724. (setup->bRequest == USB_REQ_SET_FEATURE)
  1725. ? 1 : 0);
  1726. spin_lock(&udc->lock);
  1727. }
  1728. ep0_prime_status(udc, USB_DIR_IN);
  1729. return;
  1730. default:
  1731. break;
  1732. }
  1733. if (wLength) {
  1734. /* Data phase from gadget, status phase from udc */
  1735. if (setup->bRequestType & USB_DIR_IN) {
  1736. udc->ep0_state = DATA_STATE_XMIT;
  1737. udc->ep0_dir = USB_DIR_IN;
  1738. } else {
  1739. udc->ep0_state = DATA_STATE_RECV;
  1740. udc->ep0_dir = USB_DIR_OUT;
  1741. }
  1742. spin_unlock(&udc->lock);
  1743. if (udc->driver->setup(&udc->gadget,
  1744. &udc->local_setup_buff) < 0)
  1745. qe_ep0_stall(udc);
  1746. spin_lock(&udc->lock);
  1747. } else {
  1748. /* No data phase, IN status from gadget */
  1749. udc->ep0_dir = USB_DIR_IN;
  1750. spin_unlock(&udc->lock);
  1751. if (udc->driver->setup(&udc->gadget,
  1752. &udc->local_setup_buff) < 0)
  1753. qe_ep0_stall(udc);
  1754. spin_lock(&udc->lock);
  1755. udc->ep0_state = DATA_STATE_NEED_ZLP;
  1756. }
  1757. }
  1758. /*-------------------------------------------------------------------------
  1759. USB Interrupt handlers
  1760. -------------------------------------------------------------------------*/
  1761. static void suspend_irq(struct qe_udc *udc)
  1762. {
  1763. udc->resume_state = udc->usb_state;
  1764. udc->usb_state = USB_STATE_SUSPENDED;
  1765. /* report suspend to the driver ,serial.c not support this*/
  1766. if (udc->driver->suspend)
  1767. udc->driver->suspend(&udc->gadget);
  1768. }
  1769. static void resume_irq(struct qe_udc *udc)
  1770. {
  1771. udc->usb_state = udc->resume_state;
  1772. udc->resume_state = 0;
  1773. /* report resume to the driver , serial.c not support this*/
  1774. if (udc->driver->resume)
  1775. udc->driver->resume(&udc->gadget);
  1776. }
  1777. static void idle_irq(struct qe_udc *udc)
  1778. {
  1779. u8 usbs;
  1780. usbs = in_8(&udc->usb_regs->usb_usbs);
  1781. if (usbs & USB_IDLE_STATUS_MASK) {
  1782. if ((udc->usb_state) != USB_STATE_SUSPENDED)
  1783. suspend_irq(udc);
  1784. } else {
  1785. if (udc->usb_state == USB_STATE_SUSPENDED)
  1786. resume_irq(udc);
  1787. }
  1788. }
  1789. static int reset_irq(struct qe_udc *udc)
  1790. {
  1791. unsigned char i;
  1792. if (udc->usb_state == USB_STATE_DEFAULT)
  1793. return 0;
  1794. qe_usb_disable(udc);
  1795. out_8(&udc->usb_regs->usb_usadr, 0);
  1796. for (i = 0; i < USB_MAX_ENDPOINTS; i++) {
  1797. if (udc->eps[i].init)
  1798. qe_ep_reset(udc, i);
  1799. }
  1800. reset_queues(udc);
  1801. udc->usb_state = USB_STATE_DEFAULT;
  1802. udc->ep0_state = WAIT_FOR_SETUP;
  1803. udc->ep0_dir = USB_DIR_OUT;
  1804. qe_usb_enable(udc);
  1805. return 0;
  1806. }
  1807. static int bsy_irq(struct qe_udc *udc)
  1808. {
  1809. return 0;
  1810. }
  1811. static int txe_irq(struct qe_udc *udc)
  1812. {
  1813. return 0;
  1814. }
  1815. /* ep0 tx interrupt also in here */
  1816. static int tx_irq(struct qe_udc *udc)
  1817. {
  1818. struct qe_ep *ep;
  1819. struct qe_bd __iomem *bd;
  1820. int i, res = 0;
  1821. if ((udc->usb_state == USB_STATE_ADDRESS)
  1822. && (in_8(&udc->usb_regs->usb_usadr) == 0))
  1823. out_8(&udc->usb_regs->usb_usadr, udc->device_address);
  1824. for (i = (USB_MAX_ENDPOINTS-1); ((i >= 0) && (res == 0)); i--) {
  1825. ep = &udc->eps[i];
  1826. if (ep && ep->init && (ep->dir != USB_DIR_OUT)) {
  1827. bd = ep->c_txbd;
  1828. if (!(in_be32((u32 __iomem *)bd) & T_R)
  1829. && (in_be32(&bd->buf))) {
  1830. /* confirm the transmitted bd */
  1831. if (ep->epnum == 0)
  1832. res = qe_ep0_txconf(ep);
  1833. else
  1834. res = qe_ep_txconf(ep);
  1835. }
  1836. }
  1837. }
  1838. return res;
  1839. }
  1840. /* setup packect's rx is handle in the function too */
  1841. static void rx_irq(struct qe_udc *udc)
  1842. {
  1843. struct qe_ep *ep;
  1844. struct qe_bd __iomem *bd;
  1845. int i;
  1846. for (i = 0; i < USB_MAX_ENDPOINTS; i++) {
  1847. ep = &udc->eps[i];
  1848. if (ep && ep->init && (ep->dir != USB_DIR_IN)) {
  1849. bd = ep->n_rxbd;
  1850. if (!(in_be32((u32 __iomem *)bd) & R_E)
  1851. && (in_be32(&bd->buf))) {
  1852. if (ep->epnum == 0) {
  1853. qe_ep0_rx(udc);
  1854. } else {
  1855. /*non-setup package receive*/
  1856. qe_ep_rx(ep);
  1857. }
  1858. }
  1859. }
  1860. }
  1861. }
  1862. static irqreturn_t qe_udc_irq(int irq, void *_udc)
  1863. {
  1864. struct qe_udc *udc = (struct qe_udc *)_udc;
  1865. u16 irq_src;
  1866. irqreturn_t status = IRQ_NONE;
  1867. unsigned long flags;
  1868. spin_lock_irqsave(&udc->lock, flags);
  1869. irq_src = in_be16(&udc->usb_regs->usb_usber) &
  1870. in_be16(&udc->usb_regs->usb_usbmr);
  1871. /* Clear notification bits */
  1872. out_be16(&udc->usb_regs->usb_usber, irq_src);
  1873. /* USB Interrupt */
  1874. if (irq_src & USB_E_IDLE_MASK) {
  1875. idle_irq(udc);
  1876. irq_src &= ~USB_E_IDLE_MASK;
  1877. status = IRQ_HANDLED;
  1878. }
  1879. if (irq_src & USB_E_TXB_MASK) {
  1880. tx_irq(udc);
  1881. irq_src &= ~USB_E_TXB_MASK;
  1882. status = IRQ_HANDLED;
  1883. }
  1884. if (irq_src & USB_E_RXB_MASK) {
  1885. rx_irq(udc);
  1886. irq_src &= ~USB_E_RXB_MASK;
  1887. status = IRQ_HANDLED;
  1888. }
  1889. if (irq_src & USB_E_RESET_MASK) {
  1890. reset_irq(udc);
  1891. irq_src &= ~USB_E_RESET_MASK;
  1892. status = IRQ_HANDLED;
  1893. }
  1894. if (irq_src & USB_E_BSY_MASK) {
  1895. bsy_irq(udc);
  1896. irq_src &= ~USB_E_BSY_MASK;
  1897. status = IRQ_HANDLED;
  1898. }
  1899. if (irq_src & USB_E_TXE_MASK) {
  1900. txe_irq(udc);
  1901. irq_src &= ~USB_E_TXE_MASK;
  1902. status = IRQ_HANDLED;
  1903. }
  1904. spin_unlock_irqrestore(&udc->lock, flags);
  1905. return status;
  1906. }
  1907. /*-------------------------------------------------------------------------
  1908. Gadget driver probe and unregister.
  1909. --------------------------------------------------------------------------*/
  1910. static int fsl_qe_start(struct usb_gadget *gadget,
  1911. struct usb_gadget_driver *driver)
  1912. {
  1913. struct qe_udc *udc;
  1914. unsigned long flags;
  1915. udc = container_of(gadget, struct qe_udc, gadget);
  1916. /* lock is needed but whether should use this lock or another */
  1917. spin_lock_irqsave(&udc->lock, flags);
  1918. driver->driver.bus = NULL;
  1919. /* hook up the driver */
  1920. udc->driver = driver;
  1921. udc->gadget.speed = driver->max_speed;
  1922. /* Enable IRQ reg and Set usbcmd reg EN bit */
  1923. qe_usb_enable(udc);
  1924. out_be16(&udc->usb_regs->usb_usber, 0xffff);
  1925. out_be16(&udc->usb_regs->usb_usbmr, USB_E_DEFAULT_DEVICE);
  1926. udc->usb_state = USB_STATE_ATTACHED;
  1927. udc->ep0_state = WAIT_FOR_SETUP;
  1928. udc->ep0_dir = USB_DIR_OUT;
  1929. spin_unlock_irqrestore(&udc->lock, flags);
  1930. return 0;
  1931. }
  1932. static int fsl_qe_stop(struct usb_gadget *gadget)
  1933. {
  1934. struct qe_udc *udc;
  1935. struct qe_ep *loop_ep;
  1936. unsigned long flags;
  1937. udc = container_of(gadget, struct qe_udc, gadget);
  1938. /* stop usb controller, disable intr */
  1939. qe_usb_disable(udc);
  1940. /* in fact, no needed */
  1941. udc->usb_state = USB_STATE_ATTACHED;
  1942. udc->ep0_state = WAIT_FOR_SETUP;
  1943. udc->ep0_dir = 0;
  1944. /* stand operation */
  1945. spin_lock_irqsave(&udc->lock, flags);
  1946. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1947. nuke(&udc->eps[0], -ESHUTDOWN);
  1948. list_for_each_entry(loop_ep, &udc->gadget.ep_list, ep.ep_list)
  1949. nuke(loop_ep, -ESHUTDOWN);
  1950. spin_unlock_irqrestore(&udc->lock, flags);
  1951. udc->driver = NULL;
  1952. return 0;
  1953. }
  1954. /* udc structure's alloc and setup, include ep-param alloc */
  1955. static struct qe_udc *qe_udc_config(struct platform_device *ofdev)
  1956. {
  1957. struct qe_udc *udc;
  1958. struct device_node *np = ofdev->dev.of_node;
  1959. unsigned long tmp_addr = 0;
  1960. struct usb_device_para __iomem *usbpram;
  1961. unsigned int i;
  1962. u64 size;
  1963. u32 offset;
  1964. udc = kzalloc(sizeof(*udc), GFP_KERNEL);
  1965. if (!udc)
  1966. goto cleanup;
  1967. udc->dev = &ofdev->dev;
  1968. /* get default address of usb parameter in MURAM from device tree */
  1969. offset = *of_get_address(np, 1, &size, NULL);
  1970. udc->usb_param = cpm_muram_addr(offset);
  1971. memset_io(udc->usb_param, 0, size);
  1972. usbpram = udc->usb_param;
  1973. out_be16(&usbpram->frame_n, 0);
  1974. out_be32(&usbpram->rstate, 0);
  1975. tmp_addr = cpm_muram_alloc((USB_MAX_ENDPOINTS *
  1976. sizeof(struct usb_ep_para)),
  1977. USB_EP_PARA_ALIGNMENT);
  1978. if (IS_ERR_VALUE(tmp_addr))
  1979. goto cleanup;
  1980. for (i = 0; i < USB_MAX_ENDPOINTS; i++) {
  1981. out_be16(&usbpram->epptr[i], (u16)tmp_addr);
  1982. udc->ep_param[i] = cpm_muram_addr(tmp_addr);
  1983. tmp_addr += 32;
  1984. }
  1985. memset_io(udc->ep_param[0], 0,
  1986. USB_MAX_ENDPOINTS * sizeof(struct usb_ep_para));
  1987. udc->resume_state = USB_STATE_NOTATTACHED;
  1988. udc->usb_state = USB_STATE_POWERED;
  1989. udc->ep0_dir = 0;
  1990. spin_lock_init(&udc->lock);
  1991. return udc;
  1992. cleanup:
  1993. kfree(udc);
  1994. return NULL;
  1995. }
  1996. /* USB Controller register init */
  1997. static int qe_udc_reg_init(struct qe_udc *udc)
  1998. {
  1999. struct usb_ctlr __iomem *qe_usbregs;
  2000. qe_usbregs = udc->usb_regs;
  2001. /* Spec says that we must enable the USB controller to change mode. */
  2002. out_8(&qe_usbregs->usb_usmod, 0x01);
  2003. /* Mode changed, now disable it, since muram isn't initialized yet. */
  2004. out_8(&qe_usbregs->usb_usmod, 0x00);
  2005. /* Initialize the rest. */
  2006. out_be16(&qe_usbregs->usb_usbmr, 0);
  2007. out_8(&qe_usbregs->usb_uscom, 0);
  2008. out_be16(&qe_usbregs->usb_usber, USBER_ALL_CLEAR);
  2009. return 0;
  2010. }
  2011. static int qe_ep_config(struct qe_udc *udc, unsigned char pipe_num)
  2012. {
  2013. struct qe_ep *ep = &udc->eps[pipe_num];
  2014. ep->udc = udc;
  2015. strcpy(ep->name, ep_name[pipe_num]);
  2016. ep->ep.name = ep_name[pipe_num];
  2017. if (pipe_num == 0) {
  2018. ep->ep.caps.type_control = true;
  2019. } else {
  2020. ep->ep.caps.type_iso = true;
  2021. ep->ep.caps.type_bulk = true;
  2022. ep->ep.caps.type_int = true;
  2023. }
  2024. ep->ep.caps.dir_in = true;
  2025. ep->ep.caps.dir_out = true;
  2026. ep->ep.ops = &qe_ep_ops;
  2027. ep->stopped = 1;
  2028. usb_ep_set_maxpacket_limit(&ep->ep, (unsigned short) ~0);
  2029. ep->ep.desc = NULL;
  2030. ep->dir = 0xff;
  2031. ep->epnum = (u8)pipe_num;
  2032. ep->sent = 0;
  2033. ep->last = 0;
  2034. ep->init = 0;
  2035. ep->rxframe = NULL;
  2036. ep->txframe = NULL;
  2037. ep->tx_req = NULL;
  2038. ep->state = EP_STATE_IDLE;
  2039. ep->has_data = 0;
  2040. /* the queue lists any req for this ep */
  2041. INIT_LIST_HEAD(&ep->queue);
  2042. /* gagdet.ep_list used for ep_autoconfig so no ep0*/
  2043. if (pipe_num != 0)
  2044. list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
  2045. ep->gadget = &udc->gadget;
  2046. return 0;
  2047. }
  2048. /*-----------------------------------------------------------------------
  2049. * UDC device Driver operation functions *
  2050. *----------------------------------------------------------------------*/
  2051. static void qe_udc_release(struct device *dev)
  2052. {
  2053. struct qe_udc *udc = container_of(dev, struct qe_udc, gadget.dev);
  2054. int i;
  2055. complete(udc->done);
  2056. cpm_muram_free(cpm_muram_offset(udc->ep_param[0]));
  2057. for (i = 0; i < USB_MAX_ENDPOINTS; i++)
  2058. udc->ep_param[i] = NULL;
  2059. kfree(udc);
  2060. }
  2061. /* Driver probe functions */
  2062. static const struct of_device_id qe_udc_match[];
  2063. static int qe_udc_probe(struct platform_device *ofdev)
  2064. {
  2065. struct qe_udc *udc;
  2066. const struct of_device_id *match;
  2067. struct device_node *np = ofdev->dev.of_node;
  2068. struct qe_ep *ep;
  2069. unsigned int ret = 0;
  2070. unsigned int i;
  2071. const void *prop;
  2072. match = of_match_device(qe_udc_match, &ofdev->dev);
  2073. if (!match)
  2074. return -EINVAL;
  2075. prop = of_get_property(np, "mode", NULL);
  2076. if (!prop || strcmp(prop, "peripheral"))
  2077. return -ENODEV;
  2078. /* Initialize the udc structure including QH member and other member */
  2079. udc = qe_udc_config(ofdev);
  2080. if (!udc) {
  2081. dev_err(&ofdev->dev, "failed to initialize\n");
  2082. return -ENOMEM;
  2083. }
  2084. udc->soc_type = (unsigned long)match->data;
  2085. udc->usb_regs = of_iomap(np, 0);
  2086. if (!udc->usb_regs) {
  2087. ret = -ENOMEM;
  2088. goto err1;
  2089. }
  2090. /* initialize usb hw reg except for regs for EP,
  2091. * leave usbintr reg untouched*/
  2092. qe_udc_reg_init(udc);
  2093. /* here comes the stand operations for probe
  2094. * set the qe_udc->gadget.xxx */
  2095. udc->gadget.ops = &qe_gadget_ops;
  2096. /* gadget.ep0 is a pointer */
  2097. udc->gadget.ep0 = &udc->eps[0].ep;
  2098. INIT_LIST_HEAD(&udc->gadget.ep_list);
  2099. /* modify in register gadget process */
  2100. udc->gadget.speed = USB_SPEED_UNKNOWN;
  2101. /* name: Identifies the controller hardware type. */
  2102. udc->gadget.name = driver_name;
  2103. udc->gadget.dev.parent = &ofdev->dev;
  2104. /* initialize qe_ep struct */
  2105. for (i = 0; i < USB_MAX_ENDPOINTS ; i++) {
  2106. /* because the ep type isn't decide here so
  2107. * qe_ep_init() should be called in ep_enable() */
  2108. /* setup the qe_ep struct and link ep.ep.list
  2109. * into gadget.ep_list */
  2110. qe_ep_config(udc, (unsigned char)i);
  2111. }
  2112. /* ep0 initialization in here */
  2113. ret = qe_ep_init(udc, 0, &qe_ep0_desc);
  2114. if (ret)
  2115. goto err2;
  2116. /* create a buf for ZLP send, need to remain zeroed */
  2117. udc->nullbuf = devm_kzalloc(&ofdev->dev, 256, GFP_KERNEL);
  2118. if (udc->nullbuf == NULL) {
  2119. ret = -ENOMEM;
  2120. goto err3;
  2121. }
  2122. /* buffer for data of get_status request */
  2123. udc->statusbuf = devm_kzalloc(&ofdev->dev, 2, GFP_KERNEL);
  2124. if (udc->statusbuf == NULL) {
  2125. ret = -ENOMEM;
  2126. goto err3;
  2127. }
  2128. udc->nullp = virt_to_phys((void *)udc->nullbuf);
  2129. if (udc->nullp == DMA_ADDR_INVALID) {
  2130. udc->nullp = dma_map_single(
  2131. udc->gadget.dev.parent,
  2132. udc->nullbuf,
  2133. 256,
  2134. DMA_TO_DEVICE);
  2135. udc->nullmap = 1;
  2136. } else {
  2137. dma_sync_single_for_device(udc->gadget.dev.parent,
  2138. udc->nullp, 256,
  2139. DMA_TO_DEVICE);
  2140. }
  2141. tasklet_init(&udc->rx_tasklet, ep_rx_tasklet,
  2142. (unsigned long)udc);
  2143. /* request irq and disable DR */
  2144. udc->usb_irq = irq_of_parse_and_map(np, 0);
  2145. if (!udc->usb_irq) {
  2146. ret = -EINVAL;
  2147. goto err_noirq;
  2148. }
  2149. ret = request_irq(udc->usb_irq, qe_udc_irq, 0,
  2150. driver_name, udc);
  2151. if (ret) {
  2152. dev_err(udc->dev, "cannot request irq %d err %d\n",
  2153. udc->usb_irq, ret);
  2154. goto err4;
  2155. }
  2156. ret = usb_add_gadget_udc_release(&ofdev->dev, &udc->gadget,
  2157. qe_udc_release);
  2158. if (ret)
  2159. goto err5;
  2160. platform_set_drvdata(ofdev, udc);
  2161. dev_info(udc->dev,
  2162. "%s USB controller initialized as device\n",
  2163. (udc->soc_type == PORT_QE) ? "QE" : "CPM");
  2164. return 0;
  2165. err5:
  2166. free_irq(udc->usb_irq, udc);
  2167. err4:
  2168. irq_dispose_mapping(udc->usb_irq);
  2169. err_noirq:
  2170. if (udc->nullmap) {
  2171. dma_unmap_single(udc->gadget.dev.parent,
  2172. udc->nullp, 256,
  2173. DMA_TO_DEVICE);
  2174. udc->nullp = DMA_ADDR_INVALID;
  2175. } else {
  2176. dma_sync_single_for_cpu(udc->gadget.dev.parent,
  2177. udc->nullp, 256,
  2178. DMA_TO_DEVICE);
  2179. }
  2180. err3:
  2181. ep = &udc->eps[0];
  2182. cpm_muram_free(cpm_muram_offset(ep->rxbase));
  2183. kfree(ep->rxframe);
  2184. kfree(ep->rxbuffer);
  2185. kfree(ep->txframe);
  2186. err2:
  2187. iounmap(udc->usb_regs);
  2188. err1:
  2189. kfree(udc);
  2190. return ret;
  2191. }
  2192. #ifdef CONFIG_PM
  2193. static int qe_udc_suspend(struct platform_device *dev, pm_message_t state)
  2194. {
  2195. return -ENOTSUPP;
  2196. }
  2197. static int qe_udc_resume(struct platform_device *dev)
  2198. {
  2199. return -ENOTSUPP;
  2200. }
  2201. #endif
  2202. static int qe_udc_remove(struct platform_device *ofdev)
  2203. {
  2204. struct qe_udc *udc = platform_get_drvdata(ofdev);
  2205. struct qe_ep *ep;
  2206. unsigned int size;
  2207. DECLARE_COMPLETION_ONSTACK(done);
  2208. usb_del_gadget_udc(&udc->gadget);
  2209. udc->done = &done;
  2210. tasklet_disable(&udc->rx_tasklet);
  2211. if (udc->nullmap) {
  2212. dma_unmap_single(udc->gadget.dev.parent,
  2213. udc->nullp, 256,
  2214. DMA_TO_DEVICE);
  2215. udc->nullp = DMA_ADDR_INVALID;
  2216. } else {
  2217. dma_sync_single_for_cpu(udc->gadget.dev.parent,
  2218. udc->nullp, 256,
  2219. DMA_TO_DEVICE);
  2220. }
  2221. ep = &udc->eps[0];
  2222. cpm_muram_free(cpm_muram_offset(ep->rxbase));
  2223. size = (ep->ep.maxpacket + USB_CRC_SIZE + 2) * (USB_BDRING_LEN + 1);
  2224. kfree(ep->rxframe);
  2225. if (ep->rxbufmap) {
  2226. dma_unmap_single(udc->gadget.dev.parent,
  2227. ep->rxbuf_d, size,
  2228. DMA_FROM_DEVICE);
  2229. ep->rxbuf_d = DMA_ADDR_INVALID;
  2230. } else {
  2231. dma_sync_single_for_cpu(udc->gadget.dev.parent,
  2232. ep->rxbuf_d, size,
  2233. DMA_FROM_DEVICE);
  2234. }
  2235. kfree(ep->rxbuffer);
  2236. kfree(ep->txframe);
  2237. free_irq(udc->usb_irq, udc);
  2238. irq_dispose_mapping(udc->usb_irq);
  2239. tasklet_kill(&udc->rx_tasklet);
  2240. iounmap(udc->usb_regs);
  2241. /* wait for release() of gadget.dev to free udc */
  2242. wait_for_completion(&done);
  2243. return 0;
  2244. }
  2245. /*-------------------------------------------------------------------------*/
  2246. static const struct of_device_id qe_udc_match[] = {
  2247. {
  2248. .compatible = "fsl,mpc8323-qe-usb",
  2249. .data = (void *)PORT_QE,
  2250. },
  2251. {
  2252. .compatible = "fsl,mpc8360-qe-usb",
  2253. .data = (void *)PORT_QE,
  2254. },
  2255. {
  2256. .compatible = "fsl,mpc8272-cpm-usb",
  2257. .data = (void *)PORT_CPM,
  2258. },
  2259. {},
  2260. };
  2261. MODULE_DEVICE_TABLE(of, qe_udc_match);
  2262. static struct platform_driver udc_driver = {
  2263. .driver = {
  2264. .name = driver_name,
  2265. .of_match_table = qe_udc_match,
  2266. },
  2267. .probe = qe_udc_probe,
  2268. .remove = qe_udc_remove,
  2269. #ifdef CONFIG_PM
  2270. .suspend = qe_udc_suspend,
  2271. .resume = qe_udc_resume,
  2272. #endif
  2273. };
  2274. module_platform_driver(udc_driver);
  2275. MODULE_DESCRIPTION(DRIVER_DESC);
  2276. MODULE_AUTHOR(DRIVER_AUTHOR);
  2277. MODULE_LICENSE("GPL");