otg_fsm.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * otg_fsm.c - ChipIdea USB IP core OTG FSM driver
  4. *
  5. * Copyright (C) 2014 Freescale Semiconductor, Inc.
  6. *
  7. * Author: Jun Li
  8. */
  9. /*
  10. * This file mainly handles OTG fsm, it includes OTG fsm operations
  11. * for HNP and SRP.
  12. *
  13. * TODO List
  14. * - ADP
  15. * - OTG test device
  16. */
  17. #include <linux/usb/otg.h>
  18. #include <linux/usb/gadget.h>
  19. #include <linux/usb/hcd.h>
  20. #include <linux/usb/chipidea.h>
  21. #include <linux/regulator/consumer.h>
  22. #include "ci.h"
  23. #include "bits.h"
  24. #include "otg.h"
  25. #include "otg_fsm.h"
  26. /* Add for otg: interact with user space app */
  27. static ssize_t
  28. a_bus_req_show(struct device *dev, struct device_attribute *attr, char *buf)
  29. {
  30. char *next;
  31. unsigned size, t;
  32. struct ci_hdrc *ci = dev_get_drvdata(dev);
  33. next = buf;
  34. size = PAGE_SIZE;
  35. t = scnprintf(next, size, "%d\n", ci->fsm.a_bus_req);
  36. size -= t;
  37. next += t;
  38. return PAGE_SIZE - size;
  39. }
  40. static ssize_t
  41. a_bus_req_store(struct device *dev, struct device_attribute *attr,
  42. const char *buf, size_t count)
  43. {
  44. struct ci_hdrc *ci = dev_get_drvdata(dev);
  45. if (count > 2)
  46. return -1;
  47. mutex_lock(&ci->fsm.lock);
  48. if (buf[0] == '0') {
  49. ci->fsm.a_bus_req = 0;
  50. } else if (buf[0] == '1') {
  51. /* If a_bus_drop is TRUE, a_bus_req can't be set */
  52. if (ci->fsm.a_bus_drop) {
  53. mutex_unlock(&ci->fsm.lock);
  54. return count;
  55. }
  56. ci->fsm.a_bus_req = 1;
  57. if (ci->fsm.otg->state == OTG_STATE_A_PERIPHERAL) {
  58. ci->gadget.host_request_flag = 1;
  59. mutex_unlock(&ci->fsm.lock);
  60. return count;
  61. }
  62. }
  63. ci_otg_queue_work(ci);
  64. mutex_unlock(&ci->fsm.lock);
  65. return count;
  66. }
  67. static DEVICE_ATTR_RW(a_bus_req);
  68. static ssize_t
  69. a_bus_drop_show(struct device *dev, struct device_attribute *attr, char *buf)
  70. {
  71. char *next;
  72. unsigned size, t;
  73. struct ci_hdrc *ci = dev_get_drvdata(dev);
  74. next = buf;
  75. size = PAGE_SIZE;
  76. t = scnprintf(next, size, "%d\n", ci->fsm.a_bus_drop);
  77. size -= t;
  78. next += t;
  79. return PAGE_SIZE - size;
  80. }
  81. static ssize_t
  82. a_bus_drop_store(struct device *dev, struct device_attribute *attr,
  83. const char *buf, size_t count)
  84. {
  85. struct ci_hdrc *ci = dev_get_drvdata(dev);
  86. if (count > 2)
  87. return -1;
  88. mutex_lock(&ci->fsm.lock);
  89. if (buf[0] == '0') {
  90. ci->fsm.a_bus_drop = 0;
  91. } else if (buf[0] == '1') {
  92. ci->fsm.a_bus_drop = 1;
  93. ci->fsm.a_bus_req = 0;
  94. }
  95. ci_otg_queue_work(ci);
  96. mutex_unlock(&ci->fsm.lock);
  97. return count;
  98. }
  99. static DEVICE_ATTR_RW(a_bus_drop);
  100. static ssize_t
  101. b_bus_req_show(struct device *dev, struct device_attribute *attr, char *buf)
  102. {
  103. char *next;
  104. unsigned size, t;
  105. struct ci_hdrc *ci = dev_get_drvdata(dev);
  106. next = buf;
  107. size = PAGE_SIZE;
  108. t = scnprintf(next, size, "%d\n", ci->fsm.b_bus_req);
  109. size -= t;
  110. next += t;
  111. return PAGE_SIZE - size;
  112. }
  113. static ssize_t
  114. b_bus_req_store(struct device *dev, struct device_attribute *attr,
  115. const char *buf, size_t count)
  116. {
  117. struct ci_hdrc *ci = dev_get_drvdata(dev);
  118. if (count > 2)
  119. return -1;
  120. mutex_lock(&ci->fsm.lock);
  121. if (buf[0] == '0')
  122. ci->fsm.b_bus_req = 0;
  123. else if (buf[0] == '1') {
  124. ci->fsm.b_bus_req = 1;
  125. if (ci->fsm.otg->state == OTG_STATE_B_PERIPHERAL) {
  126. ci->gadget.host_request_flag = 1;
  127. mutex_unlock(&ci->fsm.lock);
  128. return count;
  129. }
  130. }
  131. ci_otg_queue_work(ci);
  132. mutex_unlock(&ci->fsm.lock);
  133. return count;
  134. }
  135. static DEVICE_ATTR_RW(b_bus_req);
  136. static ssize_t
  137. a_clr_err_store(struct device *dev, struct device_attribute *attr,
  138. const char *buf, size_t count)
  139. {
  140. struct ci_hdrc *ci = dev_get_drvdata(dev);
  141. if (count > 2)
  142. return -1;
  143. mutex_lock(&ci->fsm.lock);
  144. if (buf[0] == '1')
  145. ci->fsm.a_clr_err = 1;
  146. ci_otg_queue_work(ci);
  147. mutex_unlock(&ci->fsm.lock);
  148. return count;
  149. }
  150. static DEVICE_ATTR_WO(a_clr_err);
  151. static struct attribute *inputs_attrs[] = {
  152. &dev_attr_a_bus_req.attr,
  153. &dev_attr_a_bus_drop.attr,
  154. &dev_attr_b_bus_req.attr,
  155. &dev_attr_a_clr_err.attr,
  156. NULL,
  157. };
  158. static const struct attribute_group inputs_attr_group = {
  159. .name = "inputs",
  160. .attrs = inputs_attrs,
  161. };
  162. /*
  163. * Keep this list in the same order as timers indexed
  164. * by enum otg_fsm_timer in include/linux/usb/otg-fsm.h
  165. */
  166. static unsigned otg_timer_ms[] = {
  167. TA_WAIT_VRISE,
  168. TA_WAIT_VFALL,
  169. TA_WAIT_BCON,
  170. TA_AIDL_BDIS,
  171. TB_ASE0_BRST,
  172. TA_BIDL_ADIS,
  173. TB_AIDL_BDIS,
  174. TB_SE0_SRP,
  175. TB_SRP_FAIL,
  176. 0,
  177. TB_DATA_PLS,
  178. TB_SSEND_SRP,
  179. };
  180. /*
  181. * Add timer to active timer list
  182. */
  183. static void ci_otg_add_timer(struct ci_hdrc *ci, enum otg_fsm_timer t)
  184. {
  185. unsigned long flags, timer_sec, timer_nsec;
  186. if (t >= NUM_OTG_FSM_TIMERS)
  187. return;
  188. spin_lock_irqsave(&ci->lock, flags);
  189. timer_sec = otg_timer_ms[t] / MSEC_PER_SEC;
  190. timer_nsec = (otg_timer_ms[t] % MSEC_PER_SEC) * NSEC_PER_MSEC;
  191. ci->hr_timeouts[t] = ktime_add(ktime_get(),
  192. ktime_set(timer_sec, timer_nsec));
  193. ci->enabled_otg_timer_bits |= (1 << t);
  194. if ((ci->next_otg_timer == NUM_OTG_FSM_TIMERS) ||
  195. ktime_after(ci->hr_timeouts[ci->next_otg_timer],
  196. ci->hr_timeouts[t])) {
  197. ci->next_otg_timer = t;
  198. hrtimer_start_range_ns(&ci->otg_fsm_hrtimer,
  199. ci->hr_timeouts[t], NSEC_PER_MSEC,
  200. HRTIMER_MODE_ABS);
  201. }
  202. spin_unlock_irqrestore(&ci->lock, flags);
  203. }
  204. /*
  205. * Remove timer from active timer list
  206. */
  207. static void ci_otg_del_timer(struct ci_hdrc *ci, enum otg_fsm_timer t)
  208. {
  209. unsigned long flags, enabled_timer_bits;
  210. enum otg_fsm_timer cur_timer, next_timer = NUM_OTG_FSM_TIMERS;
  211. if ((t >= NUM_OTG_FSM_TIMERS) ||
  212. !(ci->enabled_otg_timer_bits & (1 << t)))
  213. return;
  214. spin_lock_irqsave(&ci->lock, flags);
  215. ci->enabled_otg_timer_bits &= ~(1 << t);
  216. if (ci->next_otg_timer == t) {
  217. if (ci->enabled_otg_timer_bits == 0) {
  218. /* No enabled timers after delete it */
  219. hrtimer_cancel(&ci->otg_fsm_hrtimer);
  220. ci->next_otg_timer = NUM_OTG_FSM_TIMERS;
  221. } else {
  222. /* Find the next timer */
  223. enabled_timer_bits = ci->enabled_otg_timer_bits;
  224. for_each_set_bit(cur_timer, &enabled_timer_bits,
  225. NUM_OTG_FSM_TIMERS) {
  226. if ((next_timer == NUM_OTG_FSM_TIMERS) ||
  227. ktime_before(ci->hr_timeouts[next_timer],
  228. ci->hr_timeouts[cur_timer]))
  229. next_timer = cur_timer;
  230. }
  231. }
  232. }
  233. if (next_timer != NUM_OTG_FSM_TIMERS) {
  234. ci->next_otg_timer = next_timer;
  235. hrtimer_start_range_ns(&ci->otg_fsm_hrtimer,
  236. ci->hr_timeouts[next_timer], NSEC_PER_MSEC,
  237. HRTIMER_MODE_ABS);
  238. }
  239. spin_unlock_irqrestore(&ci->lock, flags);
  240. }
  241. /* OTG FSM timer handlers */
  242. static int a_wait_vrise_tmout(struct ci_hdrc *ci)
  243. {
  244. ci->fsm.a_wait_vrise_tmout = 1;
  245. return 0;
  246. }
  247. static int a_wait_vfall_tmout(struct ci_hdrc *ci)
  248. {
  249. ci->fsm.a_wait_vfall_tmout = 1;
  250. return 0;
  251. }
  252. static int a_wait_bcon_tmout(struct ci_hdrc *ci)
  253. {
  254. ci->fsm.a_wait_bcon_tmout = 1;
  255. return 0;
  256. }
  257. static int a_aidl_bdis_tmout(struct ci_hdrc *ci)
  258. {
  259. ci->fsm.a_aidl_bdis_tmout = 1;
  260. return 0;
  261. }
  262. static int b_ase0_brst_tmout(struct ci_hdrc *ci)
  263. {
  264. ci->fsm.b_ase0_brst_tmout = 1;
  265. return 0;
  266. }
  267. static int a_bidl_adis_tmout(struct ci_hdrc *ci)
  268. {
  269. ci->fsm.a_bidl_adis_tmout = 1;
  270. return 0;
  271. }
  272. static int b_aidl_bdis_tmout(struct ci_hdrc *ci)
  273. {
  274. ci->fsm.a_bus_suspend = 1;
  275. return 0;
  276. }
  277. static int b_se0_srp_tmout(struct ci_hdrc *ci)
  278. {
  279. ci->fsm.b_se0_srp = 1;
  280. return 0;
  281. }
  282. static int b_srp_fail_tmout(struct ci_hdrc *ci)
  283. {
  284. ci->fsm.b_srp_done = 1;
  285. return 1;
  286. }
  287. static int b_data_pls_tmout(struct ci_hdrc *ci)
  288. {
  289. ci->fsm.b_srp_done = 1;
  290. ci->fsm.b_bus_req = 0;
  291. if (ci->fsm.power_up)
  292. ci->fsm.power_up = 0;
  293. hw_write_otgsc(ci, OTGSC_HABA, 0);
  294. pm_runtime_put(ci->dev);
  295. return 0;
  296. }
  297. static int b_ssend_srp_tmout(struct ci_hdrc *ci)
  298. {
  299. ci->fsm.b_ssend_srp = 1;
  300. /* only vbus fall below B_sess_vld in b_idle state */
  301. if (ci->fsm.otg->state == OTG_STATE_B_IDLE)
  302. return 0;
  303. else
  304. return 1;
  305. }
  306. /*
  307. * Keep this list in the same order as timers indexed
  308. * by enum otg_fsm_timer in include/linux/usb/otg-fsm.h
  309. */
  310. static int (*otg_timer_handlers[])(struct ci_hdrc *) = {
  311. a_wait_vrise_tmout, /* A_WAIT_VRISE */
  312. a_wait_vfall_tmout, /* A_WAIT_VFALL */
  313. a_wait_bcon_tmout, /* A_WAIT_BCON */
  314. a_aidl_bdis_tmout, /* A_AIDL_BDIS */
  315. b_ase0_brst_tmout, /* B_ASE0_BRST */
  316. a_bidl_adis_tmout, /* A_BIDL_ADIS */
  317. b_aidl_bdis_tmout, /* B_AIDL_BDIS */
  318. b_se0_srp_tmout, /* B_SE0_SRP */
  319. b_srp_fail_tmout, /* B_SRP_FAIL */
  320. NULL, /* A_WAIT_ENUM */
  321. b_data_pls_tmout, /* B_DATA_PLS */
  322. b_ssend_srp_tmout, /* B_SSEND_SRP */
  323. };
  324. /*
  325. * Enable the next nearest enabled timer if have
  326. */
  327. static enum hrtimer_restart ci_otg_hrtimer_func(struct hrtimer *t)
  328. {
  329. struct ci_hdrc *ci = container_of(t, struct ci_hdrc, otg_fsm_hrtimer);
  330. ktime_t now, *timeout;
  331. unsigned long enabled_timer_bits;
  332. unsigned long flags;
  333. enum otg_fsm_timer cur_timer, next_timer = NUM_OTG_FSM_TIMERS;
  334. int ret = -EINVAL;
  335. spin_lock_irqsave(&ci->lock, flags);
  336. enabled_timer_bits = ci->enabled_otg_timer_bits;
  337. ci->next_otg_timer = NUM_OTG_FSM_TIMERS;
  338. now = ktime_get();
  339. for_each_set_bit(cur_timer, &enabled_timer_bits, NUM_OTG_FSM_TIMERS) {
  340. if (ktime_compare(now, ci->hr_timeouts[cur_timer]) >= 0) {
  341. ci->enabled_otg_timer_bits &= ~(1 << cur_timer);
  342. if (otg_timer_handlers[cur_timer])
  343. ret = otg_timer_handlers[cur_timer](ci);
  344. } else {
  345. if ((next_timer == NUM_OTG_FSM_TIMERS) ||
  346. ktime_before(ci->hr_timeouts[cur_timer],
  347. ci->hr_timeouts[next_timer]))
  348. next_timer = cur_timer;
  349. }
  350. }
  351. /* Enable the next nearest timer */
  352. if (next_timer < NUM_OTG_FSM_TIMERS) {
  353. timeout = &ci->hr_timeouts[next_timer];
  354. hrtimer_start_range_ns(&ci->otg_fsm_hrtimer, *timeout,
  355. NSEC_PER_MSEC, HRTIMER_MODE_ABS);
  356. ci->next_otg_timer = next_timer;
  357. }
  358. spin_unlock_irqrestore(&ci->lock, flags);
  359. if (!ret)
  360. ci_otg_queue_work(ci);
  361. return HRTIMER_NORESTART;
  362. }
  363. /* Initialize timers */
  364. static int ci_otg_init_timers(struct ci_hdrc *ci)
  365. {
  366. hrtimer_init(&ci->otg_fsm_hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
  367. ci->otg_fsm_hrtimer.function = ci_otg_hrtimer_func;
  368. return 0;
  369. }
  370. /* -------------------------------------------------------------*/
  371. /* Operations that will be called from OTG Finite State Machine */
  372. /* -------------------------------------------------------------*/
  373. static void ci_otg_fsm_add_timer(struct otg_fsm *fsm, enum otg_fsm_timer t)
  374. {
  375. struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm);
  376. if (t < NUM_OTG_FSM_TIMERS)
  377. ci_otg_add_timer(ci, t);
  378. return;
  379. }
  380. static void ci_otg_fsm_del_timer(struct otg_fsm *fsm, enum otg_fsm_timer t)
  381. {
  382. struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm);
  383. if (t < NUM_OTG_FSM_TIMERS)
  384. ci_otg_del_timer(ci, t);
  385. return;
  386. }
  387. /*
  388. * A-device drive vbus: turn on vbus regulator and enable port power
  389. * Data pulse irq should be disabled while vbus is on.
  390. */
  391. static void ci_otg_drv_vbus(struct otg_fsm *fsm, int on)
  392. {
  393. int ret;
  394. struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm);
  395. if (on) {
  396. /* Enable power power */
  397. hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP,
  398. PORTSC_PP);
  399. if (ci->platdata->reg_vbus) {
  400. ret = regulator_enable(ci->platdata->reg_vbus);
  401. if (ret) {
  402. dev_err(ci->dev,
  403. "Failed to enable vbus regulator, ret=%d\n",
  404. ret);
  405. return;
  406. }
  407. }
  408. /* Disable data pulse irq */
  409. hw_write_otgsc(ci, OTGSC_DPIE, 0);
  410. fsm->a_srp_det = 0;
  411. fsm->power_up = 0;
  412. } else {
  413. if (ci->platdata->reg_vbus)
  414. regulator_disable(ci->platdata->reg_vbus);
  415. fsm->a_bus_drop = 1;
  416. fsm->a_bus_req = 0;
  417. }
  418. }
  419. /*
  420. * Control data line by Run Stop bit.
  421. */
  422. static void ci_otg_loc_conn(struct otg_fsm *fsm, int on)
  423. {
  424. struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm);
  425. if (on)
  426. hw_write(ci, OP_USBCMD, USBCMD_RS, USBCMD_RS);
  427. else
  428. hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
  429. }
  430. /*
  431. * Generate SOF by host.
  432. * In host mode, controller will automatically send SOF.
  433. * Suspend will block the data on the port.
  434. *
  435. * This is controlled through usbcore by usb autosuspend,
  436. * so the usb device class driver need support autosuspend,
  437. * otherwise the bus suspend will not happen.
  438. */
  439. static void ci_otg_loc_sof(struct otg_fsm *fsm, int on)
  440. {
  441. struct usb_device *udev;
  442. if (!fsm->otg->host)
  443. return;
  444. udev = usb_hub_find_child(fsm->otg->host->root_hub, 1);
  445. if (!udev)
  446. return;
  447. if (on) {
  448. usb_disable_autosuspend(udev);
  449. } else {
  450. pm_runtime_set_autosuspend_delay(&udev->dev, 0);
  451. usb_enable_autosuspend(udev);
  452. }
  453. }
  454. /*
  455. * Start SRP pulsing by data-line pulsing,
  456. * no v-bus pulsing followed
  457. */
  458. static void ci_otg_start_pulse(struct otg_fsm *fsm)
  459. {
  460. struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm);
  461. /* Hardware Assistant Data pulse */
  462. hw_write_otgsc(ci, OTGSC_HADP, OTGSC_HADP);
  463. pm_runtime_get(ci->dev);
  464. ci_otg_add_timer(ci, B_DATA_PLS);
  465. }
  466. static int ci_otg_start_host(struct otg_fsm *fsm, int on)
  467. {
  468. struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm);
  469. if (on) {
  470. ci_role_stop(ci);
  471. ci_role_start(ci, CI_ROLE_HOST);
  472. } else {
  473. ci_role_stop(ci);
  474. ci_role_start(ci, CI_ROLE_GADGET);
  475. }
  476. return 0;
  477. }
  478. static int ci_otg_start_gadget(struct otg_fsm *fsm, int on)
  479. {
  480. struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm);
  481. if (on)
  482. usb_gadget_vbus_connect(&ci->gadget);
  483. else
  484. usb_gadget_vbus_disconnect(&ci->gadget);
  485. return 0;
  486. }
  487. static struct otg_fsm_ops ci_otg_ops = {
  488. .drv_vbus = ci_otg_drv_vbus,
  489. .loc_conn = ci_otg_loc_conn,
  490. .loc_sof = ci_otg_loc_sof,
  491. .start_pulse = ci_otg_start_pulse,
  492. .add_timer = ci_otg_fsm_add_timer,
  493. .del_timer = ci_otg_fsm_del_timer,
  494. .start_host = ci_otg_start_host,
  495. .start_gadget = ci_otg_start_gadget,
  496. };
  497. int ci_otg_fsm_work(struct ci_hdrc *ci)
  498. {
  499. /*
  500. * Don't do fsm transition for B device
  501. * when there is no gadget class driver
  502. */
  503. if (ci->fsm.id && !(ci->driver) &&
  504. ci->fsm.otg->state < OTG_STATE_A_IDLE)
  505. return 0;
  506. pm_runtime_get_sync(ci->dev);
  507. if (otg_statemachine(&ci->fsm)) {
  508. if (ci->fsm.otg->state == OTG_STATE_A_IDLE) {
  509. /*
  510. * Further state change for cases:
  511. * a_idle to b_idle; or
  512. * a_idle to a_wait_vrise due to ID change(1->0), so
  513. * B-dev becomes A-dev can try to start new session
  514. * consequently; or
  515. * a_idle to a_wait_vrise when power up
  516. */
  517. if ((ci->fsm.id) || (ci->id_event) ||
  518. (ci->fsm.power_up)) {
  519. ci_otg_queue_work(ci);
  520. } else {
  521. /* Enable data pulse irq */
  522. hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS |
  523. PORTSC_PP, 0);
  524. hw_write_otgsc(ci, OTGSC_DPIS, OTGSC_DPIS);
  525. hw_write_otgsc(ci, OTGSC_DPIE, OTGSC_DPIE);
  526. }
  527. if (ci->id_event)
  528. ci->id_event = false;
  529. } else if (ci->fsm.otg->state == OTG_STATE_B_IDLE) {
  530. if (ci->fsm.b_sess_vld) {
  531. ci->fsm.power_up = 0;
  532. /*
  533. * Further transite to b_periphearl state
  534. * when register gadget driver with vbus on
  535. */
  536. ci_otg_queue_work(ci);
  537. }
  538. } else if (ci->fsm.otg->state == OTG_STATE_A_HOST) {
  539. pm_runtime_mark_last_busy(ci->dev);
  540. pm_runtime_put_autosuspend(ci->dev);
  541. return 0;
  542. }
  543. }
  544. pm_runtime_put_sync(ci->dev);
  545. return 0;
  546. }
  547. /*
  548. * Update fsm variables in each state if catching expected interrupts,
  549. * called by otg fsm isr.
  550. */
  551. static void ci_otg_fsm_event(struct ci_hdrc *ci)
  552. {
  553. u32 intr_sts, otg_bsess_vld, port_conn;
  554. struct otg_fsm *fsm = &ci->fsm;
  555. intr_sts = hw_read_intr_status(ci);
  556. otg_bsess_vld = hw_read_otgsc(ci, OTGSC_BSV);
  557. port_conn = hw_read(ci, OP_PORTSC, PORTSC_CCS);
  558. switch (ci->fsm.otg->state) {
  559. case OTG_STATE_A_WAIT_BCON:
  560. if (port_conn) {
  561. fsm->b_conn = 1;
  562. fsm->a_bus_req = 1;
  563. ci_otg_queue_work(ci);
  564. }
  565. break;
  566. case OTG_STATE_B_IDLE:
  567. if (otg_bsess_vld && (intr_sts & USBi_PCI) && port_conn) {
  568. fsm->b_sess_vld = 1;
  569. ci_otg_queue_work(ci);
  570. }
  571. break;
  572. case OTG_STATE_B_PERIPHERAL:
  573. if ((intr_sts & USBi_SLI) && port_conn && otg_bsess_vld) {
  574. ci_otg_add_timer(ci, B_AIDL_BDIS);
  575. } else if (intr_sts & USBi_PCI) {
  576. ci_otg_del_timer(ci, B_AIDL_BDIS);
  577. if (fsm->a_bus_suspend == 1)
  578. fsm->a_bus_suspend = 0;
  579. }
  580. break;
  581. case OTG_STATE_B_HOST:
  582. if ((intr_sts & USBi_PCI) && !port_conn) {
  583. fsm->a_conn = 0;
  584. fsm->b_bus_req = 0;
  585. ci_otg_queue_work(ci);
  586. }
  587. break;
  588. case OTG_STATE_A_PERIPHERAL:
  589. if (intr_sts & USBi_SLI) {
  590. fsm->b_bus_suspend = 1;
  591. /*
  592. * Init a timer to know how long this suspend
  593. * will continue, if time out, indicates B no longer
  594. * wants to be host role
  595. */
  596. ci_otg_add_timer(ci, A_BIDL_ADIS);
  597. }
  598. if (intr_sts & USBi_URI)
  599. ci_otg_del_timer(ci, A_BIDL_ADIS);
  600. if (intr_sts & USBi_PCI) {
  601. if (fsm->b_bus_suspend == 1) {
  602. ci_otg_del_timer(ci, A_BIDL_ADIS);
  603. fsm->b_bus_suspend = 0;
  604. }
  605. }
  606. break;
  607. case OTG_STATE_A_SUSPEND:
  608. if ((intr_sts & USBi_PCI) && !port_conn) {
  609. fsm->b_conn = 0;
  610. /* if gadget driver is binded */
  611. if (ci->driver) {
  612. /* A device to be peripheral mode */
  613. ci->gadget.is_a_peripheral = 1;
  614. }
  615. ci_otg_queue_work(ci);
  616. }
  617. break;
  618. case OTG_STATE_A_HOST:
  619. if ((intr_sts & USBi_PCI) && !port_conn) {
  620. fsm->b_conn = 0;
  621. ci_otg_queue_work(ci);
  622. }
  623. break;
  624. case OTG_STATE_B_WAIT_ACON:
  625. if ((intr_sts & USBi_PCI) && port_conn) {
  626. fsm->a_conn = 1;
  627. ci_otg_queue_work(ci);
  628. }
  629. break;
  630. default:
  631. break;
  632. }
  633. }
  634. /*
  635. * ci_otg_irq - otg fsm related irq handling
  636. * and also update otg fsm variable by monitoring usb host and udc
  637. * state change interrupts.
  638. * @ci: ci_hdrc
  639. */
  640. irqreturn_t ci_otg_fsm_irq(struct ci_hdrc *ci)
  641. {
  642. irqreturn_t retval = IRQ_NONE;
  643. u32 otgsc, otg_int_src = 0;
  644. struct otg_fsm *fsm = &ci->fsm;
  645. otgsc = hw_read_otgsc(ci, ~0);
  646. otg_int_src = otgsc & OTGSC_INT_STATUS_BITS & (otgsc >> 8);
  647. fsm->id = (otgsc & OTGSC_ID) ? 1 : 0;
  648. if (otg_int_src) {
  649. if (otg_int_src & OTGSC_DPIS) {
  650. hw_write_otgsc(ci, OTGSC_DPIS, OTGSC_DPIS);
  651. fsm->a_srp_det = 1;
  652. fsm->a_bus_drop = 0;
  653. } else if (otg_int_src & OTGSC_IDIS) {
  654. hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS);
  655. if (fsm->id == 0) {
  656. fsm->a_bus_drop = 0;
  657. fsm->a_bus_req = 1;
  658. ci->id_event = true;
  659. }
  660. } else if (otg_int_src & OTGSC_BSVIS) {
  661. hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS);
  662. if (otgsc & OTGSC_BSV) {
  663. fsm->b_sess_vld = 1;
  664. ci_otg_del_timer(ci, B_SSEND_SRP);
  665. ci_otg_del_timer(ci, B_SRP_FAIL);
  666. fsm->b_ssend_srp = 0;
  667. } else {
  668. fsm->b_sess_vld = 0;
  669. if (fsm->id)
  670. ci_otg_add_timer(ci, B_SSEND_SRP);
  671. }
  672. } else if (otg_int_src & OTGSC_AVVIS) {
  673. hw_write_otgsc(ci, OTGSC_AVVIS, OTGSC_AVVIS);
  674. if (otgsc & OTGSC_AVV) {
  675. fsm->a_vbus_vld = 1;
  676. } else {
  677. fsm->a_vbus_vld = 0;
  678. fsm->b_conn = 0;
  679. }
  680. }
  681. ci_otg_queue_work(ci);
  682. return IRQ_HANDLED;
  683. }
  684. ci_otg_fsm_event(ci);
  685. return retval;
  686. }
  687. void ci_hdrc_otg_fsm_start(struct ci_hdrc *ci)
  688. {
  689. ci_otg_queue_work(ci);
  690. }
  691. int ci_hdrc_otg_fsm_init(struct ci_hdrc *ci)
  692. {
  693. int retval = 0;
  694. if (ci->phy)
  695. ci->otg.phy = ci->phy;
  696. else
  697. ci->otg.usb_phy = ci->usb_phy;
  698. ci->otg.gadget = &ci->gadget;
  699. ci->fsm.otg = &ci->otg;
  700. ci->fsm.power_up = 1;
  701. ci->fsm.id = hw_read_otgsc(ci, OTGSC_ID) ? 1 : 0;
  702. ci->fsm.otg->state = OTG_STATE_UNDEFINED;
  703. ci->fsm.ops = &ci_otg_ops;
  704. ci->gadget.hnp_polling_support = 1;
  705. ci->fsm.host_req_flag = devm_kzalloc(ci->dev, 1, GFP_KERNEL);
  706. if (!ci->fsm.host_req_flag)
  707. return -ENOMEM;
  708. mutex_init(&ci->fsm.lock);
  709. retval = ci_otg_init_timers(ci);
  710. if (retval) {
  711. dev_err(ci->dev, "Couldn't init OTG timers\n");
  712. return retval;
  713. }
  714. ci->enabled_otg_timer_bits = 0;
  715. ci->next_otg_timer = NUM_OTG_FSM_TIMERS;
  716. retval = sysfs_create_group(&ci->dev->kobj, &inputs_attr_group);
  717. if (retval < 0) {
  718. dev_dbg(ci->dev,
  719. "Can't register sysfs attr group: %d\n", retval);
  720. return retval;
  721. }
  722. /* Enable A vbus valid irq */
  723. hw_write_otgsc(ci, OTGSC_AVVIE, OTGSC_AVVIE);
  724. if (ci->fsm.id) {
  725. ci->fsm.b_ssend_srp =
  726. hw_read_otgsc(ci, OTGSC_BSV) ? 0 : 1;
  727. ci->fsm.b_sess_vld =
  728. hw_read_otgsc(ci, OTGSC_BSV) ? 1 : 0;
  729. /* Enable BSV irq */
  730. hw_write_otgsc(ci, OTGSC_BSVIE, OTGSC_BSVIE);
  731. }
  732. return 0;
  733. }
  734. void ci_hdrc_otg_fsm_remove(struct ci_hdrc *ci)
  735. {
  736. sysfs_remove_group(&ci->dev->kobj, &inputs_attr_group);
  737. }