host.c 6.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * host.c - ChipIdea USB host controller driver
  4. *
  5. * Copyright (c) 2012 Intel Corporation
  6. *
  7. * Author: Alexander Shishkin
  8. */
  9. #include <linux/kernel.h>
  10. #include <linux/io.h>
  11. #include <linux/usb.h>
  12. #include <linux/usb/hcd.h>
  13. #include <linux/usb/chipidea.h>
  14. #include <linux/regulator/consumer.h>
  15. #include "../host/ehci.h"
  16. #include "ci.h"
  17. #include "bits.h"
  18. #include "host.h"
  19. static struct hc_driver __read_mostly ci_ehci_hc_driver;
  20. static int (*orig_bus_suspend)(struct usb_hcd *hcd);
  21. struct ehci_ci_priv {
  22. struct regulator *reg_vbus;
  23. bool enabled;
  24. };
  25. static int ehci_ci_portpower(struct usb_hcd *hcd, int portnum, bool enable)
  26. {
  27. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  28. struct ehci_ci_priv *priv = (struct ehci_ci_priv *)ehci->priv;
  29. struct device *dev = hcd->self.controller;
  30. struct ci_hdrc *ci = dev_get_drvdata(dev);
  31. int ret = 0;
  32. int port = HCS_N_PORTS(ehci->hcs_params);
  33. if (priv->reg_vbus && enable != priv->enabled) {
  34. if (port > 1) {
  35. dev_warn(dev,
  36. "Not support multi-port regulator control\n");
  37. return 0;
  38. }
  39. if (enable)
  40. ret = regulator_enable(priv->reg_vbus);
  41. else
  42. ret = regulator_disable(priv->reg_vbus);
  43. if (ret) {
  44. dev_err(dev,
  45. "Failed to %s vbus regulator, ret=%d\n",
  46. enable ? "enable" : "disable", ret);
  47. return ret;
  48. }
  49. priv->enabled = enable;
  50. }
  51. if (enable && (ci->platdata->phy_mode == USBPHY_INTERFACE_MODE_HSIC)) {
  52. /*
  53. * Marvell 28nm HSIC PHY requires forcing the port to HS mode.
  54. * As HSIC is always HS, this should be safe for others.
  55. */
  56. hw_port_test_set(ci, 5);
  57. hw_port_test_set(ci, 0);
  58. }
  59. return 0;
  60. };
  61. static int ehci_ci_reset(struct usb_hcd *hcd)
  62. {
  63. struct device *dev = hcd->self.controller;
  64. struct ci_hdrc *ci = dev_get_drvdata(dev);
  65. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  66. int ret;
  67. ret = ehci_setup(hcd);
  68. if (ret)
  69. return ret;
  70. ehci->need_io_watchdog = 0;
  71. if (ci->platdata->notify_event) {
  72. ret = ci->platdata->notify_event(ci,
  73. CI_HDRC_CONTROLLER_RESET_EVENT);
  74. if (ret)
  75. return ret;
  76. }
  77. ci_platform_configure(ci);
  78. return ret;
  79. }
  80. static const struct ehci_driver_overrides ehci_ci_overrides = {
  81. .extra_priv_size = sizeof(struct ehci_ci_priv),
  82. .port_power = ehci_ci_portpower,
  83. .reset = ehci_ci_reset,
  84. };
  85. static irqreturn_t host_irq(struct ci_hdrc *ci)
  86. {
  87. return usb_hcd_irq(ci->irq, ci->hcd);
  88. }
  89. static int host_start(struct ci_hdrc *ci)
  90. {
  91. struct usb_hcd *hcd;
  92. struct ehci_hcd *ehci;
  93. struct ehci_ci_priv *priv;
  94. int ret;
  95. if (usb_disabled())
  96. return -ENODEV;
  97. hcd = __usb_create_hcd(&ci_ehci_hc_driver, ci->dev->parent,
  98. ci->dev, dev_name(ci->dev), NULL);
  99. if (!hcd)
  100. return -ENOMEM;
  101. dev_set_drvdata(ci->dev, ci);
  102. hcd->rsrc_start = ci->hw_bank.phys;
  103. hcd->rsrc_len = ci->hw_bank.size;
  104. hcd->regs = ci->hw_bank.abs;
  105. hcd->has_tt = 1;
  106. hcd->power_budget = ci->platdata->power_budget;
  107. hcd->tpl_support = ci->platdata->tpl_support;
  108. if (ci->phy || ci->usb_phy) {
  109. hcd->skip_phy_initialization = 1;
  110. if (ci->usb_phy)
  111. hcd->usb_phy = ci->usb_phy;
  112. }
  113. ehci = hcd_to_ehci(hcd);
  114. ehci->caps = ci->hw_bank.cap;
  115. ehci->has_hostpc = ci->hw_bank.lpm;
  116. ehci->has_tdi_phy_lpm = ci->hw_bank.lpm;
  117. ehci->imx28_write_fix = ci->imx28_write_fix;
  118. priv = (struct ehci_ci_priv *)ehci->priv;
  119. priv->reg_vbus = NULL;
  120. if (ci->platdata->reg_vbus && !ci_otg_is_fsm_mode(ci)) {
  121. if (ci->platdata->flags & CI_HDRC_TURN_VBUS_EARLY_ON) {
  122. ret = regulator_enable(ci->platdata->reg_vbus);
  123. if (ret) {
  124. dev_err(ci->dev,
  125. "Failed to enable vbus regulator, ret=%d\n",
  126. ret);
  127. goto put_hcd;
  128. }
  129. } else {
  130. priv->reg_vbus = ci->platdata->reg_vbus;
  131. }
  132. }
  133. ret = usb_add_hcd(hcd, 0, 0);
  134. if (ret) {
  135. goto disable_reg;
  136. } else {
  137. struct usb_otg *otg = &ci->otg;
  138. ci->hcd = hcd;
  139. if (ci_otg_is_fsm_mode(ci)) {
  140. otg->host = &hcd->self;
  141. hcd->self.otg_port = 1;
  142. }
  143. }
  144. return ret;
  145. disable_reg:
  146. if (ci->platdata->reg_vbus && !ci_otg_is_fsm_mode(ci) &&
  147. (ci->platdata->flags & CI_HDRC_TURN_VBUS_EARLY_ON))
  148. regulator_disable(ci->platdata->reg_vbus);
  149. put_hcd:
  150. usb_put_hcd(hcd);
  151. return ret;
  152. }
  153. static void host_stop(struct ci_hdrc *ci)
  154. {
  155. struct usb_hcd *hcd = ci->hcd;
  156. if (hcd) {
  157. if (ci->platdata->notify_event)
  158. ci->platdata->notify_event(ci,
  159. CI_HDRC_CONTROLLER_STOPPED_EVENT);
  160. usb_remove_hcd(hcd);
  161. ci->role = CI_ROLE_END;
  162. synchronize_irq(ci->irq);
  163. usb_put_hcd(hcd);
  164. if (ci->platdata->reg_vbus && !ci_otg_is_fsm_mode(ci) &&
  165. (ci->platdata->flags & CI_HDRC_TURN_VBUS_EARLY_ON))
  166. regulator_disable(ci->platdata->reg_vbus);
  167. }
  168. ci->hcd = NULL;
  169. ci->otg.host = NULL;
  170. }
  171. void ci_hdrc_host_destroy(struct ci_hdrc *ci)
  172. {
  173. if (ci->role == CI_ROLE_HOST && ci->hcd)
  174. host_stop(ci);
  175. }
  176. static int ci_ehci_bus_suspend(struct usb_hcd *hcd)
  177. {
  178. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  179. int port;
  180. u32 tmp;
  181. int ret = orig_bus_suspend(hcd);
  182. if (ret)
  183. return ret;
  184. port = HCS_N_PORTS(ehci->hcs_params);
  185. while (port--) {
  186. u32 __iomem *reg = &ehci->regs->port_status[port];
  187. u32 portsc = ehci_readl(ehci, reg);
  188. if (portsc & PORT_CONNECT) {
  189. /*
  190. * For chipidea, the resume signal will be ended
  191. * automatically, so for remote wakeup case, the
  192. * usbcmd.rs may not be set before the resume has
  193. * ended if other resume paths consumes too much
  194. * time (~24ms), in that case, the SOF will not
  195. * send out within 3ms after resume ends, then the
  196. * high speed device will enter full speed mode.
  197. */
  198. tmp = ehci_readl(ehci, &ehci->regs->command);
  199. tmp |= CMD_RUN;
  200. ehci_writel(ehci, tmp, &ehci->regs->command);
  201. /*
  202. * It needs a short delay between set RS bit and PHCD.
  203. */
  204. usleep_range(150, 200);
  205. break;
  206. }
  207. }
  208. return 0;
  209. }
  210. int ci_hdrc_host_init(struct ci_hdrc *ci)
  211. {
  212. struct ci_role_driver *rdrv;
  213. if (!hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_HC))
  214. return -ENXIO;
  215. rdrv = devm_kzalloc(ci->dev, sizeof(struct ci_role_driver), GFP_KERNEL);
  216. if (!rdrv)
  217. return -ENOMEM;
  218. rdrv->start = host_start;
  219. rdrv->stop = host_stop;
  220. rdrv->irq = host_irq;
  221. rdrv->name = "host";
  222. ci->roles[CI_ROLE_HOST] = rdrv;
  223. return 0;
  224. }
  225. void ci_hdrc_host_driver_init(void)
  226. {
  227. ehci_init_driver(&ci_ehci_hc_driver, &ehci_ci_overrides);
  228. orig_bus_suspend = ci_ehci_hc_driver.bus_suspend;
  229. ci_ehci_hc_driver.bus_suspend = ci_ehci_bus_suspend;
  230. }