s2-arm.S 1.7 KB

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  1. /*
  2. * Copyright © 2014-2017 Broadcom
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #include <linux/linkage.h>
  14. #include <asm/assembler.h>
  15. #include "pm.h"
  16. .text
  17. .align 3
  18. #define AON_CTRL_REG r10
  19. #define DDR_PHY_STATUS_REG r11
  20. /*
  21. * r0: AON_CTRL base address
  22. * r1: DDRY PHY PLL status register address
  23. */
  24. ENTRY(brcmstb_pm_do_s2)
  25. stmfd sp!, {r4-r11, lr}
  26. mov AON_CTRL_REG, r0
  27. mov DDR_PHY_STATUS_REG, r1
  28. /* Flush memory transactions */
  29. dsb
  30. /* Cache DDR_PHY_STATUS_REG translation */
  31. ldr r0, [DDR_PHY_STATUS_REG]
  32. /* power down request */
  33. ldr r0, =PM_S2_COMMAND
  34. ldr r1, =0
  35. str r1, [AON_CTRL_REG, #AON_CTRL_PM_CTRL]
  36. ldr r1, [AON_CTRL_REG, #AON_CTRL_PM_CTRL]
  37. str r0, [AON_CTRL_REG, #AON_CTRL_PM_CTRL]
  38. ldr r0, [AON_CTRL_REG, #AON_CTRL_PM_CTRL]
  39. /* Wait for interrupt */
  40. wfi
  41. nop
  42. /* Bring MEMC back up */
  43. 1: ldr r0, [DDR_PHY_STATUS_REG]
  44. ands r0, #1
  45. beq 1b
  46. /* Power-up handshake */
  47. ldr r0, =1
  48. str r0, [AON_CTRL_REG, #AON_CTRL_HOST_MISC_CMDS]
  49. ldr r0, [AON_CTRL_REG, #AON_CTRL_HOST_MISC_CMDS]
  50. ldr r0, =0
  51. str r0, [AON_CTRL_REG, #AON_CTRL_PM_CTRL]
  52. ldr r0, [AON_CTRL_REG, #AON_CTRL_PM_CTRL]
  53. /* Return to caller */
  54. ldr r0, =0
  55. ldmfd sp!, {r4-r11, pc}
  56. ENDPROC(brcmstb_pm_do_s2)
  57. /* Place literal pool here */
  58. .ltorg
  59. ENTRY(brcmstb_pm_do_s2_sz)
  60. .word . - brcmstb_pm_do_s2