qla_init.c 227 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2014 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include "qla_gbl.h"
  9. #include <linux/delay.h>
  10. #include <linux/slab.h>
  11. #include <linux/vmalloc.h>
  12. #include "qla_devtbl.h"
  13. #ifdef CONFIG_SPARC
  14. #include <asm/prom.h>
  15. #endif
  16. #include <target/target_core_base.h>
  17. #include "qla_target.h"
  18. /*
  19. * QLogic ISP2x00 Hardware Support Function Prototypes.
  20. */
  21. static int qla2x00_isp_firmware(scsi_qla_host_t *);
  22. static int qla2x00_setup_chip(scsi_qla_host_t *);
  23. static int qla2x00_fw_ready(scsi_qla_host_t *);
  24. static int qla2x00_configure_hba(scsi_qla_host_t *);
  25. static int qla2x00_configure_loop(scsi_qla_host_t *);
  26. static int qla2x00_configure_local_loop(scsi_qla_host_t *);
  27. static int qla2x00_configure_fabric(scsi_qla_host_t *);
  28. static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *);
  29. static int qla2x00_restart_isp(scsi_qla_host_t *);
  30. static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
  31. static int qla84xx_init_chip(scsi_qla_host_t *);
  32. static int qla25xx_init_queues(struct qla_hw_data *);
  33. static int qla24xx_post_prli_work(struct scsi_qla_host*, fc_port_t *);
  34. static void qla24xx_handle_plogi_done_event(struct scsi_qla_host *,
  35. struct event_arg *);
  36. static void qla24xx_handle_prli_done_event(struct scsi_qla_host *,
  37. struct event_arg *);
  38. static void __qla24xx_handle_gpdb_event(scsi_qla_host_t *, struct event_arg *);
  39. /* SRB Extensions ---------------------------------------------------------- */
  40. void
  41. qla2x00_sp_timeout(struct timer_list *t)
  42. {
  43. srb_t *sp = from_timer(sp, t, u.iocb_cmd.timer);
  44. struct srb_iocb *iocb;
  45. struct req_que *req;
  46. unsigned long flags;
  47. struct qla_hw_data *ha = sp->vha->hw;
  48. WARN_ON_ONCE(irqs_disabled());
  49. spin_lock_irqsave(&ha->hardware_lock, flags);
  50. req = sp->qpair->req;
  51. req->outstanding_cmds[sp->handle] = NULL;
  52. iocb = &sp->u.iocb_cmd;
  53. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  54. iocb->timeout(sp);
  55. }
  56. void
  57. qla2x00_sp_free(void *ptr)
  58. {
  59. srb_t *sp = ptr;
  60. struct srb_iocb *iocb = &sp->u.iocb_cmd;
  61. del_timer(&iocb->timer);
  62. qla2x00_rel_sp(sp);
  63. }
  64. /* Asynchronous Login/Logout Routines -------------------------------------- */
  65. unsigned long
  66. qla2x00_get_async_timeout(struct scsi_qla_host *vha)
  67. {
  68. unsigned long tmo;
  69. struct qla_hw_data *ha = vha->hw;
  70. /* Firmware should use switch negotiated r_a_tov for timeout. */
  71. tmo = ha->r_a_tov / 10 * 2;
  72. if (IS_QLAFX00(ha)) {
  73. tmo = FX00_DEF_RATOV * 2;
  74. } else if (!IS_FWI2_CAPABLE(ha)) {
  75. /*
  76. * Except for earlier ISPs where the timeout is seeded from the
  77. * initialization control block.
  78. */
  79. tmo = ha->login_timeout;
  80. }
  81. return tmo;
  82. }
  83. void
  84. qla2x00_async_iocb_timeout(void *data)
  85. {
  86. srb_t *sp = data;
  87. fc_port_t *fcport = sp->fcport;
  88. struct srb_iocb *lio = &sp->u.iocb_cmd;
  89. int rc, h;
  90. unsigned long flags;
  91. if (fcport) {
  92. ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
  93. "Async-%s timeout - hdl=%x portid=%06x %8phC.\n",
  94. sp->name, sp->handle, fcport->d_id.b24, fcport->port_name);
  95. fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
  96. } else {
  97. pr_info("Async-%s timeout - hdl=%x.\n",
  98. sp->name, sp->handle);
  99. }
  100. switch (sp->type) {
  101. case SRB_LOGIN_CMD:
  102. rc = qla24xx_async_abort_cmd(sp, false);
  103. if (rc) {
  104. /* Retry as needed. */
  105. lio->u.logio.data[0] = MBS_COMMAND_ERROR;
  106. lio->u.logio.data[1] =
  107. lio->u.logio.flags & SRB_LOGIN_RETRIED ?
  108. QLA_LOGIO_LOGIN_RETRIED : 0;
  109. spin_lock_irqsave(sp->qpair->qp_lock_ptr, flags);
  110. for (h = 1; h < sp->qpair->req->num_outstanding_cmds;
  111. h++) {
  112. if (sp->qpair->req->outstanding_cmds[h] ==
  113. sp) {
  114. sp->qpair->req->outstanding_cmds[h] =
  115. NULL;
  116. break;
  117. }
  118. }
  119. spin_unlock_irqrestore(sp->qpair->qp_lock_ptr, flags);
  120. sp->done(sp, QLA_FUNCTION_TIMEOUT);
  121. }
  122. break;
  123. case SRB_LOGOUT_CMD:
  124. case SRB_CT_PTHRU_CMD:
  125. case SRB_MB_IOCB:
  126. case SRB_NACK_PLOGI:
  127. case SRB_NACK_PRLI:
  128. case SRB_NACK_LOGO:
  129. case SRB_CTRL_VP:
  130. rc = qla24xx_async_abort_cmd(sp, false);
  131. if (rc) {
  132. spin_lock_irqsave(sp->qpair->qp_lock_ptr, flags);
  133. for (h = 1; h < sp->qpair->req->num_outstanding_cmds;
  134. h++) {
  135. if (sp->qpair->req->outstanding_cmds[h] ==
  136. sp) {
  137. sp->qpair->req->outstanding_cmds[h] =
  138. NULL;
  139. break;
  140. }
  141. }
  142. spin_unlock_irqrestore(sp->qpair->qp_lock_ptr, flags);
  143. sp->done(sp, QLA_FUNCTION_TIMEOUT);
  144. }
  145. break;
  146. }
  147. }
  148. static void
  149. qla2x00_async_login_sp_done(void *ptr, int res)
  150. {
  151. srb_t *sp = ptr;
  152. struct scsi_qla_host *vha = sp->vha;
  153. struct srb_iocb *lio = &sp->u.iocb_cmd;
  154. struct event_arg ea;
  155. ql_dbg(ql_dbg_disc, vha, 0x20dd,
  156. "%s %8phC res %d \n", __func__, sp->fcport->port_name, res);
  157. sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
  158. if (!test_bit(UNLOADING, &vha->dpc_flags)) {
  159. memset(&ea, 0, sizeof(ea));
  160. ea.event = FCME_PLOGI_DONE;
  161. ea.fcport = sp->fcport;
  162. ea.data[0] = lio->u.logio.data[0];
  163. ea.data[1] = lio->u.logio.data[1];
  164. ea.iop[0] = lio->u.logio.iop[0];
  165. ea.iop[1] = lio->u.logio.iop[1];
  166. ea.sp = sp;
  167. qla2x00_fcport_event_handler(vha, &ea);
  168. }
  169. sp->free(sp);
  170. }
  171. static inline bool
  172. fcport_is_smaller(fc_port_t *fcport)
  173. {
  174. if (wwn_to_u64(fcport->port_name) <
  175. wwn_to_u64(fcport->vha->port_name))
  176. return true;
  177. else
  178. return false;
  179. }
  180. static inline bool
  181. fcport_is_bigger(fc_port_t *fcport)
  182. {
  183. return !fcport_is_smaller(fcport);
  184. }
  185. int
  186. qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
  187. uint16_t *data)
  188. {
  189. srb_t *sp;
  190. struct srb_iocb *lio;
  191. int rval = QLA_FUNCTION_FAILED;
  192. if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT) ||
  193. fcport->loop_id == FC_NO_LOOP_ID) {
  194. ql_log(ql_log_warn, vha, 0xffff,
  195. "%s: %8phC - not sending command.\n",
  196. __func__, fcport->port_name);
  197. return rval;
  198. }
  199. sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
  200. if (!sp)
  201. goto done;
  202. fcport->flags |= FCF_ASYNC_SENT;
  203. fcport->logout_completed = 0;
  204. fcport->disc_state = DSC_LOGIN_PEND;
  205. sp->type = SRB_LOGIN_CMD;
  206. sp->name = "login";
  207. sp->gen1 = fcport->rscn_gen;
  208. sp->gen2 = fcport->login_gen;
  209. lio = &sp->u.iocb_cmd;
  210. lio->timeout = qla2x00_async_iocb_timeout;
  211. qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
  212. sp->done = qla2x00_async_login_sp_done;
  213. if (N2N_TOPO(fcport->vha->hw) && fcport_is_bigger(fcport))
  214. lio->u.logio.flags |= SRB_LOGIN_PRLI_ONLY;
  215. else
  216. lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
  217. if (fcport->fc4f_nvme)
  218. lio->u.logio.flags |= SRB_LOGIN_SKIP_PRLI;
  219. ql_dbg(ql_dbg_disc, vha, 0x2072,
  220. "Async-login - %8phC hdl=%x, loopid=%x portid=%02x%02x%02x "
  221. "retries=%d.\n", fcport->port_name, sp->handle, fcport->loop_id,
  222. fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
  223. fcport->login_retry);
  224. rval = qla2x00_start_sp(sp);
  225. if (rval != QLA_SUCCESS) {
  226. fcport->flags |= FCF_LOGIN_NEEDED;
  227. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  228. goto done_free_sp;
  229. }
  230. return rval;
  231. done_free_sp:
  232. sp->free(sp);
  233. fcport->flags &= ~FCF_ASYNC_SENT;
  234. done:
  235. fcport->flags &= ~FCF_ASYNC_ACTIVE;
  236. return rval;
  237. }
  238. static void
  239. qla2x00_async_logout_sp_done(void *ptr, int res)
  240. {
  241. srb_t *sp = ptr;
  242. sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
  243. sp->fcport->login_gen++;
  244. qlt_logo_completion_handler(sp->fcport, res);
  245. sp->free(sp);
  246. }
  247. int
  248. qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
  249. {
  250. srb_t *sp;
  251. struct srb_iocb *lio;
  252. int rval = QLA_FUNCTION_FAILED;
  253. fcport->flags |= FCF_ASYNC_SENT;
  254. sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
  255. if (!sp)
  256. goto done;
  257. sp->type = SRB_LOGOUT_CMD;
  258. sp->name = "logout";
  259. lio = &sp->u.iocb_cmd;
  260. lio->timeout = qla2x00_async_iocb_timeout;
  261. qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
  262. sp->done = qla2x00_async_logout_sp_done;
  263. ql_dbg(ql_dbg_disc, vha, 0x2070,
  264. "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x %8phC.\n",
  265. sp->handle, fcport->loop_id, fcport->d_id.b.domain,
  266. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  267. fcport->port_name);
  268. rval = qla2x00_start_sp(sp);
  269. if (rval != QLA_SUCCESS)
  270. goto done_free_sp;
  271. return rval;
  272. done_free_sp:
  273. sp->free(sp);
  274. done:
  275. fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
  276. return rval;
  277. }
  278. void
  279. qla2x00_async_prlo_done(struct scsi_qla_host *vha, fc_port_t *fcport,
  280. uint16_t *data)
  281. {
  282. fcport->flags &= ~FCF_ASYNC_ACTIVE;
  283. /* Don't re-login in target mode */
  284. if (!fcport->tgt_session)
  285. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  286. qlt_logo_completion_handler(fcport, data[0]);
  287. }
  288. static void
  289. qla2x00_async_prlo_sp_done(void *s, int res)
  290. {
  291. srb_t *sp = (srb_t *)s;
  292. struct srb_iocb *lio = &sp->u.iocb_cmd;
  293. struct scsi_qla_host *vha = sp->vha;
  294. sp->fcport->flags &= ~FCF_ASYNC_ACTIVE;
  295. if (!test_bit(UNLOADING, &vha->dpc_flags))
  296. qla2x00_post_async_prlo_done_work(sp->fcport->vha, sp->fcport,
  297. lio->u.logio.data);
  298. sp->free(sp);
  299. }
  300. int
  301. qla2x00_async_prlo(struct scsi_qla_host *vha, fc_port_t *fcport)
  302. {
  303. srb_t *sp;
  304. struct srb_iocb *lio;
  305. int rval;
  306. rval = QLA_FUNCTION_FAILED;
  307. sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
  308. if (!sp)
  309. goto done;
  310. sp->type = SRB_PRLO_CMD;
  311. sp->name = "prlo";
  312. lio = &sp->u.iocb_cmd;
  313. lio->timeout = qla2x00_async_iocb_timeout;
  314. qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
  315. sp->done = qla2x00_async_prlo_sp_done;
  316. rval = qla2x00_start_sp(sp);
  317. if (rval != QLA_SUCCESS)
  318. goto done_free_sp;
  319. ql_dbg(ql_dbg_disc, vha, 0x2070,
  320. "Async-prlo - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
  321. sp->handle, fcport->loop_id, fcport->d_id.b.domain,
  322. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  323. return rval;
  324. done_free_sp:
  325. sp->free(sp);
  326. done:
  327. fcport->flags &= ~FCF_ASYNC_ACTIVE;
  328. return rval;
  329. }
  330. static
  331. void qla24xx_handle_adisc_event(scsi_qla_host_t *vha, struct event_arg *ea)
  332. {
  333. struct fc_port *fcport = ea->fcport;
  334. ql_dbg(ql_dbg_disc, vha, 0x20d2,
  335. "%s %8phC DS %d LS %d rc %d login %d|%d rscn %d|%d lid %d\n",
  336. __func__, fcport->port_name, fcport->disc_state,
  337. fcport->fw_login_state, ea->rc, fcport->login_gen, ea->sp->gen2,
  338. fcport->rscn_gen, ea->sp->gen1, fcport->loop_id);
  339. if (ea->data[0] != MBS_COMMAND_COMPLETE) {
  340. ql_dbg(ql_dbg_disc, vha, 0x2066,
  341. "%s %8phC: adisc fail: post delete\n",
  342. __func__, ea->fcport->port_name);
  343. qlt_schedule_sess_for_deletion(ea->fcport);
  344. return;
  345. }
  346. if (ea->fcport->disc_state == DSC_DELETE_PEND)
  347. return;
  348. if (ea->sp->gen2 != ea->fcport->login_gen) {
  349. /* target side must have changed it. */
  350. ql_dbg(ql_dbg_disc, vha, 0x20d3,
  351. "%s %8phC generation changed\n",
  352. __func__, ea->fcport->port_name);
  353. return;
  354. } else if (ea->sp->gen1 != ea->fcport->rscn_gen) {
  355. ql_dbg(ql_dbg_disc, vha, 0x20d4, "%s %d %8phC post gidpn\n",
  356. __func__, __LINE__, ea->fcport->port_name);
  357. qla24xx_post_gidpn_work(vha, ea->fcport);
  358. return;
  359. }
  360. __qla24xx_handle_gpdb_event(vha, ea);
  361. }
  362. int qla_post_els_plogi_work(struct scsi_qla_host *vha, fc_port_t *fcport)
  363. {
  364. struct qla_work_evt *e;
  365. e = qla2x00_alloc_work(vha, QLA_EVT_ELS_PLOGI);
  366. if (!e)
  367. return QLA_FUNCTION_FAILED;
  368. e->u.fcport.fcport = fcport;
  369. fcport->flags |= FCF_ASYNC_ACTIVE;
  370. fcport->disc_state = DSC_LOGIN_PEND;
  371. return qla2x00_post_work(vha, e);
  372. }
  373. static void
  374. qla2x00_async_adisc_sp_done(void *ptr, int res)
  375. {
  376. srb_t *sp = ptr;
  377. struct scsi_qla_host *vha = sp->vha;
  378. struct event_arg ea;
  379. struct srb_iocb *lio = &sp->u.iocb_cmd;
  380. ql_dbg(ql_dbg_disc, vha, 0x2066,
  381. "Async done-%s res %x %8phC\n",
  382. sp->name, res, sp->fcport->port_name);
  383. sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
  384. memset(&ea, 0, sizeof(ea));
  385. ea.event = FCME_ADISC_DONE;
  386. ea.rc = res;
  387. ea.data[0] = lio->u.logio.data[0];
  388. ea.data[1] = lio->u.logio.data[1];
  389. ea.iop[0] = lio->u.logio.iop[0];
  390. ea.iop[1] = lio->u.logio.iop[1];
  391. ea.fcport = sp->fcport;
  392. ea.sp = sp;
  393. qla2x00_fcport_event_handler(vha, &ea);
  394. sp->free(sp);
  395. }
  396. int
  397. qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
  398. uint16_t *data)
  399. {
  400. srb_t *sp;
  401. struct srb_iocb *lio;
  402. int rval;
  403. rval = QLA_FUNCTION_FAILED;
  404. fcport->flags |= FCF_ASYNC_SENT;
  405. sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
  406. if (!sp)
  407. goto done;
  408. sp->type = SRB_ADISC_CMD;
  409. sp->name = "adisc";
  410. lio = &sp->u.iocb_cmd;
  411. lio->timeout = qla2x00_async_iocb_timeout;
  412. sp->gen1 = fcport->rscn_gen;
  413. sp->gen2 = fcport->login_gen;
  414. qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
  415. sp->done = qla2x00_async_adisc_sp_done;
  416. if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
  417. lio->u.logio.flags |= SRB_LOGIN_RETRIED;
  418. ql_dbg(ql_dbg_disc, vha, 0x206f,
  419. "Async-adisc - hdl=%x loopid=%x portid=%06x %8phC.\n",
  420. sp->handle, fcport->loop_id, fcport->d_id.b24, fcport->port_name);
  421. rval = qla2x00_start_sp(sp);
  422. if (rval != QLA_SUCCESS)
  423. goto done_free_sp;
  424. return rval;
  425. done_free_sp:
  426. sp->free(sp);
  427. done:
  428. fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
  429. qla2x00_post_async_adisc_work(vha, fcport, data);
  430. return rval;
  431. }
  432. static void qla24xx_handle_gnl_done_event(scsi_qla_host_t *vha,
  433. struct event_arg *ea)
  434. {
  435. fc_port_t *fcport, *conflict_fcport;
  436. struct get_name_list_extended *e;
  437. u16 i, n, found = 0, loop_id;
  438. port_id_t id;
  439. u64 wwn;
  440. u16 data[2];
  441. u8 current_login_state;
  442. fcport = ea->fcport;
  443. ql_dbg(ql_dbg_disc, vha, 0xffff,
  444. "%s %8phC DS %d LS rc %d %d login %d|%d rscn %d|%d lid %d\n",
  445. __func__, fcport->port_name, fcport->disc_state,
  446. fcport->fw_login_state, ea->rc,
  447. fcport->login_gen, fcport->last_login_gen,
  448. fcport->rscn_gen, fcport->last_rscn_gen, vha->loop_id);
  449. if (fcport->disc_state == DSC_DELETE_PEND)
  450. return;
  451. if (ea->rc) { /* rval */
  452. if (fcport->login_retry == 0) {
  453. ql_dbg(ql_dbg_disc, vha, 0x20de,
  454. "GNL failed Port login retry %8phN, retry cnt=%d.\n",
  455. fcport->port_name, fcport->login_retry);
  456. }
  457. return;
  458. }
  459. if (fcport->last_rscn_gen != fcport->rscn_gen) {
  460. ql_dbg(ql_dbg_disc, vha, 0x20df,
  461. "%s %8phC rscn gen changed rscn %d|%d \n",
  462. __func__, fcport->port_name,
  463. fcport->last_rscn_gen, fcport->rscn_gen);
  464. qla24xx_post_gidpn_work(vha, fcport);
  465. return;
  466. } else if (fcport->last_login_gen != fcport->login_gen) {
  467. ql_dbg(ql_dbg_disc, vha, 0x20e0,
  468. "%s %8phC login gen changed\n",
  469. __func__, fcport->port_name);
  470. return;
  471. }
  472. n = ea->data[0] / sizeof(struct get_name_list_extended);
  473. ql_dbg(ql_dbg_disc, vha, 0x20e1,
  474. "%s %d %8phC n %d %02x%02x%02x lid %d \n",
  475. __func__, __LINE__, fcport->port_name, n,
  476. fcport->d_id.b.domain, fcport->d_id.b.area,
  477. fcport->d_id.b.al_pa, fcport->loop_id);
  478. for (i = 0; i < n; i++) {
  479. e = &vha->gnl.l[i];
  480. wwn = wwn_to_u64(e->port_name);
  481. id.b.domain = e->port_id[2];
  482. id.b.area = e->port_id[1];
  483. id.b.al_pa = e->port_id[0];
  484. id.b.rsvd_1 = 0;
  485. if (memcmp((u8 *)&wwn, fcport->port_name, WWN_SIZE))
  486. continue;
  487. if (IS_SW_RESV_ADDR(id))
  488. continue;
  489. found = 1;
  490. loop_id = le16_to_cpu(e->nport_handle);
  491. loop_id = (loop_id & 0x7fff);
  492. if (fcport->fc4f_nvme)
  493. current_login_state = e->current_login_state >> 4;
  494. else
  495. current_login_state = e->current_login_state & 0xf;
  496. ql_dbg(ql_dbg_disc, vha, 0x20e2,
  497. "%s found %8phC CLS [%x|%x] nvme %d ID[%02x%02x%02x|%02x%02x%02x] lid[%d|%d]\n",
  498. __func__, fcport->port_name,
  499. e->current_login_state, fcport->fw_login_state,
  500. fcport->fc4f_nvme, id.b.domain, id.b.area, id.b.al_pa,
  501. fcport->d_id.b.domain, fcport->d_id.b.area,
  502. fcport->d_id.b.al_pa, loop_id, fcport->loop_id);
  503. switch (fcport->disc_state) {
  504. case DSC_DELETE_PEND:
  505. case DSC_DELETED:
  506. break;
  507. default:
  508. if ((id.b24 != fcport->d_id.b24 &&
  509. fcport->d_id.b24) ||
  510. (fcport->loop_id != FC_NO_LOOP_ID &&
  511. fcport->loop_id != loop_id)) {
  512. ql_dbg(ql_dbg_disc, vha, 0x20e3,
  513. "%s %d %8phC post del sess\n",
  514. __func__, __LINE__, fcport->port_name);
  515. qlt_schedule_sess_for_deletion(fcport);
  516. return;
  517. }
  518. break;
  519. }
  520. fcport->loop_id = loop_id;
  521. wwn = wwn_to_u64(fcport->port_name);
  522. qlt_find_sess_invalidate_other(vha, wwn,
  523. id, loop_id, &conflict_fcport);
  524. if (conflict_fcport) {
  525. /*
  526. * Another share fcport share the same loop_id &
  527. * nport id. Conflict fcport needs to finish
  528. * cleanup before this fcport can proceed to login.
  529. */
  530. conflict_fcport->conflict = fcport;
  531. fcport->login_pause = 1;
  532. }
  533. switch (vha->hw->current_topology) {
  534. default:
  535. switch (current_login_state) {
  536. case DSC_LS_PRLI_COMP:
  537. ql_dbg(ql_dbg_disc + ql_dbg_verbose,
  538. vha, 0x20e4, "%s %d %8phC post gpdb\n",
  539. __func__, __LINE__, fcport->port_name);
  540. if ((e->prli_svc_param_word_3[0] & BIT_4) == 0)
  541. fcport->port_type = FCT_INITIATOR;
  542. else
  543. fcport->port_type = FCT_TARGET;
  544. data[0] = data[1] = 0;
  545. qla2x00_post_async_adisc_work(vha, fcport,
  546. data);
  547. break;
  548. case DSC_LS_PORT_UNAVAIL:
  549. default:
  550. if (fcport->loop_id == FC_NO_LOOP_ID) {
  551. qla2x00_find_new_loop_id(vha, fcport);
  552. fcport->fw_login_state =
  553. DSC_LS_PORT_UNAVAIL;
  554. }
  555. ql_dbg(ql_dbg_disc, vha, 0x20e5,
  556. "%s %d %8phC\n", __func__, __LINE__,
  557. fcport->port_name);
  558. qla24xx_fcport_handle_login(vha, fcport);
  559. break;
  560. }
  561. break;
  562. case ISP_CFG_N:
  563. fcport->fw_login_state = current_login_state;
  564. fcport->d_id = id;
  565. switch (current_login_state) {
  566. case DSC_LS_PRLI_COMP:
  567. if ((e->prli_svc_param_word_3[0] & BIT_4) == 0)
  568. fcport->port_type = FCT_INITIATOR;
  569. else
  570. fcport->port_type = FCT_TARGET;
  571. data[0] = data[1] = 0;
  572. qla2x00_post_async_adisc_work(vha, fcport,
  573. data);
  574. break;
  575. case DSC_LS_PLOGI_COMP:
  576. if (fcport_is_bigger(fcport)) {
  577. /* local adapter is smaller */
  578. if (fcport->loop_id != FC_NO_LOOP_ID)
  579. qla2x00_clear_loop_id(fcport);
  580. fcport->loop_id = loop_id;
  581. qla24xx_fcport_handle_login(vha,
  582. fcport);
  583. break;
  584. }
  585. /* drop through */
  586. default:
  587. if (fcport_is_smaller(fcport)) {
  588. /* local adapter is bigger */
  589. if (fcport->loop_id != FC_NO_LOOP_ID)
  590. qla2x00_clear_loop_id(fcport);
  591. fcport->loop_id = loop_id;
  592. qla24xx_fcport_handle_login(vha,
  593. fcport);
  594. }
  595. break;
  596. }
  597. break;
  598. } /* switch (ha->current_topology) */
  599. }
  600. if (!found) {
  601. switch (vha->hw->current_topology) {
  602. case ISP_CFG_F:
  603. case ISP_CFG_FL:
  604. for (i = 0; i < n; i++) {
  605. e = &vha->gnl.l[i];
  606. id.b.domain = e->port_id[0];
  607. id.b.area = e->port_id[1];
  608. id.b.al_pa = e->port_id[2];
  609. id.b.rsvd_1 = 0;
  610. loop_id = le16_to_cpu(e->nport_handle);
  611. if (fcport->d_id.b24 == id.b24) {
  612. conflict_fcport =
  613. qla2x00_find_fcport_by_wwpn(vha,
  614. e->port_name, 0);
  615. if (conflict_fcport) {
  616. ql_dbg(ql_dbg_disc + ql_dbg_verbose,
  617. vha, 0x20e5,
  618. "%s %d %8phC post del sess\n",
  619. __func__, __LINE__,
  620. conflict_fcport->port_name);
  621. qlt_schedule_sess_for_deletion
  622. (conflict_fcport);
  623. }
  624. }
  625. /*
  626. * FW already picked this loop id for
  627. * another fcport
  628. */
  629. if (fcport->loop_id == loop_id)
  630. fcport->loop_id = FC_NO_LOOP_ID;
  631. }
  632. qla24xx_fcport_handle_login(vha, fcport);
  633. break;
  634. case ISP_CFG_N:
  635. fcport->disc_state = DSC_DELETED;
  636. if (time_after_eq(jiffies, fcport->dm_login_expire)) {
  637. if (fcport->n2n_link_reset_cnt < 2) {
  638. fcport->n2n_link_reset_cnt++;
  639. /*
  640. * remote port is not sending PLOGI.
  641. * Reset link to kick start his state
  642. * machine
  643. */
  644. set_bit(N2N_LINK_RESET,
  645. &vha->dpc_flags);
  646. } else {
  647. if (fcport->n2n_chip_reset < 1) {
  648. ql_log(ql_log_info, vha, 0x705d,
  649. "Chip reset to bring laser down");
  650. set_bit(ISP_ABORT_NEEDED,
  651. &vha->dpc_flags);
  652. fcport->n2n_chip_reset++;
  653. } else {
  654. ql_log(ql_log_info, vha, 0x705d,
  655. "Remote port %8ph is not coming back\n",
  656. fcport->port_name);
  657. fcport->scan_state = 0;
  658. }
  659. }
  660. qla2xxx_wake_dpc(vha);
  661. } else {
  662. /*
  663. * report port suppose to do PLOGI. Give him
  664. * more time. FW will catch it.
  665. */
  666. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  667. }
  668. break;
  669. default:
  670. break;
  671. }
  672. }
  673. } /* gnl_event */
  674. static void
  675. qla24xx_async_gnl_sp_done(void *s, int res)
  676. {
  677. struct srb *sp = s;
  678. struct scsi_qla_host *vha = sp->vha;
  679. unsigned long flags;
  680. struct fc_port *fcport = NULL, *tf;
  681. u16 i, n = 0, loop_id;
  682. struct event_arg ea;
  683. struct get_name_list_extended *e;
  684. u64 wwn;
  685. struct list_head h;
  686. bool found = false;
  687. ql_dbg(ql_dbg_disc, vha, 0x20e7,
  688. "Async done-%s res %x mb[1]=%x mb[2]=%x \n",
  689. sp->name, res, sp->u.iocb_cmd.u.mbx.in_mb[1],
  690. sp->u.iocb_cmd.u.mbx.in_mb[2]);
  691. if (res == QLA_FUNCTION_TIMEOUT)
  692. return;
  693. memset(&ea, 0, sizeof(ea));
  694. ea.sp = sp;
  695. ea.rc = res;
  696. ea.event = FCME_GNL_DONE;
  697. if (sp->u.iocb_cmd.u.mbx.in_mb[1] >=
  698. sizeof(struct get_name_list_extended)) {
  699. n = sp->u.iocb_cmd.u.mbx.in_mb[1] /
  700. sizeof(struct get_name_list_extended);
  701. ea.data[0] = sp->u.iocb_cmd.u.mbx.in_mb[1]; /* amnt xfered */
  702. }
  703. for (i = 0; i < n; i++) {
  704. e = &vha->gnl.l[i];
  705. loop_id = le16_to_cpu(e->nport_handle);
  706. /* mask out reserve bit */
  707. loop_id = (loop_id & 0x7fff);
  708. set_bit(loop_id, vha->hw->loop_id_map);
  709. wwn = wwn_to_u64(e->port_name);
  710. ql_dbg(ql_dbg_disc + ql_dbg_verbose, vha, 0x20e8,
  711. "%s %8phC %02x:%02x:%02x state %d/%d lid %x \n",
  712. __func__, (void *)&wwn, e->port_id[2], e->port_id[1],
  713. e->port_id[0], e->current_login_state, e->last_login_state,
  714. (loop_id & 0x7fff));
  715. }
  716. spin_lock_irqsave(&vha->gnl.fcports_lock, flags);
  717. INIT_LIST_HEAD(&h);
  718. fcport = tf = NULL;
  719. if (!list_empty(&vha->gnl.fcports))
  720. list_splice_init(&vha->gnl.fcports, &h);
  721. list_for_each_entry_safe(fcport, tf, &h, gnl_entry) {
  722. list_del_init(&fcport->gnl_entry);
  723. spin_lock(&vha->hw->tgt.sess_lock);
  724. fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
  725. spin_unlock(&vha->hw->tgt.sess_lock);
  726. ea.fcport = fcport;
  727. qla2x00_fcport_event_handler(vha, &ea);
  728. }
  729. spin_unlock_irqrestore(&vha->gnl.fcports_lock, flags);
  730. spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
  731. /* create new fcport if fw has knowledge of new sessions */
  732. for (i = 0; i < n; i++) {
  733. port_id_t id;
  734. u64 wwnn;
  735. e = &vha->gnl.l[i];
  736. wwn = wwn_to_u64(e->port_name);
  737. found = false;
  738. list_for_each_entry_safe(fcport, tf, &vha->vp_fcports, list) {
  739. if (!memcmp((u8 *)&wwn, fcport->port_name,
  740. WWN_SIZE)) {
  741. found = true;
  742. break;
  743. }
  744. }
  745. id.b.domain = e->port_id[2];
  746. id.b.area = e->port_id[1];
  747. id.b.al_pa = e->port_id[0];
  748. id.b.rsvd_1 = 0;
  749. if (!found && wwn && !IS_SW_RESV_ADDR(id)) {
  750. ql_dbg(ql_dbg_disc, vha, 0x2065,
  751. "%s %d %8phC %06x post new sess\n",
  752. __func__, __LINE__, (u8 *)&wwn, id.b24);
  753. wwnn = wwn_to_u64(e->node_name);
  754. qla24xx_post_newsess_work(vha, &id, (u8 *)&wwn,
  755. (u8 *)&wwnn, NULL, FC4_TYPE_UNKNOWN);
  756. }
  757. }
  758. spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
  759. sp->free(sp);
  760. }
  761. int qla24xx_async_gnl(struct scsi_qla_host *vha, fc_port_t *fcport)
  762. {
  763. srb_t *sp;
  764. struct srb_iocb *mbx;
  765. int rval = QLA_FUNCTION_FAILED;
  766. unsigned long flags;
  767. u16 *mb;
  768. if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT))
  769. return rval;
  770. ql_dbg(ql_dbg_disc, vha, 0x20d9,
  771. "Async-gnlist WWPN %8phC \n", fcport->port_name);
  772. spin_lock_irqsave(&vha->gnl.fcports_lock, flags);
  773. if (!list_empty(&fcport->gnl_entry)) {
  774. spin_unlock_irqrestore(&vha->gnl.fcports_lock, flags);
  775. rval = QLA_SUCCESS;
  776. goto done;
  777. }
  778. spin_lock(&vha->hw->tgt.sess_lock);
  779. fcport->disc_state = DSC_GNL;
  780. fcport->last_rscn_gen = fcport->rscn_gen;
  781. fcport->last_login_gen = fcport->login_gen;
  782. spin_unlock(&vha->hw->tgt.sess_lock);
  783. list_add_tail(&fcport->gnl_entry, &vha->gnl.fcports);
  784. spin_unlock_irqrestore(&vha->gnl.fcports_lock, flags);
  785. sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
  786. if (!sp)
  787. goto done;
  788. fcport->flags |= FCF_ASYNC_SENT;
  789. sp->type = SRB_MB_IOCB;
  790. sp->name = "gnlist";
  791. sp->gen1 = fcport->rscn_gen;
  792. sp->gen2 = fcport->login_gen;
  793. mbx = &sp->u.iocb_cmd;
  794. mbx->timeout = qla2x00_async_iocb_timeout;
  795. qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha)+2);
  796. mb = sp->u.iocb_cmd.u.mbx.out_mb;
  797. mb[0] = MBC_PORT_NODE_NAME_LIST;
  798. mb[1] = BIT_2 | BIT_3;
  799. mb[2] = MSW(vha->gnl.ldma);
  800. mb[3] = LSW(vha->gnl.ldma);
  801. mb[6] = MSW(MSD(vha->gnl.ldma));
  802. mb[7] = LSW(MSD(vha->gnl.ldma));
  803. mb[8] = vha->gnl.size;
  804. mb[9] = vha->vp_idx;
  805. sp->done = qla24xx_async_gnl_sp_done;
  806. rval = qla2x00_start_sp(sp);
  807. if (rval != QLA_SUCCESS)
  808. goto done_free_sp;
  809. ql_dbg(ql_dbg_disc, vha, 0x20da,
  810. "Async-%s - OUT WWPN %8phC hndl %x\n",
  811. sp->name, fcport->port_name, sp->handle);
  812. return rval;
  813. done_free_sp:
  814. sp->free(sp);
  815. fcport->flags &= ~FCF_ASYNC_SENT;
  816. done:
  817. return rval;
  818. }
  819. int qla24xx_post_gnl_work(struct scsi_qla_host *vha, fc_port_t *fcport)
  820. {
  821. struct qla_work_evt *e;
  822. e = qla2x00_alloc_work(vha, QLA_EVT_GNL);
  823. if (!e)
  824. return QLA_FUNCTION_FAILED;
  825. e->u.fcport.fcport = fcport;
  826. fcport->flags |= FCF_ASYNC_ACTIVE;
  827. fcport->disc_state = DSC_LOGIN_PEND;
  828. return qla2x00_post_work(vha, e);
  829. }
  830. static
  831. void qla24xx_async_gpdb_sp_done(void *s, int res)
  832. {
  833. struct srb *sp = s;
  834. struct scsi_qla_host *vha = sp->vha;
  835. struct qla_hw_data *ha = vha->hw;
  836. fc_port_t *fcport = sp->fcport;
  837. u16 *mb = sp->u.iocb_cmd.u.mbx.in_mb;
  838. struct event_arg ea;
  839. ql_dbg(ql_dbg_disc, vha, 0x20db,
  840. "Async done-%s res %x, WWPN %8phC mb[1]=%x mb[2]=%x \n",
  841. sp->name, res, fcport->port_name, mb[1], mb[2]);
  842. fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
  843. if (res == QLA_FUNCTION_TIMEOUT)
  844. goto done;
  845. memset(&ea, 0, sizeof(ea));
  846. ea.event = FCME_GPDB_DONE;
  847. ea.fcport = fcport;
  848. ea.sp = sp;
  849. qla2x00_fcport_event_handler(vha, &ea);
  850. done:
  851. dma_pool_free(ha->s_dma_pool, sp->u.iocb_cmd.u.mbx.in,
  852. sp->u.iocb_cmd.u.mbx.in_dma);
  853. sp->free(sp);
  854. }
  855. static int qla24xx_post_prli_work(struct scsi_qla_host *vha, fc_port_t *fcport)
  856. {
  857. struct qla_work_evt *e;
  858. e = qla2x00_alloc_work(vha, QLA_EVT_PRLI);
  859. if (!e)
  860. return QLA_FUNCTION_FAILED;
  861. e->u.fcport.fcport = fcport;
  862. return qla2x00_post_work(vha, e);
  863. }
  864. static void
  865. qla2x00_async_prli_sp_done(void *ptr, int res)
  866. {
  867. srb_t *sp = ptr;
  868. struct scsi_qla_host *vha = sp->vha;
  869. struct srb_iocb *lio = &sp->u.iocb_cmd;
  870. struct event_arg ea;
  871. ql_dbg(ql_dbg_disc, vha, 0x2129,
  872. "%s %8phC res %d \n", __func__,
  873. sp->fcport->port_name, res);
  874. sp->fcport->flags &= ~FCF_ASYNC_SENT;
  875. if (!test_bit(UNLOADING, &vha->dpc_flags)) {
  876. memset(&ea, 0, sizeof(ea));
  877. ea.event = FCME_PRLI_DONE;
  878. ea.fcport = sp->fcport;
  879. ea.data[0] = lio->u.logio.data[0];
  880. ea.data[1] = lio->u.logio.data[1];
  881. ea.iop[0] = lio->u.logio.iop[0];
  882. ea.iop[1] = lio->u.logio.iop[1];
  883. ea.sp = sp;
  884. qla2x00_fcport_event_handler(vha, &ea);
  885. }
  886. sp->free(sp);
  887. }
  888. int
  889. qla24xx_async_prli(struct scsi_qla_host *vha, fc_port_t *fcport)
  890. {
  891. srb_t *sp;
  892. struct srb_iocb *lio;
  893. int rval = QLA_FUNCTION_FAILED;
  894. if (!vha->flags.online)
  895. return rval;
  896. if (fcport->fw_login_state == DSC_LS_PLOGI_PEND ||
  897. fcport->fw_login_state == DSC_LS_PRLI_PEND)
  898. return rval;
  899. sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
  900. if (!sp)
  901. return rval;
  902. fcport->flags |= FCF_ASYNC_SENT;
  903. fcport->logout_completed = 0;
  904. sp->type = SRB_PRLI_CMD;
  905. sp->name = "prli";
  906. lio = &sp->u.iocb_cmd;
  907. lio->timeout = qla2x00_async_iocb_timeout;
  908. qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
  909. sp->done = qla2x00_async_prli_sp_done;
  910. lio->u.logio.flags = 0;
  911. if (fcport->fc4f_nvme)
  912. lio->u.logio.flags |= SRB_LOGIN_NVME_PRLI;
  913. rval = qla2x00_start_sp(sp);
  914. if (rval != QLA_SUCCESS) {
  915. fcport->flags |= FCF_LOGIN_NEEDED;
  916. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  917. goto done_free_sp;
  918. }
  919. ql_dbg(ql_dbg_disc, vha, 0x211b,
  920. "Async-prli - %8phC hdl=%x, loopid=%x portid=%06x retries=%d %s.\n",
  921. fcport->port_name, sp->handle, fcport->loop_id, fcport->d_id.b24,
  922. fcport->login_retry, fcport->fc4f_nvme ? "nvme" : "fc");
  923. return rval;
  924. done_free_sp:
  925. sp->free(sp);
  926. fcport->flags &= ~FCF_ASYNC_SENT;
  927. return rval;
  928. }
  929. int qla24xx_post_gpdb_work(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt)
  930. {
  931. struct qla_work_evt *e;
  932. e = qla2x00_alloc_work(vha, QLA_EVT_GPDB);
  933. if (!e)
  934. return QLA_FUNCTION_FAILED;
  935. e->u.fcport.fcport = fcport;
  936. e->u.fcport.opt = opt;
  937. fcport->flags |= FCF_ASYNC_ACTIVE;
  938. return qla2x00_post_work(vha, e);
  939. }
  940. int qla24xx_async_gpdb(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt)
  941. {
  942. srb_t *sp;
  943. struct srb_iocb *mbx;
  944. int rval = QLA_FUNCTION_FAILED;
  945. u16 *mb;
  946. dma_addr_t pd_dma;
  947. struct port_database_24xx *pd;
  948. struct qla_hw_data *ha = vha->hw;
  949. if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT) ||
  950. fcport->loop_id == FC_NO_LOOP_ID) {
  951. ql_log(ql_log_warn, vha, 0xffff,
  952. "%s: %8phC - not sending command.\n",
  953. __func__, fcport->port_name);
  954. return rval;
  955. }
  956. fcport->disc_state = DSC_GPDB;
  957. sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
  958. if (!sp)
  959. goto done;
  960. fcport->flags |= FCF_ASYNC_SENT;
  961. sp->type = SRB_MB_IOCB;
  962. sp->name = "gpdb";
  963. sp->gen1 = fcport->rscn_gen;
  964. sp->gen2 = fcport->login_gen;
  965. mbx = &sp->u.iocb_cmd;
  966. mbx->timeout = qla2x00_async_iocb_timeout;
  967. qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
  968. pd = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
  969. if (pd == NULL) {
  970. ql_log(ql_log_warn, vha, 0xd043,
  971. "Failed to allocate port database structure.\n");
  972. goto done_free_sp;
  973. }
  974. mb = sp->u.iocb_cmd.u.mbx.out_mb;
  975. mb[0] = MBC_GET_PORT_DATABASE;
  976. mb[1] = fcport->loop_id;
  977. mb[2] = MSW(pd_dma);
  978. mb[3] = LSW(pd_dma);
  979. mb[6] = MSW(MSD(pd_dma));
  980. mb[7] = LSW(MSD(pd_dma));
  981. mb[9] = vha->vp_idx;
  982. mb[10] = opt;
  983. mbx->u.mbx.in = (void *)pd;
  984. mbx->u.mbx.in_dma = pd_dma;
  985. sp->done = qla24xx_async_gpdb_sp_done;
  986. ql_dbg(ql_dbg_disc, vha, 0x20dc,
  987. "Async-%s %8phC hndl %x opt %x\n",
  988. sp->name, fcport->port_name, sp->handle, opt);
  989. rval = qla2x00_start_sp(sp);
  990. if (rval != QLA_SUCCESS)
  991. goto done_free_sp;
  992. return rval;
  993. done_free_sp:
  994. if (pd)
  995. dma_pool_free(ha->s_dma_pool, pd, pd_dma);
  996. sp->free(sp);
  997. fcport->flags &= ~FCF_ASYNC_SENT;
  998. done:
  999. qla24xx_post_gpdb_work(vha, fcport, opt);
  1000. return rval;
  1001. }
  1002. static
  1003. void __qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, struct event_arg *ea)
  1004. {
  1005. unsigned long flags;
  1006. spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
  1007. ea->fcport->login_gen++;
  1008. ea->fcport->deleted = 0;
  1009. ea->fcport->logout_on_delete = 1;
  1010. if (!ea->fcport->login_succ && !IS_SW_RESV_ADDR(ea->fcport->d_id)) {
  1011. vha->fcport_count++;
  1012. ea->fcport->login_succ = 1;
  1013. ql_dbg(ql_dbg_disc, vha, 0x20d6,
  1014. "%s %d %8phC post upd_fcport fcp_cnt %d\n",
  1015. __func__, __LINE__, ea->fcport->port_name,
  1016. vha->fcport_count);
  1017. qla24xx_post_upd_fcport_work(vha, ea->fcport);
  1018. } else if (ea->fcport->login_succ) {
  1019. /*
  1020. * We have an existing session. A late RSCN delivery
  1021. * must have triggered the session to be re-validate.
  1022. * Session is still valid.
  1023. */
  1024. ql_dbg(ql_dbg_disc, vha, 0x20d6,
  1025. "%s %d %8phC session revalidate success\n",
  1026. __func__, __LINE__, ea->fcport->port_name);
  1027. ea->fcport->disc_state = DSC_LOGIN_COMPLETE;
  1028. }
  1029. spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
  1030. }
  1031. static
  1032. void qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, struct event_arg *ea)
  1033. {
  1034. fc_port_t *fcport = ea->fcport;
  1035. struct port_database_24xx *pd;
  1036. struct srb *sp = ea->sp;
  1037. uint8_t ls;
  1038. pd = (struct port_database_24xx *)sp->u.iocb_cmd.u.mbx.in;
  1039. fcport->flags &= ~FCF_ASYNC_SENT;
  1040. ql_dbg(ql_dbg_disc, vha, 0x20d2,
  1041. "%s %8phC DS %d LS %d nvme %x rc %d\n", __func__, fcport->port_name,
  1042. fcport->disc_state, pd->current_login_state, fcport->fc4f_nvme,
  1043. ea->rc);
  1044. if (fcport->disc_state == DSC_DELETE_PEND)
  1045. return;
  1046. if (fcport->fc4f_nvme)
  1047. ls = pd->current_login_state >> 4;
  1048. else
  1049. ls = pd->current_login_state & 0xf;
  1050. switch (ls) {
  1051. case PDS_PRLI_COMPLETE:
  1052. __qla24xx_parse_gpdb(vha, fcport, pd);
  1053. break;
  1054. case PDS_PLOGI_PENDING:
  1055. case PDS_PLOGI_COMPLETE:
  1056. case PDS_PRLI_PENDING:
  1057. case PDS_PRLI2_PENDING:
  1058. /* Set discovery state back to GNL to Relogin attempt */
  1059. if (qla_dual_mode_enabled(vha) ||
  1060. qla_ini_mode_enabled(vha)) {
  1061. fcport->disc_state = DSC_GNL;
  1062. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  1063. }
  1064. return;
  1065. case PDS_LOGO_PENDING:
  1066. case PDS_PORT_UNAVAILABLE:
  1067. default:
  1068. ql_dbg(ql_dbg_disc, vha, 0x20d5, "%s %d %8phC post del sess\n",
  1069. __func__, __LINE__, fcport->port_name);
  1070. qlt_schedule_sess_for_deletion(fcport);
  1071. return;
  1072. }
  1073. __qla24xx_handle_gpdb_event(vha, ea);
  1074. } /* gpdb event */
  1075. static void qla_chk_n2n_b4_login(struct scsi_qla_host *vha, fc_port_t *fcport)
  1076. {
  1077. u8 login = 0;
  1078. int rc;
  1079. if (qla_tgt_mode_enabled(vha))
  1080. return;
  1081. if (qla_dual_mode_enabled(vha)) {
  1082. if (N2N_TOPO(vha->hw)) {
  1083. u64 mywwn, wwn;
  1084. mywwn = wwn_to_u64(vha->port_name);
  1085. wwn = wwn_to_u64(fcport->port_name);
  1086. if (mywwn > wwn)
  1087. login = 1;
  1088. else if ((fcport->fw_login_state == DSC_LS_PLOGI_COMP)
  1089. && time_after_eq(jiffies,
  1090. fcport->plogi_nack_done_deadline))
  1091. login = 1;
  1092. } else {
  1093. login = 1;
  1094. }
  1095. } else {
  1096. /* initiator mode */
  1097. login = 1;
  1098. }
  1099. if (login) {
  1100. if (fcport->loop_id == FC_NO_LOOP_ID) {
  1101. fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
  1102. rc = qla2x00_find_new_loop_id(vha, fcport);
  1103. if (rc) {
  1104. ql_dbg(ql_dbg_disc, vha, 0x20e6,
  1105. "%s %d %8phC post del sess - out of loopid\n",
  1106. __func__, __LINE__, fcport->port_name);
  1107. fcport->scan_state = 0;
  1108. qlt_schedule_sess_for_deletion(fcport);
  1109. return;
  1110. }
  1111. }
  1112. ql_dbg(ql_dbg_disc, vha, 0x20bf,
  1113. "%s %d %8phC post login\n",
  1114. __func__, __LINE__, fcport->port_name);
  1115. qla2x00_post_async_login_work(vha, fcport, NULL);
  1116. }
  1117. }
  1118. int qla24xx_fcport_handle_login(struct scsi_qla_host *vha, fc_port_t *fcport)
  1119. {
  1120. u16 data[2];
  1121. u64 wwn;
  1122. ql_dbg(ql_dbg_disc, vha, 0x20d8,
  1123. "%s %8phC DS %d LS %d P %d fl %x confl %p rscn %d|%d login %d retry %d lid %d scan %d\n",
  1124. __func__, fcport->port_name, fcport->disc_state,
  1125. fcport->fw_login_state, fcport->login_pause, fcport->flags,
  1126. fcport->conflict, fcport->last_rscn_gen, fcport->rscn_gen,
  1127. fcport->login_gen, fcport->login_retry,
  1128. fcport->loop_id, fcport->scan_state);
  1129. if (fcport->scan_state != QLA_FCPORT_FOUND)
  1130. return 0;
  1131. if ((fcport->loop_id != FC_NO_LOOP_ID) &&
  1132. ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
  1133. (fcport->fw_login_state == DSC_LS_PRLI_PEND)))
  1134. return 0;
  1135. if (fcport->fw_login_state == DSC_LS_PLOGI_COMP) {
  1136. if (time_before_eq(jiffies, fcport->plogi_nack_done_deadline)) {
  1137. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  1138. return 0;
  1139. }
  1140. }
  1141. /* for pure Target Mode. Login will not be initiated */
  1142. if (vha->host->active_mode == MODE_TARGET)
  1143. return 0;
  1144. if (fcport->flags & FCF_ASYNC_SENT) {
  1145. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  1146. return 0;
  1147. }
  1148. switch (fcport->disc_state) {
  1149. case DSC_DELETED:
  1150. wwn = wwn_to_u64(fcport->node_name);
  1151. switch (vha->hw->current_topology) {
  1152. case ISP_CFG_N:
  1153. if (fcport_is_smaller(fcport)) {
  1154. /* this adapter is bigger */
  1155. if (fcport->login_retry) {
  1156. if (fcport->loop_id == FC_NO_LOOP_ID) {
  1157. qla2x00_find_new_loop_id(vha,
  1158. fcport);
  1159. fcport->fw_login_state =
  1160. DSC_LS_PORT_UNAVAIL;
  1161. }
  1162. fcport->login_retry--;
  1163. qla_post_els_plogi_work(vha, fcport);
  1164. } else {
  1165. ql_log(ql_log_info, vha, 0x705d,
  1166. "Unable to reach remote port %8phC",
  1167. fcport->port_name);
  1168. }
  1169. } else {
  1170. qla24xx_post_gnl_work(vha, fcport);
  1171. }
  1172. break;
  1173. default:
  1174. if (wwn == 0) {
  1175. ql_dbg(ql_dbg_disc, vha, 0xffff,
  1176. "%s %d %8phC post GNNID\n",
  1177. __func__, __LINE__, fcport->port_name);
  1178. qla24xx_post_gnnid_work(vha, fcport);
  1179. } else if (fcport->loop_id == FC_NO_LOOP_ID) {
  1180. ql_dbg(ql_dbg_disc, vha, 0x20bd,
  1181. "%s %d %8phC post gnl\n",
  1182. __func__, __LINE__, fcport->port_name);
  1183. qla24xx_post_gnl_work(vha, fcport);
  1184. } else {
  1185. qla_chk_n2n_b4_login(vha, fcport);
  1186. }
  1187. break;
  1188. }
  1189. break;
  1190. case DSC_GNL:
  1191. switch (vha->hw->current_topology) {
  1192. case ISP_CFG_N:
  1193. if ((fcport->current_login_state & 0xf) == 0x6) {
  1194. ql_dbg(ql_dbg_disc, vha, 0x2118,
  1195. "%s %d %8phC post GPDB work\n",
  1196. __func__, __LINE__, fcport->port_name);
  1197. fcport->chip_reset =
  1198. vha->hw->base_qpair->chip_reset;
  1199. qla24xx_post_gpdb_work(vha, fcport, 0);
  1200. } else {
  1201. ql_dbg(ql_dbg_disc, vha, 0x2118,
  1202. "%s %d %8phC post NVMe PRLI\n",
  1203. __func__, __LINE__, fcport->port_name);
  1204. qla24xx_post_prli_work(vha, fcport);
  1205. }
  1206. break;
  1207. default:
  1208. if (fcport->login_pause) {
  1209. fcport->last_rscn_gen = fcport->rscn_gen;
  1210. fcport->last_login_gen = fcport->login_gen;
  1211. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  1212. break;
  1213. }
  1214. qla_chk_n2n_b4_login(vha, fcport);
  1215. break;
  1216. }
  1217. break;
  1218. case DSC_LOGIN_FAILED:
  1219. fcport->login_retry--;
  1220. ql_dbg(ql_dbg_disc, vha, 0x20d0,
  1221. "%s %d %8phC post gidpn\n",
  1222. __func__, __LINE__, fcport->port_name);
  1223. if (N2N_TOPO(vha->hw))
  1224. qla_chk_n2n_b4_login(vha, fcport);
  1225. else
  1226. qla24xx_post_gidpn_work(vha, fcport);
  1227. break;
  1228. case DSC_LOGIN_COMPLETE:
  1229. /* recheck login state */
  1230. ql_dbg(ql_dbg_disc, vha, 0x20d1,
  1231. "%s %d %8phC post adisc\n",
  1232. __func__, __LINE__, fcport->port_name);
  1233. fcport->login_retry--;
  1234. data[0] = data[1] = 0;
  1235. qla2x00_post_async_adisc_work(vha, fcport, data);
  1236. break;
  1237. case DSC_LOGIN_PEND:
  1238. if (fcport->fw_login_state == DSC_LS_PLOGI_COMP)
  1239. qla24xx_post_prli_work(vha, fcport);
  1240. break;
  1241. default:
  1242. break;
  1243. }
  1244. return 0;
  1245. }
  1246. static
  1247. void qla24xx_handle_rscn_event(fc_port_t *fcport, struct event_arg *ea)
  1248. {
  1249. fcport->rscn_gen++;
  1250. ql_dbg(ql_dbg_disc, fcport->vha, 0x210c,
  1251. "%s %8phC DS %d LS %d\n",
  1252. __func__, fcport->port_name, fcport->disc_state,
  1253. fcport->fw_login_state);
  1254. if (fcport->flags & FCF_ASYNC_SENT)
  1255. return;
  1256. switch (fcport->disc_state) {
  1257. case DSC_DELETED:
  1258. case DSC_LOGIN_COMPLETE:
  1259. qla24xx_post_gpnid_work(fcport->vha, &ea->id);
  1260. break;
  1261. default:
  1262. break;
  1263. }
  1264. }
  1265. int qla24xx_post_newsess_work(struct scsi_qla_host *vha, port_id_t *id,
  1266. u8 *port_name, u8 *node_name, void *pla, u8 fc4_type)
  1267. {
  1268. struct qla_work_evt *e;
  1269. e = qla2x00_alloc_work(vha, QLA_EVT_NEW_SESS);
  1270. if (!e)
  1271. return QLA_FUNCTION_FAILED;
  1272. e->u.new_sess.id = *id;
  1273. e->u.new_sess.pla = pla;
  1274. e->u.new_sess.fc4_type = fc4_type;
  1275. memcpy(e->u.new_sess.port_name, port_name, WWN_SIZE);
  1276. if (node_name)
  1277. memcpy(e->u.new_sess.node_name, node_name, WWN_SIZE);
  1278. return qla2x00_post_work(vha, e);
  1279. }
  1280. static
  1281. void qla24xx_handle_relogin_event(scsi_qla_host_t *vha,
  1282. struct event_arg *ea)
  1283. {
  1284. fc_port_t *fcport = ea->fcport;
  1285. ql_dbg(ql_dbg_disc, vha, 0x2102,
  1286. "%s %8phC DS %d LS %d P %d del %d cnfl %p rscn %d|%d login %d|%d fl %x\n",
  1287. __func__, fcport->port_name, fcport->disc_state,
  1288. fcport->fw_login_state, fcport->login_pause,
  1289. fcport->deleted, fcport->conflict,
  1290. fcport->last_rscn_gen, fcport->rscn_gen,
  1291. fcport->last_login_gen, fcport->login_gen,
  1292. fcport->flags);
  1293. if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
  1294. (fcport->fw_login_state == DSC_LS_PRLI_PEND))
  1295. return;
  1296. if (fcport->fw_login_state == DSC_LS_PLOGI_COMP) {
  1297. if (time_before_eq(jiffies, fcport->plogi_nack_done_deadline)) {
  1298. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  1299. return;
  1300. }
  1301. }
  1302. if (fcport->last_rscn_gen != fcport->rscn_gen) {
  1303. ql_dbg(ql_dbg_disc, vha, 0x20e9, "%s %d %8phC post gidpn\n",
  1304. __func__, __LINE__, fcport->port_name);
  1305. qla24xx_post_gidpn_work(vha, fcport);
  1306. return;
  1307. }
  1308. qla24xx_fcport_handle_login(vha, fcport);
  1309. }
  1310. void qla_handle_els_plogi_done(scsi_qla_host_t *vha, struct event_arg *ea)
  1311. {
  1312. ql_dbg(ql_dbg_disc, vha, 0x2118,
  1313. "%s %d %8phC post PRLI\n",
  1314. __func__, __LINE__, ea->fcport->port_name);
  1315. qla24xx_post_prli_work(vha, ea->fcport);
  1316. }
  1317. void qla2x00_fcport_event_handler(scsi_qla_host_t *vha, struct event_arg *ea)
  1318. {
  1319. fc_port_t *f, *tf;
  1320. uint32_t id = 0, mask, rid;
  1321. unsigned long flags;
  1322. fc_port_t *fcport;
  1323. switch (ea->event) {
  1324. case FCME_RELOGIN:
  1325. if (test_bit(UNLOADING, &vha->dpc_flags))
  1326. return;
  1327. qla24xx_handle_relogin_event(vha, ea);
  1328. break;
  1329. case FCME_RSCN:
  1330. if (test_bit(UNLOADING, &vha->dpc_flags))
  1331. return;
  1332. switch (ea->id.b.rsvd_1) {
  1333. case RSCN_PORT_ADDR:
  1334. fcport = qla2x00_find_fcport_by_nportid
  1335. (vha, &ea->id, 1);
  1336. if (fcport)
  1337. fcport->rscn_rcvd = 1;
  1338. spin_lock_irqsave(&vha->work_lock, flags);
  1339. if (vha->scan.scan_flags == 0) {
  1340. ql_dbg(ql_dbg_disc, vha, 0xffff,
  1341. "%s: schedule\n", __func__);
  1342. vha->scan.scan_flags |= SF_QUEUED;
  1343. schedule_delayed_work(&vha->scan.scan_work, 5);
  1344. }
  1345. spin_unlock_irqrestore(&vha->work_lock, flags);
  1346. break;
  1347. case RSCN_AREA_ADDR:
  1348. case RSCN_DOM_ADDR:
  1349. if (ea->id.b.rsvd_1 == RSCN_AREA_ADDR) {
  1350. mask = 0xffff00;
  1351. ql_dbg(ql_dbg_async, vha, 0x5044,
  1352. "RSCN: Area 0x%06x was affected\n",
  1353. ea->id.b24);
  1354. } else {
  1355. mask = 0xff0000;
  1356. ql_dbg(ql_dbg_async, vha, 0x507a,
  1357. "RSCN: Domain 0x%06x was affected\n",
  1358. ea->id.b24);
  1359. }
  1360. rid = ea->id.b24 & mask;
  1361. list_for_each_entry_safe(f, tf, &vha->vp_fcports,
  1362. list) {
  1363. id = f->d_id.b24 & mask;
  1364. if (rid == id) {
  1365. ea->fcport = f;
  1366. qla24xx_handle_rscn_event(f, ea);
  1367. }
  1368. }
  1369. break;
  1370. case RSCN_FAB_ADDR:
  1371. default:
  1372. ql_log(ql_log_warn, vha, 0xd045,
  1373. "RSCN: Fabric was affected. Addr format %d\n",
  1374. ea->id.b.rsvd_1);
  1375. qla2x00_mark_all_devices_lost(vha, 1);
  1376. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1377. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  1378. }
  1379. break;
  1380. case FCME_GIDPN_DONE:
  1381. qla24xx_handle_gidpn_event(vha, ea);
  1382. break;
  1383. case FCME_GNL_DONE:
  1384. qla24xx_handle_gnl_done_event(vha, ea);
  1385. break;
  1386. case FCME_GPSC_DONE:
  1387. qla24xx_handle_gpsc_event(vha, ea);
  1388. break;
  1389. case FCME_PLOGI_DONE: /* Initiator side sent LLIOCB */
  1390. qla24xx_handle_plogi_done_event(vha, ea);
  1391. break;
  1392. case FCME_PRLI_DONE:
  1393. qla24xx_handle_prli_done_event(vha, ea);
  1394. break;
  1395. case FCME_GPDB_DONE:
  1396. qla24xx_handle_gpdb_event(vha, ea);
  1397. break;
  1398. case FCME_GPNID_DONE:
  1399. qla24xx_handle_gpnid_event(vha, ea);
  1400. break;
  1401. case FCME_GFFID_DONE:
  1402. qla24xx_handle_gffid_event(vha, ea);
  1403. break;
  1404. case FCME_ADISC_DONE:
  1405. qla24xx_handle_adisc_event(vha, ea);
  1406. break;
  1407. case FCME_GNNID_DONE:
  1408. qla24xx_handle_gnnid_event(vha, ea);
  1409. break;
  1410. case FCME_GFPNID_DONE:
  1411. qla24xx_handle_gfpnid_event(vha, ea);
  1412. break;
  1413. case FCME_ELS_PLOGI_DONE:
  1414. qla_handle_els_plogi_done(vha, ea);
  1415. break;
  1416. default:
  1417. BUG_ON(1);
  1418. break;
  1419. }
  1420. }
  1421. static void
  1422. qla2x00_tmf_iocb_timeout(void *data)
  1423. {
  1424. srb_t *sp = data;
  1425. struct srb_iocb *tmf = &sp->u.iocb_cmd;
  1426. tmf->u.tmf.comp_status = CS_TIMEOUT;
  1427. complete(&tmf->u.tmf.comp);
  1428. }
  1429. static void
  1430. qla2x00_tmf_sp_done(void *ptr, int res)
  1431. {
  1432. srb_t *sp = ptr;
  1433. struct srb_iocb *tmf = &sp->u.iocb_cmd;
  1434. complete(&tmf->u.tmf.comp);
  1435. }
  1436. int
  1437. qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint32_t lun,
  1438. uint32_t tag)
  1439. {
  1440. struct scsi_qla_host *vha = fcport->vha;
  1441. struct srb_iocb *tm_iocb;
  1442. srb_t *sp;
  1443. int rval = QLA_FUNCTION_FAILED;
  1444. sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
  1445. if (!sp)
  1446. goto done;
  1447. tm_iocb = &sp->u.iocb_cmd;
  1448. sp->type = SRB_TM_CMD;
  1449. sp->name = "tmf";
  1450. tm_iocb->timeout = qla2x00_tmf_iocb_timeout;
  1451. init_completion(&tm_iocb->u.tmf.comp);
  1452. qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
  1453. tm_iocb->u.tmf.flags = flags;
  1454. tm_iocb->u.tmf.lun = lun;
  1455. tm_iocb->u.tmf.data = tag;
  1456. sp->done = qla2x00_tmf_sp_done;
  1457. ql_dbg(ql_dbg_taskm, vha, 0x802f,
  1458. "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
  1459. sp->handle, fcport->loop_id, fcport->d_id.b.domain,
  1460. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  1461. rval = qla2x00_start_sp(sp);
  1462. if (rval != QLA_SUCCESS)
  1463. goto done_free_sp;
  1464. wait_for_completion(&tm_iocb->u.tmf.comp);
  1465. rval = tm_iocb->u.tmf.data;
  1466. if (rval != QLA_SUCCESS) {
  1467. ql_log(ql_log_warn, vha, 0x8030,
  1468. "TM IOCB failed (%x).\n", rval);
  1469. }
  1470. if (!test_bit(UNLOADING, &vha->dpc_flags) && !IS_QLAFX00(vha->hw)) {
  1471. flags = tm_iocb->u.tmf.flags;
  1472. lun = (uint16_t)tm_iocb->u.tmf.lun;
  1473. /* Issue Marker IOCB */
  1474. qla2x00_marker(vha, vha->hw->req_q_map[0],
  1475. vha->hw->rsp_q_map[0], fcport->loop_id, lun,
  1476. flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
  1477. }
  1478. done_free_sp:
  1479. sp->free(sp);
  1480. fcport->flags &= ~FCF_ASYNC_SENT;
  1481. done:
  1482. return rval;
  1483. }
  1484. static void
  1485. qla24xx_abort_iocb_timeout(void *data)
  1486. {
  1487. srb_t *sp = data;
  1488. struct srb_iocb *abt = &sp->u.iocb_cmd;
  1489. abt->u.abt.comp_status = CS_TIMEOUT;
  1490. sp->done(sp, QLA_FUNCTION_TIMEOUT);
  1491. }
  1492. static void
  1493. qla24xx_abort_sp_done(void *ptr, int res)
  1494. {
  1495. srb_t *sp = ptr;
  1496. struct srb_iocb *abt = &sp->u.iocb_cmd;
  1497. if (del_timer(&sp->u.iocb_cmd.timer)) {
  1498. if (sp->flags & SRB_WAKEUP_ON_COMP)
  1499. complete(&abt->u.abt.comp);
  1500. else
  1501. sp->free(sp);
  1502. }
  1503. }
  1504. int
  1505. qla24xx_async_abort_cmd(srb_t *cmd_sp, bool wait)
  1506. {
  1507. scsi_qla_host_t *vha = cmd_sp->vha;
  1508. struct srb_iocb *abt_iocb;
  1509. srb_t *sp;
  1510. int rval = QLA_FUNCTION_FAILED;
  1511. sp = qla2xxx_get_qpair_sp(cmd_sp->qpair, cmd_sp->fcport, GFP_KERNEL);
  1512. if (!sp)
  1513. goto done;
  1514. abt_iocb = &sp->u.iocb_cmd;
  1515. sp->type = SRB_ABT_CMD;
  1516. sp->name = "abort";
  1517. sp->qpair = cmd_sp->qpair;
  1518. if (wait)
  1519. sp->flags = SRB_WAKEUP_ON_COMP;
  1520. abt_iocb->timeout = qla24xx_abort_iocb_timeout;
  1521. init_completion(&abt_iocb->u.abt.comp);
  1522. /* FW can send 2 x ABTS's timeout/20s */
  1523. qla2x00_init_timer(sp, 42);
  1524. abt_iocb->u.abt.cmd_hndl = cmd_sp->handle;
  1525. abt_iocb->u.abt.req_que_no = cpu_to_le16(cmd_sp->qpair->req->id);
  1526. sp->done = qla24xx_abort_sp_done;
  1527. ql_dbg(ql_dbg_async, vha, 0x507c,
  1528. "Abort command issued - hdl=%x, type=%x\n",
  1529. cmd_sp->handle, cmd_sp->type);
  1530. rval = qla2x00_start_sp(sp);
  1531. if (rval != QLA_SUCCESS)
  1532. goto done_free_sp;
  1533. if (wait) {
  1534. wait_for_completion(&abt_iocb->u.abt.comp);
  1535. rval = abt_iocb->u.abt.comp_status == CS_COMPLETE ?
  1536. QLA_SUCCESS : QLA_FUNCTION_FAILED;
  1537. } else {
  1538. goto done;
  1539. }
  1540. done_free_sp:
  1541. sp->free(sp);
  1542. done:
  1543. return rval;
  1544. }
  1545. int
  1546. qla24xx_async_abort_command(srb_t *sp)
  1547. {
  1548. unsigned long flags = 0;
  1549. uint32_t handle;
  1550. fc_port_t *fcport = sp->fcport;
  1551. struct scsi_qla_host *vha = fcport->vha;
  1552. struct qla_hw_data *ha = vha->hw;
  1553. struct req_que *req = vha->req;
  1554. if (vha->flags.qpairs_available && sp->qpair)
  1555. req = sp->qpair->req;
  1556. spin_lock_irqsave(&ha->hardware_lock, flags);
  1557. for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
  1558. if (req->outstanding_cmds[handle] == sp)
  1559. break;
  1560. }
  1561. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1562. if (handle == req->num_outstanding_cmds) {
  1563. /* Command not found. */
  1564. return QLA_FUNCTION_FAILED;
  1565. }
  1566. if (sp->type == SRB_FXIOCB_DCMD)
  1567. return qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
  1568. FXDISC_ABORT_IOCTL);
  1569. return qla24xx_async_abort_cmd(sp, true);
  1570. }
  1571. static void
  1572. qla24xx_handle_prli_done_event(struct scsi_qla_host *vha, struct event_arg *ea)
  1573. {
  1574. switch (ea->data[0]) {
  1575. case MBS_COMMAND_COMPLETE:
  1576. ql_dbg(ql_dbg_disc, vha, 0x2118,
  1577. "%s %d %8phC post gpdb\n",
  1578. __func__, __LINE__, ea->fcport->port_name);
  1579. ea->fcport->chip_reset = vha->hw->base_qpair->chip_reset;
  1580. ea->fcport->logout_on_delete = 1;
  1581. qla24xx_post_gpdb_work(vha, ea->fcport, 0);
  1582. break;
  1583. default:
  1584. if ((ea->iop[0] == LSC_SCODE_ELS_REJECT) &&
  1585. (ea->iop[1] == 0x50000)) { /* reson 5=busy expl:0x0 */
  1586. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  1587. ea->fcport->fw_login_state = DSC_LS_PLOGI_COMP;
  1588. break;
  1589. }
  1590. if (ea->fcport->n2n_flag) {
  1591. ql_dbg(ql_dbg_disc, vha, 0x2118,
  1592. "%s %d %8phC post fc4 prli\n",
  1593. __func__, __LINE__, ea->fcport->port_name);
  1594. ea->fcport->fc4f_nvme = 0;
  1595. ea->fcport->n2n_flag = 0;
  1596. qla24xx_post_prli_work(vha, ea->fcport);
  1597. }
  1598. ql_dbg(ql_dbg_disc, vha, 0x2119,
  1599. "%s %d %8phC unhandle event of %x\n",
  1600. __func__, __LINE__, ea->fcport->port_name, ea->data[0]);
  1601. break;
  1602. }
  1603. }
  1604. static void
  1605. qla24xx_handle_plogi_done_event(struct scsi_qla_host *vha, struct event_arg *ea)
  1606. {
  1607. port_id_t cid; /* conflict Nport id */
  1608. u16 lid;
  1609. struct fc_port *conflict_fcport;
  1610. unsigned long flags;
  1611. struct fc_port *fcport = ea->fcport;
  1612. ql_dbg(ql_dbg_disc, vha, 0xffff,
  1613. "%s %8phC DS %d LS %d rc %d login %d|%d rscn %d|%d data %x|%x iop %x|%x\n",
  1614. __func__, fcport->port_name, fcport->disc_state,
  1615. fcport->fw_login_state, ea->rc, ea->sp->gen2, fcport->login_gen,
  1616. ea->sp->gen2, fcport->rscn_gen|ea->sp->gen1,
  1617. ea->data[0], ea->data[1], ea->iop[0], ea->iop[1]);
  1618. if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
  1619. (fcport->fw_login_state == DSC_LS_PRLI_PEND)) {
  1620. ql_dbg(ql_dbg_disc, vha, 0x20ea,
  1621. "%s %d %8phC Remote is trying to login\n",
  1622. __func__, __LINE__, fcport->port_name);
  1623. return;
  1624. }
  1625. if ((fcport->disc_state == DSC_DELETE_PEND) ||
  1626. (fcport->disc_state == DSC_DELETED)) {
  1627. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  1628. return;
  1629. }
  1630. if (ea->sp->gen2 != fcport->login_gen) {
  1631. /* target side must have changed it. */
  1632. ql_dbg(ql_dbg_disc, vha, 0x20d3,
  1633. "%s %8phC generation changed\n",
  1634. __func__, fcport->port_name);
  1635. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  1636. return;
  1637. } else if (ea->sp->gen1 != fcport->rscn_gen) {
  1638. ql_dbg(ql_dbg_disc, vha, 0x20d4, "%s %d %8phC post gidpn\n",
  1639. __func__, __LINE__, fcport->port_name);
  1640. qla24xx_post_gidpn_work(vha, fcport);
  1641. return;
  1642. }
  1643. switch (ea->data[0]) {
  1644. case MBS_COMMAND_COMPLETE:
  1645. /*
  1646. * Driver must validate login state - If PRLI not complete,
  1647. * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
  1648. * requests.
  1649. */
  1650. if (ea->fcport->fc4f_nvme) {
  1651. ql_dbg(ql_dbg_disc, vha, 0x2117,
  1652. "%s %d %8phC post prli\n",
  1653. __func__, __LINE__, ea->fcport->port_name);
  1654. qla24xx_post_prli_work(vha, ea->fcport);
  1655. } else {
  1656. ql_dbg(ql_dbg_disc, vha, 0x20ea,
  1657. "%s %d %8phC LoopID 0x%x in use with %06x. post gnl\n",
  1658. __func__, __LINE__, ea->fcport->port_name,
  1659. ea->fcport->loop_id, ea->fcport->d_id.b24);
  1660. set_bit(ea->fcport->loop_id, vha->hw->loop_id_map);
  1661. spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
  1662. ea->fcport->chip_reset = vha->hw->base_qpair->chip_reset;
  1663. ea->fcport->logout_on_delete = 1;
  1664. ea->fcport->send_els_logo = 0;
  1665. ea->fcport->fw_login_state = DSC_LS_PRLI_COMP;
  1666. spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
  1667. qla24xx_post_gpdb_work(vha, ea->fcport, 0);
  1668. }
  1669. break;
  1670. case MBS_COMMAND_ERROR:
  1671. ql_dbg(ql_dbg_disc, vha, 0x20eb, "%s %d %8phC cmd error %x\n",
  1672. __func__, __LINE__, ea->fcport->port_name, ea->data[1]);
  1673. ea->fcport->flags &= ~FCF_ASYNC_SENT;
  1674. ea->fcport->disc_state = DSC_LOGIN_FAILED;
  1675. if (ea->data[1] & QLA_LOGIO_LOGIN_RETRIED)
  1676. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  1677. else
  1678. qla2x00_mark_device_lost(vha, ea->fcport, 1, 0);
  1679. break;
  1680. case MBS_LOOP_ID_USED:
  1681. /* data[1] = IO PARAM 1 = nport ID */
  1682. cid.b.domain = (ea->iop[1] >> 16) & 0xff;
  1683. cid.b.area = (ea->iop[1] >> 8) & 0xff;
  1684. cid.b.al_pa = ea->iop[1] & 0xff;
  1685. cid.b.rsvd_1 = 0;
  1686. ql_dbg(ql_dbg_disc, vha, 0x20ec,
  1687. "%s %d %8phC lid %#x in use with pid %06x post gnl\n",
  1688. __func__, __LINE__, ea->fcport->port_name,
  1689. ea->fcport->loop_id, cid.b24);
  1690. set_bit(ea->fcport->loop_id, vha->hw->loop_id_map);
  1691. ea->fcport->loop_id = FC_NO_LOOP_ID;
  1692. qla24xx_post_gnl_work(vha, ea->fcport);
  1693. break;
  1694. case MBS_PORT_ID_USED:
  1695. lid = ea->iop[1] & 0xffff;
  1696. qlt_find_sess_invalidate_other(vha,
  1697. wwn_to_u64(ea->fcport->port_name),
  1698. ea->fcport->d_id, lid, &conflict_fcport);
  1699. if (conflict_fcport) {
  1700. /*
  1701. * Another fcport share the same loop_id/nport id.
  1702. * Conflict fcport needs to finish cleanup before this
  1703. * fcport can proceed to login.
  1704. */
  1705. conflict_fcport->conflict = ea->fcport;
  1706. ea->fcport->login_pause = 1;
  1707. ql_dbg(ql_dbg_disc, vha, 0x20ed,
  1708. "%s %d %8phC NPortId %06x inuse with loopid 0x%x. post gidpn\n",
  1709. __func__, __LINE__, ea->fcport->port_name,
  1710. ea->fcport->d_id.b24, lid);
  1711. qla2x00_clear_loop_id(ea->fcport);
  1712. qla24xx_post_gidpn_work(vha, ea->fcport);
  1713. } else {
  1714. ql_dbg(ql_dbg_disc, vha, 0x20ed,
  1715. "%s %d %8phC NPortId %06x inuse with loopid 0x%x. sched delete\n",
  1716. __func__, __LINE__, ea->fcport->port_name,
  1717. ea->fcport->d_id.b24, lid);
  1718. qla2x00_clear_loop_id(ea->fcport);
  1719. set_bit(lid, vha->hw->loop_id_map);
  1720. ea->fcport->loop_id = lid;
  1721. ea->fcport->keep_nport_handle = 0;
  1722. qlt_schedule_sess_for_deletion(ea->fcport);
  1723. }
  1724. break;
  1725. }
  1726. return;
  1727. }
  1728. void
  1729. qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
  1730. uint16_t *data)
  1731. {
  1732. qlt_logo_completion_handler(fcport, data[0]);
  1733. fcport->login_gen++;
  1734. fcport->flags &= ~FCF_ASYNC_ACTIVE;
  1735. return;
  1736. }
  1737. void
  1738. qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
  1739. uint16_t *data)
  1740. {
  1741. fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
  1742. if (data[0] == MBS_COMMAND_COMPLETE) {
  1743. qla2x00_update_fcport(vha, fcport);
  1744. return;
  1745. }
  1746. /* Retry login. */
  1747. if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
  1748. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  1749. else
  1750. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  1751. return;
  1752. }
  1753. /****************************************************************************/
  1754. /* QLogic ISP2x00 Hardware Support Functions. */
  1755. /****************************************************************************/
  1756. static int
  1757. qla83xx_nic_core_fw_load(scsi_qla_host_t *vha)
  1758. {
  1759. int rval = QLA_SUCCESS;
  1760. struct qla_hw_data *ha = vha->hw;
  1761. uint32_t idc_major_ver, idc_minor_ver;
  1762. uint16_t config[4];
  1763. qla83xx_idc_lock(vha, 0);
  1764. /* SV: TODO: Assign initialization timeout from
  1765. * flash-info / other param
  1766. */
  1767. ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT;
  1768. ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT;
  1769. /* Set our fcoe function presence */
  1770. if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) {
  1771. ql_dbg(ql_dbg_p3p, vha, 0xb077,
  1772. "Error while setting DRV-Presence.\n");
  1773. rval = QLA_FUNCTION_FAILED;
  1774. goto exit;
  1775. }
  1776. /* Decide the reset ownership */
  1777. qla83xx_reset_ownership(vha);
  1778. /*
  1779. * On first protocol driver load:
  1780. * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery
  1781. * register.
  1782. * Others: Check compatibility with current IDC Major version.
  1783. */
  1784. qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver);
  1785. if (ha->flags.nic_core_reset_owner) {
  1786. /* Set IDC Major version */
  1787. idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION;
  1788. qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver);
  1789. /* Clearing IDC-Lock-Recovery register */
  1790. qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0);
  1791. } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) {
  1792. /*
  1793. * Clear further IDC participation if we are not compatible with
  1794. * the current IDC Major Version.
  1795. */
  1796. ql_log(ql_log_warn, vha, 0xb07d,
  1797. "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n",
  1798. idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION);
  1799. __qla83xx_clear_drv_presence(vha);
  1800. rval = QLA_FUNCTION_FAILED;
  1801. goto exit;
  1802. }
  1803. /* Each function sets its supported Minor version. */
  1804. qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver);
  1805. idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2));
  1806. qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver);
  1807. if (ha->flags.nic_core_reset_owner) {
  1808. memset(config, 0, sizeof(config));
  1809. if (!qla81xx_get_port_config(vha, config))
  1810. qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
  1811. QLA8XXX_DEV_READY);
  1812. }
  1813. rval = qla83xx_idc_state_handler(vha);
  1814. exit:
  1815. qla83xx_idc_unlock(vha, 0);
  1816. return rval;
  1817. }
  1818. /*
  1819. * qla2x00_initialize_adapter
  1820. * Initialize board.
  1821. *
  1822. * Input:
  1823. * ha = adapter block pointer.
  1824. *
  1825. * Returns:
  1826. * 0 = success
  1827. */
  1828. int
  1829. qla2x00_initialize_adapter(scsi_qla_host_t *vha)
  1830. {
  1831. int rval;
  1832. struct qla_hw_data *ha = vha->hw;
  1833. struct req_que *req = ha->req_q_map[0];
  1834. memset(&vha->qla_stats, 0, sizeof(vha->qla_stats));
  1835. memset(&vha->fc_host_stat, 0, sizeof(vha->fc_host_stat));
  1836. /* Clear adapter flags. */
  1837. vha->flags.online = 0;
  1838. ha->flags.chip_reset_done = 0;
  1839. vha->flags.reset_active = 0;
  1840. ha->flags.pci_channel_io_perm_failure = 0;
  1841. ha->flags.eeh_busy = 0;
  1842. vha->qla_stats.jiffies_at_last_reset = get_jiffies_64();
  1843. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  1844. atomic_set(&vha->loop_state, LOOP_DOWN);
  1845. vha->device_flags = DFLG_NO_CABLE;
  1846. vha->dpc_flags = 0;
  1847. vha->flags.management_server_logged_in = 0;
  1848. vha->marker_needed = 0;
  1849. ha->isp_abort_cnt = 0;
  1850. ha->beacon_blink_led = 0;
  1851. set_bit(0, ha->req_qid_map);
  1852. set_bit(0, ha->rsp_qid_map);
  1853. ql_dbg(ql_dbg_init, vha, 0x0040,
  1854. "Configuring PCI space...\n");
  1855. rval = ha->isp_ops->pci_config(vha);
  1856. if (rval) {
  1857. ql_log(ql_log_warn, vha, 0x0044,
  1858. "Unable to configure PCI space.\n");
  1859. return (rval);
  1860. }
  1861. ha->isp_ops->reset_chip(vha);
  1862. rval = qla2xxx_get_flash_info(vha);
  1863. if (rval) {
  1864. ql_log(ql_log_fatal, vha, 0x004f,
  1865. "Unable to validate FLASH data.\n");
  1866. return rval;
  1867. }
  1868. if (IS_QLA8044(ha)) {
  1869. qla8044_read_reset_template(vha);
  1870. /* NOTE: If ql2xdontresethba==1, set IDC_CTRL DONTRESET_BIT0.
  1871. * If DONRESET_BIT0 is set, drivers should not set dev_state
  1872. * to NEED_RESET. But if NEED_RESET is set, drivers should
  1873. * should honor the reset. */
  1874. if (ql2xdontresethba == 1)
  1875. qla8044_set_idc_dontreset(vha);
  1876. }
  1877. ha->isp_ops->get_flash_version(vha, req->ring);
  1878. ql_dbg(ql_dbg_init, vha, 0x0061,
  1879. "Configure NVRAM parameters...\n");
  1880. ha->isp_ops->nvram_config(vha);
  1881. if (ha->flags.disable_serdes) {
  1882. /* Mask HBA via NVRAM settings? */
  1883. ql_log(ql_log_info, vha, 0x0077,
  1884. "Masking HBA WWPN %8phN (via NVRAM).\n", vha->port_name);
  1885. return QLA_FUNCTION_FAILED;
  1886. }
  1887. ql_dbg(ql_dbg_init, vha, 0x0078,
  1888. "Verifying loaded RISC code...\n");
  1889. if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
  1890. rval = ha->isp_ops->chip_diag(vha);
  1891. if (rval)
  1892. return (rval);
  1893. rval = qla2x00_setup_chip(vha);
  1894. if (rval)
  1895. return (rval);
  1896. }
  1897. if (IS_QLA84XX(ha)) {
  1898. ha->cs84xx = qla84xx_get_chip(vha);
  1899. if (!ha->cs84xx) {
  1900. ql_log(ql_log_warn, vha, 0x00d0,
  1901. "Unable to configure ISP84XX.\n");
  1902. return QLA_FUNCTION_FAILED;
  1903. }
  1904. }
  1905. if (qla_ini_mode_enabled(vha) || qla_dual_mode_enabled(vha))
  1906. rval = qla2x00_init_rings(vha);
  1907. ha->flags.chip_reset_done = 1;
  1908. if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
  1909. /* Issue verify 84xx FW IOCB to complete 84xx initialization */
  1910. rval = qla84xx_init_chip(vha);
  1911. if (rval != QLA_SUCCESS) {
  1912. ql_log(ql_log_warn, vha, 0x00d4,
  1913. "Unable to initialize ISP84XX.\n");
  1914. qla84xx_put_chip(vha);
  1915. }
  1916. }
  1917. /* Load the NIC Core f/w if we are the first protocol driver. */
  1918. if (IS_QLA8031(ha)) {
  1919. rval = qla83xx_nic_core_fw_load(vha);
  1920. if (rval)
  1921. ql_log(ql_log_warn, vha, 0x0124,
  1922. "Error in initializing NIC Core f/w.\n");
  1923. }
  1924. if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
  1925. qla24xx_read_fcp_prio_cfg(vha);
  1926. if (IS_P3P_TYPE(ha))
  1927. qla82xx_set_driver_version(vha, QLA2XXX_VERSION);
  1928. else
  1929. qla25xx_set_driver_version(vha, QLA2XXX_VERSION);
  1930. return (rval);
  1931. }
  1932. /**
  1933. * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
  1934. * @vha: HA context
  1935. *
  1936. * Returns 0 on success.
  1937. */
  1938. int
  1939. qla2100_pci_config(scsi_qla_host_t *vha)
  1940. {
  1941. uint16_t w;
  1942. unsigned long flags;
  1943. struct qla_hw_data *ha = vha->hw;
  1944. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1945. pci_set_master(ha->pdev);
  1946. pci_try_set_mwi(ha->pdev);
  1947. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  1948. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  1949. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  1950. pci_disable_rom(ha->pdev);
  1951. /* Get PCI bus information. */
  1952. spin_lock_irqsave(&ha->hardware_lock, flags);
  1953. ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
  1954. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1955. return QLA_SUCCESS;
  1956. }
  1957. /**
  1958. * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
  1959. * @vha: HA context
  1960. *
  1961. * Returns 0 on success.
  1962. */
  1963. int
  1964. qla2300_pci_config(scsi_qla_host_t *vha)
  1965. {
  1966. uint16_t w;
  1967. unsigned long flags = 0;
  1968. uint32_t cnt;
  1969. struct qla_hw_data *ha = vha->hw;
  1970. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1971. pci_set_master(ha->pdev);
  1972. pci_try_set_mwi(ha->pdev);
  1973. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  1974. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  1975. if (IS_QLA2322(ha) || IS_QLA6322(ha))
  1976. w &= ~PCI_COMMAND_INTX_DISABLE;
  1977. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  1978. /*
  1979. * If this is a 2300 card and not 2312, reset the
  1980. * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
  1981. * the 2310 also reports itself as a 2300 so we need to get the
  1982. * fb revision level -- a 6 indicates it really is a 2300 and
  1983. * not a 2310.
  1984. */
  1985. if (IS_QLA2300(ha)) {
  1986. spin_lock_irqsave(&ha->hardware_lock, flags);
  1987. /* Pause RISC. */
  1988. WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
  1989. for (cnt = 0; cnt < 30000; cnt++) {
  1990. if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
  1991. break;
  1992. udelay(10);
  1993. }
  1994. /* Select FPM registers. */
  1995. WRT_REG_WORD(&reg->ctrl_status, 0x20);
  1996. RD_REG_WORD(&reg->ctrl_status);
  1997. /* Get the fb rev level */
  1998. ha->fb_rev = RD_FB_CMD_REG(ha, reg);
  1999. if (ha->fb_rev == FPM_2300)
  2000. pci_clear_mwi(ha->pdev);
  2001. /* Deselect FPM registers. */
  2002. WRT_REG_WORD(&reg->ctrl_status, 0x0);
  2003. RD_REG_WORD(&reg->ctrl_status);
  2004. /* Release RISC module. */
  2005. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  2006. for (cnt = 0; cnt < 30000; cnt++) {
  2007. if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
  2008. break;
  2009. udelay(10);
  2010. }
  2011. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2012. }
  2013. pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
  2014. pci_disable_rom(ha->pdev);
  2015. /* Get PCI bus information. */
  2016. spin_lock_irqsave(&ha->hardware_lock, flags);
  2017. ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
  2018. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2019. return QLA_SUCCESS;
  2020. }
  2021. /**
  2022. * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
  2023. * @vha: HA context
  2024. *
  2025. * Returns 0 on success.
  2026. */
  2027. int
  2028. qla24xx_pci_config(scsi_qla_host_t *vha)
  2029. {
  2030. uint16_t w;
  2031. unsigned long flags = 0;
  2032. struct qla_hw_data *ha = vha->hw;
  2033. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  2034. pci_set_master(ha->pdev);
  2035. pci_try_set_mwi(ha->pdev);
  2036. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  2037. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  2038. w &= ~PCI_COMMAND_INTX_DISABLE;
  2039. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  2040. pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
  2041. /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
  2042. if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
  2043. pcix_set_mmrbc(ha->pdev, 2048);
  2044. /* PCIe -- adjust Maximum Read Request Size (2048). */
  2045. if (pci_is_pcie(ha->pdev))
  2046. pcie_set_readrq(ha->pdev, 4096);
  2047. pci_disable_rom(ha->pdev);
  2048. ha->chip_revision = ha->pdev->revision;
  2049. /* Get PCI bus information. */
  2050. spin_lock_irqsave(&ha->hardware_lock, flags);
  2051. ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
  2052. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2053. return QLA_SUCCESS;
  2054. }
  2055. /**
  2056. * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
  2057. * @vha: HA context
  2058. *
  2059. * Returns 0 on success.
  2060. */
  2061. int
  2062. qla25xx_pci_config(scsi_qla_host_t *vha)
  2063. {
  2064. uint16_t w;
  2065. struct qla_hw_data *ha = vha->hw;
  2066. pci_set_master(ha->pdev);
  2067. pci_try_set_mwi(ha->pdev);
  2068. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  2069. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  2070. w &= ~PCI_COMMAND_INTX_DISABLE;
  2071. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  2072. /* PCIe -- adjust Maximum Read Request Size (2048). */
  2073. if (pci_is_pcie(ha->pdev))
  2074. pcie_set_readrq(ha->pdev, 4096);
  2075. pci_disable_rom(ha->pdev);
  2076. ha->chip_revision = ha->pdev->revision;
  2077. return QLA_SUCCESS;
  2078. }
  2079. /**
  2080. * qla2x00_isp_firmware() - Choose firmware image.
  2081. * @vha: HA context
  2082. *
  2083. * Returns 0 on success.
  2084. */
  2085. static int
  2086. qla2x00_isp_firmware(scsi_qla_host_t *vha)
  2087. {
  2088. int rval;
  2089. uint16_t loop_id, topo, sw_cap;
  2090. uint8_t domain, area, al_pa;
  2091. struct qla_hw_data *ha = vha->hw;
  2092. /* Assume loading risc code */
  2093. rval = QLA_FUNCTION_FAILED;
  2094. if (ha->flags.disable_risc_code_load) {
  2095. ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
  2096. /* Verify checksum of loaded RISC code. */
  2097. rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
  2098. if (rval == QLA_SUCCESS) {
  2099. /* And, verify we are not in ROM code. */
  2100. rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
  2101. &area, &domain, &topo, &sw_cap);
  2102. }
  2103. }
  2104. if (rval)
  2105. ql_dbg(ql_dbg_init, vha, 0x007a,
  2106. "**** Load RISC code ****.\n");
  2107. return (rval);
  2108. }
  2109. /**
  2110. * qla2x00_reset_chip() - Reset ISP chip.
  2111. * @vha: HA context
  2112. *
  2113. * Returns 0 on success.
  2114. */
  2115. void
  2116. qla2x00_reset_chip(scsi_qla_host_t *vha)
  2117. {
  2118. unsigned long flags = 0;
  2119. struct qla_hw_data *ha = vha->hw;
  2120. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  2121. uint32_t cnt;
  2122. uint16_t cmd;
  2123. if (unlikely(pci_channel_offline(ha->pdev)))
  2124. return;
  2125. ha->isp_ops->disable_intrs(ha);
  2126. spin_lock_irqsave(&ha->hardware_lock, flags);
  2127. /* Turn off master enable */
  2128. cmd = 0;
  2129. pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
  2130. cmd &= ~PCI_COMMAND_MASTER;
  2131. pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
  2132. if (!IS_QLA2100(ha)) {
  2133. /* Pause RISC. */
  2134. WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
  2135. if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
  2136. for (cnt = 0; cnt < 30000; cnt++) {
  2137. if ((RD_REG_WORD(&reg->hccr) &
  2138. HCCR_RISC_PAUSE) != 0)
  2139. break;
  2140. udelay(100);
  2141. }
  2142. } else {
  2143. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  2144. udelay(10);
  2145. }
  2146. /* Select FPM registers. */
  2147. WRT_REG_WORD(&reg->ctrl_status, 0x20);
  2148. RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
  2149. /* FPM Soft Reset. */
  2150. WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
  2151. RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
  2152. /* Toggle Fpm Reset. */
  2153. if (!IS_QLA2200(ha)) {
  2154. WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
  2155. RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
  2156. }
  2157. /* Select frame buffer registers. */
  2158. WRT_REG_WORD(&reg->ctrl_status, 0x10);
  2159. RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
  2160. /* Reset frame buffer FIFOs. */
  2161. if (IS_QLA2200(ha)) {
  2162. WRT_FB_CMD_REG(ha, reg, 0xa000);
  2163. RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
  2164. } else {
  2165. WRT_FB_CMD_REG(ha, reg, 0x00fc);
  2166. /* Read back fb_cmd until zero or 3 seconds max */
  2167. for (cnt = 0; cnt < 3000; cnt++) {
  2168. if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
  2169. break;
  2170. udelay(100);
  2171. }
  2172. }
  2173. /* Select RISC module registers. */
  2174. WRT_REG_WORD(&reg->ctrl_status, 0);
  2175. RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
  2176. /* Reset RISC processor. */
  2177. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  2178. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  2179. /* Release RISC processor. */
  2180. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  2181. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  2182. }
  2183. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  2184. WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
  2185. /* Reset ISP chip. */
  2186. WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
  2187. /* Wait for RISC to recover from reset. */
  2188. if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
  2189. /*
  2190. * It is necessary to for a delay here since the card doesn't
  2191. * respond to PCI reads during a reset. On some architectures
  2192. * this will result in an MCA.
  2193. */
  2194. udelay(20);
  2195. for (cnt = 30000; cnt; cnt--) {
  2196. if ((RD_REG_WORD(&reg->ctrl_status) &
  2197. CSR_ISP_SOFT_RESET) == 0)
  2198. break;
  2199. udelay(100);
  2200. }
  2201. } else
  2202. udelay(10);
  2203. /* Reset RISC processor. */
  2204. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  2205. WRT_REG_WORD(&reg->semaphore, 0);
  2206. /* Release RISC processor. */
  2207. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  2208. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  2209. if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
  2210. for (cnt = 0; cnt < 30000; cnt++) {
  2211. if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
  2212. break;
  2213. udelay(100);
  2214. }
  2215. } else
  2216. udelay(100);
  2217. /* Turn on master enable */
  2218. cmd |= PCI_COMMAND_MASTER;
  2219. pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
  2220. /* Disable RISC pause on FPM parity error. */
  2221. if (!IS_QLA2100(ha)) {
  2222. WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
  2223. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  2224. }
  2225. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2226. }
  2227. /**
  2228. * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
  2229. * @vha: HA context
  2230. *
  2231. * Returns 0 on success.
  2232. */
  2233. static int
  2234. qla81xx_reset_mpi(scsi_qla_host_t *vha)
  2235. {
  2236. uint16_t mb[4] = {0x1010, 0, 1, 0};
  2237. if (!IS_QLA81XX(vha->hw))
  2238. return QLA_SUCCESS;
  2239. return qla81xx_write_mpi_register(vha, mb);
  2240. }
  2241. /**
  2242. * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
  2243. * @vha: HA context
  2244. *
  2245. * Returns 0 on success.
  2246. */
  2247. static inline int
  2248. qla24xx_reset_risc(scsi_qla_host_t *vha)
  2249. {
  2250. unsigned long flags = 0;
  2251. struct qla_hw_data *ha = vha->hw;
  2252. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  2253. uint32_t cnt;
  2254. uint16_t wd;
  2255. static int abts_cnt; /* ISP abort retry counts */
  2256. int rval = QLA_SUCCESS;
  2257. spin_lock_irqsave(&ha->hardware_lock, flags);
  2258. /* Reset RISC. */
  2259. WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
  2260. for (cnt = 0; cnt < 30000; cnt++) {
  2261. if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
  2262. break;
  2263. udelay(10);
  2264. }
  2265. if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE))
  2266. set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags);
  2267. ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017e,
  2268. "HCCR: 0x%x, Control Status %x, DMA active status:0x%x\n",
  2269. RD_REG_DWORD(&reg->hccr),
  2270. RD_REG_DWORD(&reg->ctrl_status),
  2271. (RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE));
  2272. WRT_REG_DWORD(&reg->ctrl_status,
  2273. CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
  2274. pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
  2275. udelay(100);
  2276. /* Wait for firmware to complete NVRAM accesses. */
  2277. RD_REG_WORD(&reg->mailbox0);
  2278. for (cnt = 10000; RD_REG_WORD(&reg->mailbox0) != 0 &&
  2279. rval == QLA_SUCCESS; cnt--) {
  2280. barrier();
  2281. if (cnt)
  2282. udelay(5);
  2283. else
  2284. rval = QLA_FUNCTION_TIMEOUT;
  2285. }
  2286. if (rval == QLA_SUCCESS)
  2287. set_bit(ISP_MBX_RDY, &ha->fw_dump_cap_flags);
  2288. ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017f,
  2289. "HCCR: 0x%x, MailBox0 Status 0x%x\n",
  2290. RD_REG_DWORD(&reg->hccr),
  2291. RD_REG_DWORD(&reg->mailbox0));
  2292. /* Wait for soft-reset to complete. */
  2293. RD_REG_DWORD(&reg->ctrl_status);
  2294. for (cnt = 0; cnt < 60; cnt++) {
  2295. barrier();
  2296. if ((RD_REG_DWORD(&reg->ctrl_status) &
  2297. CSRX_ISP_SOFT_RESET) == 0)
  2298. break;
  2299. udelay(5);
  2300. }
  2301. if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_ISP_SOFT_RESET))
  2302. set_bit(ISP_SOFT_RESET_CMPL, &ha->fw_dump_cap_flags);
  2303. ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015d,
  2304. "HCCR: 0x%x, Soft Reset status: 0x%x\n",
  2305. RD_REG_DWORD(&reg->hccr),
  2306. RD_REG_DWORD(&reg->ctrl_status));
  2307. /* If required, do an MPI FW reset now */
  2308. if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
  2309. if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
  2310. if (++abts_cnt < 5) {
  2311. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2312. set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
  2313. } else {
  2314. /*
  2315. * We exhausted the ISP abort retries. We have to
  2316. * set the board offline.
  2317. */
  2318. abts_cnt = 0;
  2319. vha->flags.online = 0;
  2320. }
  2321. }
  2322. }
  2323. WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
  2324. RD_REG_DWORD(&reg->hccr);
  2325. WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
  2326. RD_REG_DWORD(&reg->hccr);
  2327. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
  2328. RD_REG_DWORD(&reg->hccr);
  2329. RD_REG_WORD(&reg->mailbox0);
  2330. for (cnt = 60; RD_REG_WORD(&reg->mailbox0) != 0 &&
  2331. rval == QLA_SUCCESS; cnt--) {
  2332. barrier();
  2333. if (cnt)
  2334. udelay(5);
  2335. else
  2336. rval = QLA_FUNCTION_TIMEOUT;
  2337. }
  2338. if (rval == QLA_SUCCESS)
  2339. set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags);
  2340. ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015e,
  2341. "Host Risc 0x%x, mailbox0 0x%x\n",
  2342. RD_REG_DWORD(&reg->hccr),
  2343. RD_REG_WORD(&reg->mailbox0));
  2344. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2345. ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015f,
  2346. "Driver in %s mode\n",
  2347. IS_NOPOLLING_TYPE(ha) ? "Interrupt" : "Polling");
  2348. if (IS_NOPOLLING_TYPE(ha))
  2349. ha->isp_ops->enable_intrs(ha);
  2350. return rval;
  2351. }
  2352. static void
  2353. qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data)
  2354. {
  2355. struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
  2356. WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
  2357. *data = RD_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET);
  2358. }
  2359. static void
  2360. qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data)
  2361. {
  2362. struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
  2363. WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
  2364. WRT_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET, data);
  2365. }
  2366. static void
  2367. qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha)
  2368. {
  2369. uint32_t wd32 = 0;
  2370. uint delta_msec = 100;
  2371. uint elapsed_msec = 0;
  2372. uint timeout_msec;
  2373. ulong n;
  2374. if (vha->hw->pdev->subsystem_device != 0x0175 &&
  2375. vha->hw->pdev->subsystem_device != 0x0240)
  2376. return;
  2377. WRT_REG_DWORD(&vha->hw->iobase->isp24.hccr, HCCRX_SET_RISC_PAUSE);
  2378. udelay(100);
  2379. attempt:
  2380. timeout_msec = TIMEOUT_SEMAPHORE;
  2381. n = timeout_msec / delta_msec;
  2382. while (n--) {
  2383. qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET);
  2384. qla25xx_read_risc_sema_reg(vha, &wd32);
  2385. if (wd32 & RISC_SEMAPHORE)
  2386. break;
  2387. msleep(delta_msec);
  2388. elapsed_msec += delta_msec;
  2389. if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
  2390. goto force;
  2391. }
  2392. if (!(wd32 & RISC_SEMAPHORE))
  2393. goto force;
  2394. if (!(wd32 & RISC_SEMAPHORE_FORCE))
  2395. goto acquired;
  2396. qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR);
  2397. timeout_msec = TIMEOUT_SEMAPHORE_FORCE;
  2398. n = timeout_msec / delta_msec;
  2399. while (n--) {
  2400. qla25xx_read_risc_sema_reg(vha, &wd32);
  2401. if (!(wd32 & RISC_SEMAPHORE_FORCE))
  2402. break;
  2403. msleep(delta_msec);
  2404. elapsed_msec += delta_msec;
  2405. if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
  2406. goto force;
  2407. }
  2408. if (wd32 & RISC_SEMAPHORE_FORCE)
  2409. qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR);
  2410. goto attempt;
  2411. force:
  2412. qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET);
  2413. acquired:
  2414. return;
  2415. }
  2416. /**
  2417. * qla24xx_reset_chip() - Reset ISP24xx chip.
  2418. * @vha: HA context
  2419. *
  2420. * Returns 0 on success.
  2421. */
  2422. void
  2423. qla24xx_reset_chip(scsi_qla_host_t *vha)
  2424. {
  2425. struct qla_hw_data *ha = vha->hw;
  2426. if (pci_channel_offline(ha->pdev) &&
  2427. ha->flags.pci_channel_io_perm_failure) {
  2428. return;
  2429. }
  2430. ha->isp_ops->disable_intrs(ha);
  2431. qla25xx_manipulate_risc_semaphore(vha);
  2432. /* Perform RISC reset. */
  2433. qla24xx_reset_risc(vha);
  2434. }
  2435. /**
  2436. * qla2x00_chip_diag() - Test chip for proper operation.
  2437. * @vha: HA context
  2438. *
  2439. * Returns 0 on success.
  2440. */
  2441. int
  2442. qla2x00_chip_diag(scsi_qla_host_t *vha)
  2443. {
  2444. int rval;
  2445. struct qla_hw_data *ha = vha->hw;
  2446. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  2447. unsigned long flags = 0;
  2448. uint16_t data;
  2449. uint32_t cnt;
  2450. uint16_t mb[5];
  2451. struct req_que *req = ha->req_q_map[0];
  2452. /* Assume a failed state */
  2453. rval = QLA_FUNCTION_FAILED;
  2454. ql_dbg(ql_dbg_init, vha, 0x007b, "Testing device at %p.\n",
  2455. &reg->flash_address);
  2456. spin_lock_irqsave(&ha->hardware_lock, flags);
  2457. /* Reset ISP chip. */
  2458. WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
  2459. /*
  2460. * We need to have a delay here since the card will not respond while
  2461. * in reset causing an MCA on some architectures.
  2462. */
  2463. udelay(20);
  2464. data = qla2x00_debounce_register(&reg->ctrl_status);
  2465. for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
  2466. udelay(5);
  2467. data = RD_REG_WORD(&reg->ctrl_status);
  2468. barrier();
  2469. }
  2470. if (!cnt)
  2471. goto chip_diag_failed;
  2472. ql_dbg(ql_dbg_init, vha, 0x007c,
  2473. "Reset register cleared by chip reset.\n");
  2474. /* Reset RISC processor. */
  2475. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  2476. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  2477. /* Workaround for QLA2312 PCI parity error */
  2478. if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
  2479. data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
  2480. for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
  2481. udelay(5);
  2482. data = RD_MAILBOX_REG(ha, reg, 0);
  2483. barrier();
  2484. }
  2485. } else
  2486. udelay(10);
  2487. if (!cnt)
  2488. goto chip_diag_failed;
  2489. /* Check product ID of chip */
  2490. ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product ID of chip.\n");
  2491. mb[1] = RD_MAILBOX_REG(ha, reg, 1);
  2492. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  2493. mb[3] = RD_MAILBOX_REG(ha, reg, 3);
  2494. mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
  2495. if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
  2496. mb[3] != PROD_ID_3) {
  2497. ql_log(ql_log_warn, vha, 0x0062,
  2498. "Wrong product ID = 0x%x,0x%x,0x%x.\n",
  2499. mb[1], mb[2], mb[3]);
  2500. goto chip_diag_failed;
  2501. }
  2502. ha->product_id[0] = mb[1];
  2503. ha->product_id[1] = mb[2];
  2504. ha->product_id[2] = mb[3];
  2505. ha->product_id[3] = mb[4];
  2506. /* Adjust fw RISC transfer size */
  2507. if (req->length > 1024)
  2508. ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
  2509. else
  2510. ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
  2511. req->length;
  2512. if (IS_QLA2200(ha) &&
  2513. RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
  2514. /* Limit firmware transfer size with a 2200A */
  2515. ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
  2516. ha->device_type |= DT_ISP2200A;
  2517. ha->fw_transfer_size = 128;
  2518. }
  2519. /* Wrap Incoming Mailboxes Test. */
  2520. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2521. ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
  2522. rval = qla2x00_mbx_reg_test(vha);
  2523. if (rval)
  2524. ql_log(ql_log_warn, vha, 0x0080,
  2525. "Failed mailbox send register test.\n");
  2526. else
  2527. /* Flag a successful rval */
  2528. rval = QLA_SUCCESS;
  2529. spin_lock_irqsave(&ha->hardware_lock, flags);
  2530. chip_diag_failed:
  2531. if (rval)
  2532. ql_log(ql_log_info, vha, 0x0081,
  2533. "Chip diagnostics **** FAILED ****.\n");
  2534. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2535. return (rval);
  2536. }
  2537. /**
  2538. * qla24xx_chip_diag() - Test ISP24xx for proper operation.
  2539. * @vha: HA context
  2540. *
  2541. * Returns 0 on success.
  2542. */
  2543. int
  2544. qla24xx_chip_diag(scsi_qla_host_t *vha)
  2545. {
  2546. int rval;
  2547. struct qla_hw_data *ha = vha->hw;
  2548. struct req_que *req = ha->req_q_map[0];
  2549. if (IS_P3P_TYPE(ha))
  2550. return QLA_SUCCESS;
  2551. ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
  2552. rval = qla2x00_mbx_reg_test(vha);
  2553. if (rval) {
  2554. ql_log(ql_log_warn, vha, 0x0082,
  2555. "Failed mailbox send register test.\n");
  2556. } else {
  2557. /* Flag a successful rval */
  2558. rval = QLA_SUCCESS;
  2559. }
  2560. return rval;
  2561. }
  2562. static void
  2563. qla2x00_alloc_offload_mem(scsi_qla_host_t *vha)
  2564. {
  2565. int rval;
  2566. dma_addr_t tc_dma;
  2567. void *tc;
  2568. struct qla_hw_data *ha = vha->hw;
  2569. if (ha->eft) {
  2570. ql_dbg(ql_dbg_init, vha, 0x00bd,
  2571. "%s: Offload Mem is already allocated.\n",
  2572. __func__);
  2573. return;
  2574. }
  2575. if (IS_FWI2_CAPABLE(ha)) {
  2576. /* Allocate memory for Fibre Channel Event Buffer. */
  2577. if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
  2578. !IS_QLA27XX(ha))
  2579. goto try_eft;
  2580. if (ha->fce)
  2581. dma_free_coherent(&ha->pdev->dev,
  2582. FCE_SIZE, ha->fce, ha->fce_dma);
  2583. /* Allocate memory for Fibre Channel Event Buffer. */
  2584. tc = dma_zalloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
  2585. GFP_KERNEL);
  2586. if (!tc) {
  2587. ql_log(ql_log_warn, vha, 0x00be,
  2588. "Unable to allocate (%d KB) for FCE.\n",
  2589. FCE_SIZE / 1024);
  2590. goto try_eft;
  2591. }
  2592. rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
  2593. ha->fce_mb, &ha->fce_bufs);
  2594. if (rval) {
  2595. ql_log(ql_log_warn, vha, 0x00bf,
  2596. "Unable to initialize FCE (%d).\n", rval);
  2597. dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
  2598. tc_dma);
  2599. ha->flags.fce_enabled = 0;
  2600. goto try_eft;
  2601. }
  2602. ql_dbg(ql_dbg_init, vha, 0x00c0,
  2603. "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
  2604. ha->flags.fce_enabled = 1;
  2605. ha->fce_dma = tc_dma;
  2606. ha->fce = tc;
  2607. try_eft:
  2608. if (ha->eft)
  2609. dma_free_coherent(&ha->pdev->dev,
  2610. EFT_SIZE, ha->eft, ha->eft_dma);
  2611. /* Allocate memory for Extended Trace Buffer. */
  2612. tc = dma_zalloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
  2613. GFP_KERNEL);
  2614. if (!tc) {
  2615. ql_log(ql_log_warn, vha, 0x00c1,
  2616. "Unable to allocate (%d KB) for EFT.\n",
  2617. EFT_SIZE / 1024);
  2618. goto eft_err;
  2619. }
  2620. rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
  2621. if (rval) {
  2622. ql_log(ql_log_warn, vha, 0x00c2,
  2623. "Unable to initialize EFT (%d).\n", rval);
  2624. dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
  2625. tc_dma);
  2626. goto eft_err;
  2627. }
  2628. ql_dbg(ql_dbg_init, vha, 0x00c3,
  2629. "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
  2630. ha->eft_dma = tc_dma;
  2631. ha->eft = tc;
  2632. }
  2633. eft_err:
  2634. return;
  2635. }
  2636. void
  2637. qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
  2638. {
  2639. uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
  2640. eft_size, fce_size, mq_size;
  2641. struct qla_hw_data *ha = vha->hw;
  2642. struct req_que *req = ha->req_q_map[0];
  2643. struct rsp_que *rsp = ha->rsp_q_map[0];
  2644. struct qla2xxx_fw_dump *fw_dump;
  2645. dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
  2646. req_q_size = rsp_q_size = 0;
  2647. if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
  2648. fixed_size = sizeof(struct qla2100_fw_dump);
  2649. } else if (IS_QLA23XX(ha)) {
  2650. fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
  2651. mem_size = (ha->fw_memory_size - 0x11000 + 1) *
  2652. sizeof(uint16_t);
  2653. } else if (IS_FWI2_CAPABLE(ha)) {
  2654. if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
  2655. fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
  2656. else if (IS_QLA81XX(ha))
  2657. fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
  2658. else if (IS_QLA25XX(ha))
  2659. fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
  2660. else
  2661. fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
  2662. mem_size = (ha->fw_memory_size - 0x100000 + 1) *
  2663. sizeof(uint32_t);
  2664. if (ha->mqenable) {
  2665. if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
  2666. mq_size = sizeof(struct qla2xxx_mq_chain);
  2667. /*
  2668. * Allocate maximum buffer size for all queues.
  2669. * Resizing must be done at end-of-dump processing.
  2670. */
  2671. mq_size += ha->max_req_queues *
  2672. (req->length * sizeof(request_t));
  2673. mq_size += ha->max_rsp_queues *
  2674. (rsp->length * sizeof(response_t));
  2675. }
  2676. if (ha->tgt.atio_ring)
  2677. mq_size += ha->tgt.atio_q_length * sizeof(request_t);
  2678. /* Allocate memory for Fibre Channel Event Buffer. */
  2679. if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
  2680. !IS_QLA27XX(ha))
  2681. goto try_eft;
  2682. fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
  2683. try_eft:
  2684. ql_dbg(ql_dbg_init, vha, 0x00c3,
  2685. "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
  2686. eft_size = EFT_SIZE;
  2687. }
  2688. if (IS_QLA27XX(ha)) {
  2689. if (!ha->fw_dump_template) {
  2690. ql_log(ql_log_warn, vha, 0x00ba,
  2691. "Failed missing fwdump template\n");
  2692. return;
  2693. }
  2694. dump_size = qla27xx_fwdt_calculate_dump_size(vha);
  2695. ql_dbg(ql_dbg_init, vha, 0x00fa,
  2696. "-> allocating fwdump (%x bytes)...\n", dump_size);
  2697. goto allocate;
  2698. }
  2699. req_q_size = req->length * sizeof(request_t);
  2700. rsp_q_size = rsp->length * sizeof(response_t);
  2701. dump_size = offsetof(struct qla2xxx_fw_dump, isp);
  2702. dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
  2703. ha->chain_offset = dump_size;
  2704. dump_size += mq_size + fce_size;
  2705. if (ha->exchoffld_buf)
  2706. dump_size += sizeof(struct qla2xxx_offld_chain) +
  2707. ha->exchoffld_size;
  2708. if (ha->exlogin_buf)
  2709. dump_size += sizeof(struct qla2xxx_offld_chain) +
  2710. ha->exlogin_size;
  2711. allocate:
  2712. if (!ha->fw_dump_len || dump_size != ha->fw_dump_len) {
  2713. fw_dump = vmalloc(dump_size);
  2714. if (!fw_dump) {
  2715. ql_log(ql_log_warn, vha, 0x00c4,
  2716. "Unable to allocate (%d KB) for firmware dump.\n",
  2717. dump_size / 1024);
  2718. } else {
  2719. if (ha->fw_dump)
  2720. vfree(ha->fw_dump);
  2721. ha->fw_dump = fw_dump;
  2722. ha->fw_dump_len = dump_size;
  2723. ql_dbg(ql_dbg_init, vha, 0x00c5,
  2724. "Allocated (%d KB) for firmware dump.\n",
  2725. dump_size / 1024);
  2726. if (IS_QLA27XX(ha))
  2727. return;
  2728. ha->fw_dump->signature[0] = 'Q';
  2729. ha->fw_dump->signature[1] = 'L';
  2730. ha->fw_dump->signature[2] = 'G';
  2731. ha->fw_dump->signature[3] = 'C';
  2732. ha->fw_dump->version = htonl(1);
  2733. ha->fw_dump->fixed_size = htonl(fixed_size);
  2734. ha->fw_dump->mem_size = htonl(mem_size);
  2735. ha->fw_dump->req_q_size = htonl(req_q_size);
  2736. ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
  2737. ha->fw_dump->eft_size = htonl(eft_size);
  2738. ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
  2739. ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
  2740. ha->fw_dump->header_size =
  2741. htonl(offsetof(struct qla2xxx_fw_dump, isp));
  2742. }
  2743. }
  2744. }
  2745. static int
  2746. qla81xx_mpi_sync(scsi_qla_host_t *vha)
  2747. {
  2748. #define MPS_MASK 0xe0
  2749. int rval;
  2750. uint16_t dc;
  2751. uint32_t dw;
  2752. if (!IS_QLA81XX(vha->hw))
  2753. return QLA_SUCCESS;
  2754. rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
  2755. if (rval != QLA_SUCCESS) {
  2756. ql_log(ql_log_warn, vha, 0x0105,
  2757. "Unable to acquire semaphore.\n");
  2758. goto done;
  2759. }
  2760. pci_read_config_word(vha->hw->pdev, 0x54, &dc);
  2761. rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
  2762. if (rval != QLA_SUCCESS) {
  2763. ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
  2764. goto done_release;
  2765. }
  2766. dc &= MPS_MASK;
  2767. if (dc == (dw & MPS_MASK))
  2768. goto done_release;
  2769. dw &= ~MPS_MASK;
  2770. dw |= dc;
  2771. rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
  2772. if (rval != QLA_SUCCESS) {
  2773. ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
  2774. }
  2775. done_release:
  2776. rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
  2777. if (rval != QLA_SUCCESS) {
  2778. ql_log(ql_log_warn, vha, 0x006d,
  2779. "Unable to release semaphore.\n");
  2780. }
  2781. done:
  2782. return rval;
  2783. }
  2784. int
  2785. qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req)
  2786. {
  2787. /* Don't try to reallocate the array */
  2788. if (req->outstanding_cmds)
  2789. return QLA_SUCCESS;
  2790. if (!IS_FWI2_CAPABLE(ha))
  2791. req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS;
  2792. else {
  2793. if (ha->cur_fw_xcb_count <= ha->cur_fw_iocb_count)
  2794. req->num_outstanding_cmds = ha->cur_fw_xcb_count;
  2795. else
  2796. req->num_outstanding_cmds = ha->cur_fw_iocb_count;
  2797. }
  2798. req->outstanding_cmds = kcalloc(req->num_outstanding_cmds,
  2799. sizeof(srb_t *),
  2800. GFP_KERNEL);
  2801. if (!req->outstanding_cmds) {
  2802. /*
  2803. * Try to allocate a minimal size just so we can get through
  2804. * initialization.
  2805. */
  2806. req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS;
  2807. req->outstanding_cmds = kcalloc(req->num_outstanding_cmds,
  2808. sizeof(srb_t *),
  2809. GFP_KERNEL);
  2810. if (!req->outstanding_cmds) {
  2811. ql_log(ql_log_fatal, NULL, 0x0126,
  2812. "Failed to allocate memory for "
  2813. "outstanding_cmds for req_que %p.\n", req);
  2814. req->num_outstanding_cmds = 0;
  2815. return QLA_FUNCTION_FAILED;
  2816. }
  2817. }
  2818. return QLA_SUCCESS;
  2819. }
  2820. #define PRINT_FIELD(_field, _flag, _str) { \
  2821. if (a0->_field & _flag) {\
  2822. if (p) {\
  2823. strcat(ptr, "|");\
  2824. ptr++;\
  2825. leftover--;\
  2826. } \
  2827. len = snprintf(ptr, leftover, "%s", _str); \
  2828. p = 1;\
  2829. leftover -= len;\
  2830. ptr += len; \
  2831. } \
  2832. }
  2833. static void qla2xxx_print_sfp_info(struct scsi_qla_host *vha)
  2834. {
  2835. #define STR_LEN 64
  2836. struct sff_8247_a0 *a0 = (struct sff_8247_a0 *)vha->hw->sfp_data;
  2837. u8 str[STR_LEN], *ptr, p;
  2838. int leftover, len;
  2839. memset(str, 0, STR_LEN);
  2840. snprintf(str, SFF_VEN_NAME_LEN+1, a0->vendor_name);
  2841. ql_dbg(ql_dbg_init, vha, 0x015a,
  2842. "SFP MFG Name: %s\n", str);
  2843. memset(str, 0, STR_LEN);
  2844. snprintf(str, SFF_PART_NAME_LEN+1, a0->vendor_pn);
  2845. ql_dbg(ql_dbg_init, vha, 0x015c,
  2846. "SFP Part Name: %s\n", str);
  2847. /* media */
  2848. memset(str, 0, STR_LEN);
  2849. ptr = str;
  2850. leftover = STR_LEN;
  2851. p = len = 0;
  2852. PRINT_FIELD(fc_med_cc9, FC_MED_TW, "Twin AX");
  2853. PRINT_FIELD(fc_med_cc9, FC_MED_TP, "Twisted Pair");
  2854. PRINT_FIELD(fc_med_cc9, FC_MED_MI, "Min Coax");
  2855. PRINT_FIELD(fc_med_cc9, FC_MED_TV, "Video Coax");
  2856. PRINT_FIELD(fc_med_cc9, FC_MED_M6, "MultiMode 62.5um");
  2857. PRINT_FIELD(fc_med_cc9, FC_MED_M5, "MultiMode 50um");
  2858. PRINT_FIELD(fc_med_cc9, FC_MED_SM, "SingleMode");
  2859. ql_dbg(ql_dbg_init, vha, 0x0160,
  2860. "SFP Media: %s\n", str);
  2861. /* link length */
  2862. memset(str, 0, STR_LEN);
  2863. ptr = str;
  2864. leftover = STR_LEN;
  2865. p = len = 0;
  2866. PRINT_FIELD(fc_ll_cc7, FC_LL_VL, "Very Long");
  2867. PRINT_FIELD(fc_ll_cc7, FC_LL_S, "Short");
  2868. PRINT_FIELD(fc_ll_cc7, FC_LL_I, "Intermediate");
  2869. PRINT_FIELD(fc_ll_cc7, FC_LL_L, "Long");
  2870. PRINT_FIELD(fc_ll_cc7, FC_LL_M, "Medium");
  2871. ql_dbg(ql_dbg_init, vha, 0x0196,
  2872. "SFP Link Length: %s\n", str);
  2873. memset(str, 0, STR_LEN);
  2874. ptr = str;
  2875. leftover = STR_LEN;
  2876. p = len = 0;
  2877. PRINT_FIELD(fc_ll_cc7, FC_LL_SA, "Short Wave (SA)");
  2878. PRINT_FIELD(fc_ll_cc7, FC_LL_LC, "Long Wave(LC)");
  2879. PRINT_FIELD(fc_tec_cc8, FC_TEC_SN, "Short Wave (SN)");
  2880. PRINT_FIELD(fc_tec_cc8, FC_TEC_SL, "Short Wave (SL)");
  2881. PRINT_FIELD(fc_tec_cc8, FC_TEC_LL, "Long Wave (LL)");
  2882. ql_dbg(ql_dbg_init, vha, 0x016e,
  2883. "SFP FC Link Tech: %s\n", str);
  2884. if (a0->length_km)
  2885. ql_dbg(ql_dbg_init, vha, 0x016f,
  2886. "SFP Distant: %d km\n", a0->length_km);
  2887. if (a0->length_100m)
  2888. ql_dbg(ql_dbg_init, vha, 0x0170,
  2889. "SFP Distant: %d m\n", a0->length_100m*100);
  2890. if (a0->length_50um_10m)
  2891. ql_dbg(ql_dbg_init, vha, 0x0189,
  2892. "SFP Distant (WL=50um): %d m\n", a0->length_50um_10m * 10);
  2893. if (a0->length_62um_10m)
  2894. ql_dbg(ql_dbg_init, vha, 0x018a,
  2895. "SFP Distant (WL=62.5um): %d m\n", a0->length_62um_10m * 10);
  2896. if (a0->length_om4_10m)
  2897. ql_dbg(ql_dbg_init, vha, 0x0194,
  2898. "SFP Distant (OM4): %d m\n", a0->length_om4_10m * 10);
  2899. if (a0->length_om3_10m)
  2900. ql_dbg(ql_dbg_init, vha, 0x0195,
  2901. "SFP Distant (OM3): %d m\n", a0->length_om3_10m * 10);
  2902. }
  2903. /*
  2904. * Return Code:
  2905. * QLA_SUCCESS: no action
  2906. * QLA_INTERFACE_ERROR: SFP is not there.
  2907. * QLA_FUNCTION_FAILED: detected New SFP
  2908. */
  2909. int
  2910. qla24xx_detect_sfp(scsi_qla_host_t *vha)
  2911. {
  2912. int rc = QLA_SUCCESS;
  2913. struct sff_8247_a0 *a;
  2914. struct qla_hw_data *ha = vha->hw;
  2915. if (!AUTO_DETECT_SFP_SUPPORT(vha))
  2916. goto out;
  2917. rc = qla2x00_read_sfp_dev(vha, NULL, 0);
  2918. if (rc)
  2919. goto out;
  2920. a = (struct sff_8247_a0 *)vha->hw->sfp_data;
  2921. qla2xxx_print_sfp_info(vha);
  2922. if (a->fc_ll_cc7 & FC_LL_VL || a->fc_ll_cc7 & FC_LL_L) {
  2923. /* long range */
  2924. ha->flags.detected_lr_sfp = 1;
  2925. if (a->length_km > 5 || a->length_100m > 50)
  2926. ha->long_range_distance = LR_DISTANCE_10K;
  2927. else
  2928. ha->long_range_distance = LR_DISTANCE_5K;
  2929. if (ha->flags.detected_lr_sfp != ha->flags.using_lr_setting)
  2930. ql_dbg(ql_dbg_async, vha, 0x507b,
  2931. "Detected Long Range SFP.\n");
  2932. } else {
  2933. /* short range */
  2934. ha->flags.detected_lr_sfp = 0;
  2935. if (ha->flags.using_lr_setting)
  2936. ql_dbg(ql_dbg_async, vha, 0x5084,
  2937. "Detected Short Range SFP.\n");
  2938. }
  2939. if (!vha->flags.init_done)
  2940. rc = QLA_SUCCESS;
  2941. out:
  2942. return rc;
  2943. }
  2944. /**
  2945. * qla2x00_setup_chip() - Load and start RISC firmware.
  2946. * @vha: HA context
  2947. *
  2948. * Returns 0 on success.
  2949. */
  2950. static int
  2951. qla2x00_setup_chip(scsi_qla_host_t *vha)
  2952. {
  2953. int rval;
  2954. uint32_t srisc_address = 0;
  2955. struct qla_hw_data *ha = vha->hw;
  2956. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  2957. unsigned long flags;
  2958. uint16_t fw_major_version;
  2959. if (IS_P3P_TYPE(ha)) {
  2960. rval = ha->isp_ops->load_risc(vha, &srisc_address);
  2961. if (rval == QLA_SUCCESS) {
  2962. qla2x00_stop_firmware(vha);
  2963. goto enable_82xx_npiv;
  2964. } else
  2965. goto failed;
  2966. }
  2967. if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
  2968. /* Disable SRAM, Instruction RAM and GP RAM parity. */
  2969. spin_lock_irqsave(&ha->hardware_lock, flags);
  2970. WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
  2971. RD_REG_WORD(&reg->hccr);
  2972. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2973. }
  2974. qla81xx_mpi_sync(vha);
  2975. /* Load firmware sequences */
  2976. rval = ha->isp_ops->load_risc(vha, &srisc_address);
  2977. if (rval == QLA_SUCCESS) {
  2978. ql_dbg(ql_dbg_init, vha, 0x00c9,
  2979. "Verifying Checksum of loaded RISC code.\n");
  2980. rval = qla2x00_verify_checksum(vha, srisc_address);
  2981. if (rval == QLA_SUCCESS) {
  2982. /* Start firmware execution. */
  2983. ql_dbg(ql_dbg_init, vha, 0x00ca,
  2984. "Starting firmware.\n");
  2985. if (ql2xexlogins)
  2986. ha->flags.exlogins_enabled = 1;
  2987. if (qla_is_exch_offld_enabled(vha))
  2988. ha->flags.exchoffld_enabled = 1;
  2989. rval = qla2x00_execute_fw(vha, srisc_address);
  2990. /* Retrieve firmware information. */
  2991. if (rval == QLA_SUCCESS) {
  2992. qla24xx_detect_sfp(vha);
  2993. rval = qla2x00_set_exlogins_buffer(vha);
  2994. if (rval != QLA_SUCCESS)
  2995. goto failed;
  2996. rval = qla2x00_set_exchoffld_buffer(vha);
  2997. if (rval != QLA_SUCCESS)
  2998. goto failed;
  2999. enable_82xx_npiv:
  3000. fw_major_version = ha->fw_major_version;
  3001. if (IS_P3P_TYPE(ha))
  3002. qla82xx_check_md_needed(vha);
  3003. else
  3004. rval = qla2x00_get_fw_version(vha);
  3005. if (rval != QLA_SUCCESS)
  3006. goto failed;
  3007. ha->flags.npiv_supported = 0;
  3008. if (IS_QLA2XXX_MIDTYPE(ha) &&
  3009. (ha->fw_attributes & BIT_2)) {
  3010. ha->flags.npiv_supported = 1;
  3011. if ((!ha->max_npiv_vports) ||
  3012. ((ha->max_npiv_vports + 1) %
  3013. MIN_MULTI_ID_FABRIC))
  3014. ha->max_npiv_vports =
  3015. MIN_MULTI_ID_FABRIC - 1;
  3016. }
  3017. qla2x00_get_resource_cnts(vha);
  3018. /*
  3019. * Allocate the array of outstanding commands
  3020. * now that we know the firmware resources.
  3021. */
  3022. rval = qla2x00_alloc_outstanding_cmds(ha,
  3023. vha->req);
  3024. if (rval != QLA_SUCCESS)
  3025. goto failed;
  3026. if (!fw_major_version && !(IS_P3P_TYPE(ha)))
  3027. qla2x00_alloc_offload_mem(vha);
  3028. if (ql2xallocfwdump && !(IS_P3P_TYPE(ha)))
  3029. qla2x00_alloc_fw_dump(vha);
  3030. } else {
  3031. goto failed;
  3032. }
  3033. } else {
  3034. ql_log(ql_log_fatal, vha, 0x00cd,
  3035. "ISP Firmware failed checksum.\n");
  3036. goto failed;
  3037. }
  3038. } else
  3039. goto failed;
  3040. if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
  3041. /* Enable proper parity. */
  3042. spin_lock_irqsave(&ha->hardware_lock, flags);
  3043. if (IS_QLA2300(ha))
  3044. /* SRAM parity */
  3045. WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
  3046. else
  3047. /* SRAM, Instruction RAM and GP RAM parity */
  3048. WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
  3049. RD_REG_WORD(&reg->hccr);
  3050. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  3051. }
  3052. if (IS_QLA27XX(ha))
  3053. ha->flags.fac_supported = 1;
  3054. else if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
  3055. uint32_t size;
  3056. rval = qla81xx_fac_get_sector_size(vha, &size);
  3057. if (rval == QLA_SUCCESS) {
  3058. ha->flags.fac_supported = 1;
  3059. ha->fdt_block_size = size << 2;
  3060. } else {
  3061. ql_log(ql_log_warn, vha, 0x00ce,
  3062. "Unsupported FAC firmware (%d.%02d.%02d).\n",
  3063. ha->fw_major_version, ha->fw_minor_version,
  3064. ha->fw_subminor_version);
  3065. if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
  3066. ha->flags.fac_supported = 0;
  3067. rval = QLA_SUCCESS;
  3068. }
  3069. }
  3070. }
  3071. failed:
  3072. if (rval) {
  3073. ql_log(ql_log_fatal, vha, 0x00cf,
  3074. "Setup chip ****FAILED****.\n");
  3075. }
  3076. return (rval);
  3077. }
  3078. /**
  3079. * qla2x00_init_response_q_entries() - Initializes response queue entries.
  3080. * @rsp: response queue
  3081. *
  3082. * Beginning of request ring has initialization control block already built
  3083. * by nvram config routine.
  3084. *
  3085. * Returns 0 on success.
  3086. */
  3087. void
  3088. qla2x00_init_response_q_entries(struct rsp_que *rsp)
  3089. {
  3090. uint16_t cnt;
  3091. response_t *pkt;
  3092. rsp->ring_ptr = rsp->ring;
  3093. rsp->ring_index = 0;
  3094. rsp->status_srb = NULL;
  3095. pkt = rsp->ring_ptr;
  3096. for (cnt = 0; cnt < rsp->length; cnt++) {
  3097. pkt->signature = RESPONSE_PROCESSED;
  3098. pkt++;
  3099. }
  3100. }
  3101. /**
  3102. * qla2x00_update_fw_options() - Read and process firmware options.
  3103. * @vha: HA context
  3104. *
  3105. * Returns 0 on success.
  3106. */
  3107. void
  3108. qla2x00_update_fw_options(scsi_qla_host_t *vha)
  3109. {
  3110. uint16_t swing, emphasis, tx_sens, rx_sens;
  3111. struct qla_hw_data *ha = vha->hw;
  3112. memset(ha->fw_options, 0, sizeof(ha->fw_options));
  3113. qla2x00_get_fw_options(vha, ha->fw_options);
  3114. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  3115. return;
  3116. /* Serial Link options. */
  3117. ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
  3118. "Serial link options.\n");
  3119. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
  3120. (uint8_t *)&ha->fw_seriallink_options,
  3121. sizeof(ha->fw_seriallink_options));
  3122. ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
  3123. if (ha->fw_seriallink_options[3] & BIT_2) {
  3124. ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
  3125. /* 1G settings */
  3126. swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
  3127. emphasis = (ha->fw_seriallink_options[2] &
  3128. (BIT_4 | BIT_3)) >> 3;
  3129. tx_sens = ha->fw_seriallink_options[0] &
  3130. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  3131. rx_sens = (ha->fw_seriallink_options[0] &
  3132. (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
  3133. ha->fw_options[10] = (emphasis << 14) | (swing << 8);
  3134. if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
  3135. if (rx_sens == 0x0)
  3136. rx_sens = 0x3;
  3137. ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
  3138. } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
  3139. ha->fw_options[10] |= BIT_5 |
  3140. ((rx_sens & (BIT_1 | BIT_0)) << 2) |
  3141. (tx_sens & (BIT_1 | BIT_0));
  3142. /* 2G settings */
  3143. swing = (ha->fw_seriallink_options[2] &
  3144. (BIT_7 | BIT_6 | BIT_5)) >> 5;
  3145. emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
  3146. tx_sens = ha->fw_seriallink_options[1] &
  3147. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  3148. rx_sens = (ha->fw_seriallink_options[1] &
  3149. (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
  3150. ha->fw_options[11] = (emphasis << 14) | (swing << 8);
  3151. if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
  3152. if (rx_sens == 0x0)
  3153. rx_sens = 0x3;
  3154. ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
  3155. } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
  3156. ha->fw_options[11] |= BIT_5 |
  3157. ((rx_sens & (BIT_1 | BIT_0)) << 2) |
  3158. (tx_sens & (BIT_1 | BIT_0));
  3159. }
  3160. /* FCP2 options. */
  3161. /* Return command IOCBs without waiting for an ABTS to complete. */
  3162. ha->fw_options[3] |= BIT_13;
  3163. /* LED scheme. */
  3164. if (ha->flags.enable_led_scheme)
  3165. ha->fw_options[2] |= BIT_12;
  3166. /* Detect ISP6312. */
  3167. if (IS_QLA6312(ha))
  3168. ha->fw_options[2] |= BIT_13;
  3169. /* Set Retry FLOGI in case of P2P connection */
  3170. if (ha->operating_mode == P2P) {
  3171. ha->fw_options[2] |= BIT_3;
  3172. ql_dbg(ql_dbg_disc, vha, 0x2100,
  3173. "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
  3174. __func__, ha->fw_options[2]);
  3175. }
  3176. /* Update firmware options. */
  3177. qla2x00_set_fw_options(vha, ha->fw_options);
  3178. }
  3179. void
  3180. qla24xx_update_fw_options(scsi_qla_host_t *vha)
  3181. {
  3182. int rval;
  3183. struct qla_hw_data *ha = vha->hw;
  3184. if (IS_P3P_TYPE(ha))
  3185. return;
  3186. /* Hold status IOCBs until ABTS response received. */
  3187. if (ql2xfwholdabts)
  3188. ha->fw_options[3] |= BIT_12;
  3189. /* Set Retry FLOGI in case of P2P connection */
  3190. if (ha->operating_mode == P2P) {
  3191. ha->fw_options[2] |= BIT_3;
  3192. ql_dbg(ql_dbg_disc, vha, 0x2101,
  3193. "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
  3194. __func__, ha->fw_options[2]);
  3195. }
  3196. /* Move PUREX, ABTS RX & RIDA to ATIOQ */
  3197. if (ql2xmvasynctoatio &&
  3198. (IS_QLA83XX(ha) || IS_QLA27XX(ha))) {
  3199. if (qla_tgt_mode_enabled(vha) ||
  3200. qla_dual_mode_enabled(vha))
  3201. ha->fw_options[2] |= BIT_11;
  3202. else
  3203. ha->fw_options[2] &= ~BIT_11;
  3204. }
  3205. if (IS_QLA25XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
  3206. /*
  3207. * Tell FW to track each exchange to prevent
  3208. * driver from using stale exchange.
  3209. */
  3210. if (qla_tgt_mode_enabled(vha) ||
  3211. qla_dual_mode_enabled(vha))
  3212. ha->fw_options[2] |= BIT_4;
  3213. else
  3214. ha->fw_options[2] &= ~BIT_4;
  3215. /* Reserve 1/2 of emergency exchanges for ELS.*/
  3216. if (qla2xuseresexchforels)
  3217. ha->fw_options[2] |= BIT_8;
  3218. else
  3219. ha->fw_options[2] &= ~BIT_8;
  3220. }
  3221. ql_dbg(ql_dbg_init, vha, 0x00e8,
  3222. "%s, add FW options 1-3 = 0x%04x 0x%04x 0x%04x mode %x\n",
  3223. __func__, ha->fw_options[1], ha->fw_options[2],
  3224. ha->fw_options[3], vha->host->active_mode);
  3225. if (ha->fw_options[1] || ha->fw_options[2] || ha->fw_options[3])
  3226. qla2x00_set_fw_options(vha, ha->fw_options);
  3227. /* Update Serial Link options. */
  3228. if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
  3229. return;
  3230. rval = qla2x00_set_serdes_params(vha,
  3231. le16_to_cpu(ha->fw_seriallink_options24[1]),
  3232. le16_to_cpu(ha->fw_seriallink_options24[2]),
  3233. le16_to_cpu(ha->fw_seriallink_options24[3]));
  3234. if (rval != QLA_SUCCESS) {
  3235. ql_log(ql_log_warn, vha, 0x0104,
  3236. "Unable to update Serial Link options (%x).\n", rval);
  3237. }
  3238. }
  3239. void
  3240. qla2x00_config_rings(struct scsi_qla_host *vha)
  3241. {
  3242. struct qla_hw_data *ha = vha->hw;
  3243. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  3244. struct req_que *req = ha->req_q_map[0];
  3245. struct rsp_que *rsp = ha->rsp_q_map[0];
  3246. /* Setup ring parameters in initialization control block. */
  3247. ha->init_cb->request_q_outpointer = cpu_to_le16(0);
  3248. ha->init_cb->response_q_inpointer = cpu_to_le16(0);
  3249. ha->init_cb->request_q_length = cpu_to_le16(req->length);
  3250. ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
  3251. ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
  3252. ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
  3253. ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
  3254. ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
  3255. WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
  3256. WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
  3257. WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
  3258. WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
  3259. RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
  3260. }
  3261. void
  3262. qla24xx_config_rings(struct scsi_qla_host *vha)
  3263. {
  3264. struct qla_hw_data *ha = vha->hw;
  3265. device_reg_t *reg = ISP_QUE_REG(ha, 0);
  3266. struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
  3267. struct qla_msix_entry *msix;
  3268. struct init_cb_24xx *icb;
  3269. uint16_t rid = 0;
  3270. struct req_que *req = ha->req_q_map[0];
  3271. struct rsp_que *rsp = ha->rsp_q_map[0];
  3272. /* Setup ring parameters in initialization control block. */
  3273. icb = (struct init_cb_24xx *)ha->init_cb;
  3274. icb->request_q_outpointer = cpu_to_le16(0);
  3275. icb->response_q_inpointer = cpu_to_le16(0);
  3276. icb->request_q_length = cpu_to_le16(req->length);
  3277. icb->response_q_length = cpu_to_le16(rsp->length);
  3278. icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
  3279. icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
  3280. icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
  3281. icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
  3282. /* Setup ATIO queue dma pointers for target mode */
  3283. icb->atio_q_inpointer = cpu_to_le16(0);
  3284. icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
  3285. icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma));
  3286. icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma));
  3287. if (IS_SHADOW_REG_CAPABLE(ha))
  3288. icb->firmware_options_2 |= cpu_to_le32(BIT_30|BIT_29);
  3289. if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
  3290. icb->qos = cpu_to_le16(QLA_DEFAULT_QUE_QOS);
  3291. icb->rid = cpu_to_le16(rid);
  3292. if (ha->flags.msix_enabled) {
  3293. msix = &ha->msix_entries[1];
  3294. ql_dbg(ql_dbg_init, vha, 0x0019,
  3295. "Registering vector 0x%x for base que.\n",
  3296. msix->entry);
  3297. icb->msix = cpu_to_le16(msix->entry);
  3298. }
  3299. /* Use alternate PCI bus number */
  3300. if (MSB(rid))
  3301. icb->firmware_options_2 |= cpu_to_le32(BIT_19);
  3302. /* Use alternate PCI devfn */
  3303. if (LSB(rid))
  3304. icb->firmware_options_2 |= cpu_to_le32(BIT_18);
  3305. /* Use Disable MSIX Handshake mode for capable adapters */
  3306. if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
  3307. (ha->flags.msix_enabled)) {
  3308. icb->firmware_options_2 &= cpu_to_le32(~BIT_22);
  3309. ha->flags.disable_msix_handshake = 1;
  3310. ql_dbg(ql_dbg_init, vha, 0x00fe,
  3311. "MSIX Handshake Disable Mode turned on.\n");
  3312. } else {
  3313. icb->firmware_options_2 |= cpu_to_le32(BIT_22);
  3314. }
  3315. icb->firmware_options_2 |= cpu_to_le32(BIT_23);
  3316. WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
  3317. WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
  3318. WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
  3319. WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
  3320. } else {
  3321. WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
  3322. WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
  3323. WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
  3324. WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
  3325. }
  3326. qlt_24xx_config_rings(vha);
  3327. /* PCI posting */
  3328. RD_REG_DWORD(&ioreg->hccr);
  3329. }
  3330. /**
  3331. * qla2x00_init_rings() - Initializes firmware.
  3332. * @vha: HA context
  3333. *
  3334. * Beginning of request ring has initialization control block already built
  3335. * by nvram config routine.
  3336. *
  3337. * Returns 0 on success.
  3338. */
  3339. int
  3340. qla2x00_init_rings(scsi_qla_host_t *vha)
  3341. {
  3342. int rval;
  3343. unsigned long flags = 0;
  3344. int cnt, que;
  3345. struct qla_hw_data *ha = vha->hw;
  3346. struct req_que *req;
  3347. struct rsp_que *rsp;
  3348. struct mid_init_cb_24xx *mid_init_cb =
  3349. (struct mid_init_cb_24xx *) ha->init_cb;
  3350. spin_lock_irqsave(&ha->hardware_lock, flags);
  3351. /* Clear outstanding commands array. */
  3352. for (que = 0; que < ha->max_req_queues; que++) {
  3353. req = ha->req_q_map[que];
  3354. if (!req || !test_bit(que, ha->req_qid_map))
  3355. continue;
  3356. req->out_ptr = (void *)(req->ring + req->length);
  3357. *req->out_ptr = 0;
  3358. for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++)
  3359. req->outstanding_cmds[cnt] = NULL;
  3360. req->current_outstanding_cmd = 1;
  3361. /* Initialize firmware. */
  3362. req->ring_ptr = req->ring;
  3363. req->ring_index = 0;
  3364. req->cnt = req->length;
  3365. }
  3366. for (que = 0; que < ha->max_rsp_queues; que++) {
  3367. rsp = ha->rsp_q_map[que];
  3368. if (!rsp || !test_bit(que, ha->rsp_qid_map))
  3369. continue;
  3370. rsp->in_ptr = (void *)(rsp->ring + rsp->length);
  3371. *rsp->in_ptr = 0;
  3372. /* Initialize response queue entries */
  3373. if (IS_QLAFX00(ha))
  3374. qlafx00_init_response_q_entries(rsp);
  3375. else
  3376. qla2x00_init_response_q_entries(rsp);
  3377. }
  3378. ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
  3379. ha->tgt.atio_ring_index = 0;
  3380. /* Initialize ATIO queue entries */
  3381. qlt_init_atio_q_entries(vha);
  3382. ha->isp_ops->config_rings(vha);
  3383. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  3384. ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
  3385. if (IS_QLAFX00(ha)) {
  3386. rval = qlafx00_init_firmware(vha, ha->init_cb_size);
  3387. goto next_check;
  3388. }
  3389. /* Update any ISP specific firmware options before initialization. */
  3390. ha->isp_ops->update_fw_options(vha);
  3391. if (ha->flags.npiv_supported) {
  3392. if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha))
  3393. ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
  3394. mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
  3395. }
  3396. if (IS_FWI2_CAPABLE(ha)) {
  3397. mid_init_cb->options = cpu_to_le16(BIT_1);
  3398. mid_init_cb->init_cb.execution_throttle =
  3399. cpu_to_le16(ha->cur_fw_xcb_count);
  3400. ha->flags.dport_enabled =
  3401. (mid_init_cb->init_cb.firmware_options_1 & BIT_7) != 0;
  3402. ql_dbg(ql_dbg_init, vha, 0x0191, "DPORT Support: %s.\n",
  3403. (ha->flags.dport_enabled) ? "enabled" : "disabled");
  3404. /* FA-WWPN Status */
  3405. ha->flags.fawwpn_enabled =
  3406. (mid_init_cb->init_cb.firmware_options_1 & BIT_6) != 0;
  3407. ql_dbg(ql_dbg_init, vha, 0x00bc, "FA-WWPN Support: %s.\n",
  3408. (ha->flags.fawwpn_enabled) ? "enabled" : "disabled");
  3409. }
  3410. rval = qla2x00_init_firmware(vha, ha->init_cb_size);
  3411. next_check:
  3412. if (rval) {
  3413. ql_log(ql_log_fatal, vha, 0x00d2,
  3414. "Init Firmware **** FAILED ****.\n");
  3415. } else {
  3416. ql_dbg(ql_dbg_init, vha, 0x00d3,
  3417. "Init Firmware -- success.\n");
  3418. QLA_FW_STARTED(ha);
  3419. }
  3420. return (rval);
  3421. }
  3422. /**
  3423. * qla2x00_fw_ready() - Waits for firmware ready.
  3424. * @vha: HA context
  3425. *
  3426. * Returns 0 on success.
  3427. */
  3428. static int
  3429. qla2x00_fw_ready(scsi_qla_host_t *vha)
  3430. {
  3431. int rval;
  3432. unsigned long wtime, mtime, cs84xx_time;
  3433. uint16_t min_wait; /* Minimum wait time if loop is down */
  3434. uint16_t wait_time; /* Wait time if loop is coming ready */
  3435. uint16_t state[6];
  3436. struct qla_hw_data *ha = vha->hw;
  3437. if (IS_QLAFX00(vha->hw))
  3438. return qlafx00_fw_ready(vha);
  3439. rval = QLA_SUCCESS;
  3440. /* Time to wait for loop down */
  3441. if (IS_P3P_TYPE(ha))
  3442. min_wait = 30;
  3443. else
  3444. min_wait = 20;
  3445. /*
  3446. * Firmware should take at most one RATOV to login, plus 5 seconds for
  3447. * our own processing.
  3448. */
  3449. if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
  3450. wait_time = min_wait;
  3451. }
  3452. /* Min wait time if loop down */
  3453. mtime = jiffies + (min_wait * HZ);
  3454. /* wait time before firmware ready */
  3455. wtime = jiffies + (wait_time * HZ);
  3456. /* Wait for ISP to finish LIP */
  3457. if (!vha->flags.init_done)
  3458. ql_log(ql_log_info, vha, 0x801e,
  3459. "Waiting for LIP to complete.\n");
  3460. do {
  3461. memset(state, -1, sizeof(state));
  3462. rval = qla2x00_get_firmware_state(vha, state);
  3463. if (rval == QLA_SUCCESS) {
  3464. if (state[0] < FSTATE_LOSS_OF_SYNC) {
  3465. vha->device_flags &= ~DFLG_NO_CABLE;
  3466. }
  3467. if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
  3468. ql_dbg(ql_dbg_taskm, vha, 0x801f,
  3469. "fw_state=%x 84xx=%x.\n", state[0],
  3470. state[2]);
  3471. if ((state[2] & FSTATE_LOGGED_IN) &&
  3472. (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
  3473. ql_dbg(ql_dbg_taskm, vha, 0x8028,
  3474. "Sending verify iocb.\n");
  3475. cs84xx_time = jiffies;
  3476. rval = qla84xx_init_chip(vha);
  3477. if (rval != QLA_SUCCESS) {
  3478. ql_log(ql_log_warn,
  3479. vha, 0x8007,
  3480. "Init chip failed.\n");
  3481. break;
  3482. }
  3483. /* Add time taken to initialize. */
  3484. cs84xx_time = jiffies - cs84xx_time;
  3485. wtime += cs84xx_time;
  3486. mtime += cs84xx_time;
  3487. ql_dbg(ql_dbg_taskm, vha, 0x8008,
  3488. "Increasing wait time by %ld. "
  3489. "New time %ld.\n", cs84xx_time,
  3490. wtime);
  3491. }
  3492. } else if (state[0] == FSTATE_READY) {
  3493. ql_dbg(ql_dbg_taskm, vha, 0x8037,
  3494. "F/W Ready - OK.\n");
  3495. qla2x00_get_retry_cnt(vha, &ha->retry_count,
  3496. &ha->login_timeout, &ha->r_a_tov);
  3497. rval = QLA_SUCCESS;
  3498. break;
  3499. }
  3500. rval = QLA_FUNCTION_FAILED;
  3501. if (atomic_read(&vha->loop_down_timer) &&
  3502. state[0] != FSTATE_READY) {
  3503. /* Loop down. Timeout on min_wait for states
  3504. * other than Wait for Login.
  3505. */
  3506. if (time_after_eq(jiffies, mtime)) {
  3507. ql_log(ql_log_info, vha, 0x8038,
  3508. "Cable is unplugged...\n");
  3509. vha->device_flags |= DFLG_NO_CABLE;
  3510. break;
  3511. }
  3512. }
  3513. } else {
  3514. /* Mailbox cmd failed. Timeout on min_wait. */
  3515. if (time_after_eq(jiffies, mtime) ||
  3516. ha->flags.isp82xx_fw_hung)
  3517. break;
  3518. }
  3519. if (time_after_eq(jiffies, wtime))
  3520. break;
  3521. /* Delay for a while */
  3522. msleep(500);
  3523. } while (1);
  3524. ql_dbg(ql_dbg_taskm, vha, 0x803a,
  3525. "fw_state=%x (%x, %x, %x, %x %x) curr time=%lx.\n", state[0],
  3526. state[1], state[2], state[3], state[4], state[5], jiffies);
  3527. if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
  3528. ql_log(ql_log_warn, vha, 0x803b,
  3529. "Firmware ready **** FAILED ****.\n");
  3530. }
  3531. return (rval);
  3532. }
  3533. /*
  3534. * qla2x00_configure_hba
  3535. * Setup adapter context.
  3536. *
  3537. * Input:
  3538. * ha = adapter state pointer.
  3539. *
  3540. * Returns:
  3541. * 0 = success
  3542. *
  3543. * Context:
  3544. * Kernel context.
  3545. */
  3546. static int
  3547. qla2x00_configure_hba(scsi_qla_host_t *vha)
  3548. {
  3549. int rval;
  3550. uint16_t loop_id;
  3551. uint16_t topo;
  3552. uint16_t sw_cap;
  3553. uint8_t al_pa;
  3554. uint8_t area;
  3555. uint8_t domain;
  3556. char connect_type[22];
  3557. struct qla_hw_data *ha = vha->hw;
  3558. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  3559. port_id_t id;
  3560. unsigned long flags;
  3561. /* Get host addresses. */
  3562. rval = qla2x00_get_adapter_id(vha,
  3563. &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
  3564. if (rval != QLA_SUCCESS) {
  3565. if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
  3566. IS_CNA_CAPABLE(ha) ||
  3567. (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
  3568. ql_dbg(ql_dbg_disc, vha, 0x2008,
  3569. "Loop is in a transition state.\n");
  3570. } else {
  3571. ql_log(ql_log_warn, vha, 0x2009,
  3572. "Unable to get host loop ID.\n");
  3573. if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) &&
  3574. (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) {
  3575. ql_log(ql_log_warn, vha, 0x1151,
  3576. "Doing link init.\n");
  3577. if (qla24xx_link_initialize(vha) == QLA_SUCCESS)
  3578. return rval;
  3579. }
  3580. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  3581. }
  3582. return (rval);
  3583. }
  3584. if (topo == 4) {
  3585. ql_log(ql_log_info, vha, 0x200a,
  3586. "Cannot get topology - retrying.\n");
  3587. return (QLA_FUNCTION_FAILED);
  3588. }
  3589. vha->loop_id = loop_id;
  3590. /* initialize */
  3591. ha->min_external_loopid = SNS_FIRST_LOOP_ID;
  3592. ha->operating_mode = LOOP;
  3593. ha->switch_cap = 0;
  3594. switch (topo) {
  3595. case 0:
  3596. ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
  3597. ha->current_topology = ISP_CFG_NL;
  3598. strcpy(connect_type, "(Loop)");
  3599. break;
  3600. case 1:
  3601. ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
  3602. ha->switch_cap = sw_cap;
  3603. ha->current_topology = ISP_CFG_FL;
  3604. strcpy(connect_type, "(FL_Port)");
  3605. break;
  3606. case 2:
  3607. ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
  3608. ha->operating_mode = P2P;
  3609. ha->current_topology = ISP_CFG_N;
  3610. strcpy(connect_type, "(N_Port-to-N_Port)");
  3611. break;
  3612. case 3:
  3613. ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
  3614. ha->switch_cap = sw_cap;
  3615. ha->operating_mode = P2P;
  3616. ha->current_topology = ISP_CFG_F;
  3617. strcpy(connect_type, "(F_Port)");
  3618. break;
  3619. default:
  3620. ql_dbg(ql_dbg_disc, vha, 0x200f,
  3621. "HBA in unknown topology %x, using NL.\n", topo);
  3622. ha->current_topology = ISP_CFG_NL;
  3623. strcpy(connect_type, "(Loop)");
  3624. break;
  3625. }
  3626. /* Save Host port and loop ID. */
  3627. /* byte order - Big Endian */
  3628. id.b.domain = domain;
  3629. id.b.area = area;
  3630. id.b.al_pa = al_pa;
  3631. id.b.rsvd_1 = 0;
  3632. spin_lock_irqsave(&ha->hardware_lock, flags);
  3633. if (!(topo == 2 && ha->flags.n2n_bigger))
  3634. qlt_update_host_map(vha, id);
  3635. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  3636. if (!vha->flags.init_done)
  3637. ql_log(ql_log_info, vha, 0x2010,
  3638. "Topology - %s, Host Loop address 0x%x.\n",
  3639. connect_type, vha->loop_id);
  3640. return(rval);
  3641. }
  3642. inline void
  3643. qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
  3644. char *def)
  3645. {
  3646. char *st, *en;
  3647. uint16_t index;
  3648. struct qla_hw_data *ha = vha->hw;
  3649. int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
  3650. !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
  3651. if (memcmp(model, BINZERO, len) != 0) {
  3652. strncpy(ha->model_number, model, len);
  3653. st = en = ha->model_number;
  3654. en += len - 1;
  3655. while (en > st) {
  3656. if (*en != 0x20 && *en != 0x00)
  3657. break;
  3658. *en-- = '\0';
  3659. }
  3660. index = (ha->pdev->subsystem_device & 0xff);
  3661. if (use_tbl &&
  3662. ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
  3663. index < QLA_MODEL_NAMES)
  3664. strncpy(ha->model_desc,
  3665. qla2x00_model_name[index * 2 + 1],
  3666. sizeof(ha->model_desc) - 1);
  3667. } else {
  3668. index = (ha->pdev->subsystem_device & 0xff);
  3669. if (use_tbl &&
  3670. ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
  3671. index < QLA_MODEL_NAMES) {
  3672. strcpy(ha->model_number,
  3673. qla2x00_model_name[index * 2]);
  3674. strncpy(ha->model_desc,
  3675. qla2x00_model_name[index * 2 + 1],
  3676. sizeof(ha->model_desc) - 1);
  3677. } else {
  3678. strcpy(ha->model_number, def);
  3679. }
  3680. }
  3681. if (IS_FWI2_CAPABLE(ha))
  3682. qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
  3683. sizeof(ha->model_desc));
  3684. }
  3685. /* On sparc systems, obtain port and node WWN from firmware
  3686. * properties.
  3687. */
  3688. static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
  3689. {
  3690. #ifdef CONFIG_SPARC
  3691. struct qla_hw_data *ha = vha->hw;
  3692. struct pci_dev *pdev = ha->pdev;
  3693. struct device_node *dp = pci_device_to_OF_node(pdev);
  3694. const u8 *val;
  3695. int len;
  3696. val = of_get_property(dp, "port-wwn", &len);
  3697. if (val && len >= WWN_SIZE)
  3698. memcpy(nv->port_name, val, WWN_SIZE);
  3699. val = of_get_property(dp, "node-wwn", &len);
  3700. if (val && len >= WWN_SIZE)
  3701. memcpy(nv->node_name, val, WWN_SIZE);
  3702. #endif
  3703. }
  3704. /*
  3705. * NVRAM configuration for ISP 2xxx
  3706. *
  3707. * Input:
  3708. * ha = adapter block pointer.
  3709. *
  3710. * Output:
  3711. * initialization control block in response_ring
  3712. * host adapters parameters in host adapter block
  3713. *
  3714. * Returns:
  3715. * 0 = success.
  3716. */
  3717. int
  3718. qla2x00_nvram_config(scsi_qla_host_t *vha)
  3719. {
  3720. int rval;
  3721. uint8_t chksum = 0;
  3722. uint16_t cnt;
  3723. uint8_t *dptr1, *dptr2;
  3724. struct qla_hw_data *ha = vha->hw;
  3725. init_cb_t *icb = ha->init_cb;
  3726. nvram_t *nv = ha->nvram;
  3727. uint8_t *ptr = ha->nvram;
  3728. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  3729. rval = QLA_SUCCESS;
  3730. /* Determine NVRAM starting address. */
  3731. ha->nvram_size = sizeof(nvram_t);
  3732. ha->nvram_base = 0;
  3733. if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
  3734. if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
  3735. ha->nvram_base = 0x80;
  3736. /* Get NVRAM data and calculate checksum. */
  3737. ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
  3738. for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
  3739. chksum += *ptr++;
  3740. ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
  3741. "Contents of NVRAM.\n");
  3742. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
  3743. (uint8_t *)nv, ha->nvram_size);
  3744. /* Bad NVRAM data, set defaults parameters. */
  3745. if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
  3746. nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
  3747. /* Reset NVRAM data. */
  3748. ql_log(ql_log_warn, vha, 0x0064,
  3749. "Inconsistent NVRAM "
  3750. "detected: checksum=0x%x id=%c version=0x%x.\n",
  3751. chksum, nv->id[0], nv->nvram_version);
  3752. ql_log(ql_log_warn, vha, 0x0065,
  3753. "Falling back to "
  3754. "functioning (yet invalid -- WWPN) defaults.\n");
  3755. /*
  3756. * Set default initialization control block.
  3757. */
  3758. memset(nv, 0, ha->nvram_size);
  3759. nv->parameter_block_version = ICB_VERSION;
  3760. if (IS_QLA23XX(ha)) {
  3761. nv->firmware_options[0] = BIT_2 | BIT_1;
  3762. nv->firmware_options[1] = BIT_7 | BIT_5;
  3763. nv->add_firmware_options[0] = BIT_5;
  3764. nv->add_firmware_options[1] = BIT_5 | BIT_4;
  3765. nv->frame_payload_size = 2048;
  3766. nv->special_options[1] = BIT_7;
  3767. } else if (IS_QLA2200(ha)) {
  3768. nv->firmware_options[0] = BIT_2 | BIT_1;
  3769. nv->firmware_options[1] = BIT_7 | BIT_5;
  3770. nv->add_firmware_options[0] = BIT_5;
  3771. nv->add_firmware_options[1] = BIT_5 | BIT_4;
  3772. nv->frame_payload_size = 1024;
  3773. } else if (IS_QLA2100(ha)) {
  3774. nv->firmware_options[0] = BIT_3 | BIT_1;
  3775. nv->firmware_options[1] = BIT_5;
  3776. nv->frame_payload_size = 1024;
  3777. }
  3778. nv->max_iocb_allocation = cpu_to_le16(256);
  3779. nv->execution_throttle = cpu_to_le16(16);
  3780. nv->retry_count = 8;
  3781. nv->retry_delay = 1;
  3782. nv->port_name[0] = 33;
  3783. nv->port_name[3] = 224;
  3784. nv->port_name[4] = 139;
  3785. qla2xxx_nvram_wwn_from_ofw(vha, nv);
  3786. nv->login_timeout = 4;
  3787. /*
  3788. * Set default host adapter parameters
  3789. */
  3790. nv->host_p[1] = BIT_2;
  3791. nv->reset_delay = 5;
  3792. nv->port_down_retry_count = 8;
  3793. nv->max_luns_per_target = cpu_to_le16(8);
  3794. nv->link_down_timeout = 60;
  3795. rval = 1;
  3796. }
  3797. #if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
  3798. /*
  3799. * The SN2 does not provide BIOS emulation which means you can't change
  3800. * potentially bogus BIOS settings. Force the use of default settings
  3801. * for link rate and frame size. Hope that the rest of the settings
  3802. * are valid.
  3803. */
  3804. if (ia64_platform_is("sn2")) {
  3805. nv->frame_payload_size = 2048;
  3806. if (IS_QLA23XX(ha))
  3807. nv->special_options[1] = BIT_7;
  3808. }
  3809. #endif
  3810. /* Reset Initialization control block */
  3811. memset(icb, 0, ha->init_cb_size);
  3812. /*
  3813. * Setup driver NVRAM options.
  3814. */
  3815. nv->firmware_options[0] |= (BIT_6 | BIT_1);
  3816. nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
  3817. nv->firmware_options[1] |= (BIT_5 | BIT_0);
  3818. nv->firmware_options[1] &= ~BIT_4;
  3819. if (IS_QLA23XX(ha)) {
  3820. nv->firmware_options[0] |= BIT_2;
  3821. nv->firmware_options[0] &= ~BIT_3;
  3822. nv->special_options[0] &= ~BIT_6;
  3823. nv->add_firmware_options[1] |= BIT_5 | BIT_4;
  3824. if (IS_QLA2300(ha)) {
  3825. if (ha->fb_rev == FPM_2310) {
  3826. strcpy(ha->model_number, "QLA2310");
  3827. } else {
  3828. strcpy(ha->model_number, "QLA2300");
  3829. }
  3830. } else {
  3831. qla2x00_set_model_info(vha, nv->model_number,
  3832. sizeof(nv->model_number), "QLA23xx");
  3833. }
  3834. } else if (IS_QLA2200(ha)) {
  3835. nv->firmware_options[0] |= BIT_2;
  3836. /*
  3837. * 'Point-to-point preferred, else loop' is not a safe
  3838. * connection mode setting.
  3839. */
  3840. if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
  3841. (BIT_5 | BIT_4)) {
  3842. /* Force 'loop preferred, else point-to-point'. */
  3843. nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
  3844. nv->add_firmware_options[0] |= BIT_5;
  3845. }
  3846. strcpy(ha->model_number, "QLA22xx");
  3847. } else /*if (IS_QLA2100(ha))*/ {
  3848. strcpy(ha->model_number, "QLA2100");
  3849. }
  3850. /*
  3851. * Copy over NVRAM RISC parameter block to initialization control block.
  3852. */
  3853. dptr1 = (uint8_t *)icb;
  3854. dptr2 = (uint8_t *)&nv->parameter_block_version;
  3855. cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
  3856. while (cnt--)
  3857. *dptr1++ = *dptr2++;
  3858. /* Copy 2nd half. */
  3859. dptr1 = (uint8_t *)icb->add_firmware_options;
  3860. cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
  3861. while (cnt--)
  3862. *dptr1++ = *dptr2++;
  3863. ha->frame_payload_size = le16_to_cpu(icb->frame_payload_size);
  3864. /* Use alternate WWN? */
  3865. if (nv->host_p[1] & BIT_7) {
  3866. memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
  3867. memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
  3868. }
  3869. /* Prepare nodename */
  3870. if ((icb->firmware_options[1] & BIT_6) == 0) {
  3871. /*
  3872. * Firmware will apply the following mask if the nodename was
  3873. * not provided.
  3874. */
  3875. memcpy(icb->node_name, icb->port_name, WWN_SIZE);
  3876. icb->node_name[0] &= 0xF0;
  3877. }
  3878. /*
  3879. * Set host adapter parameters.
  3880. */
  3881. /*
  3882. * BIT_7 in the host-parameters section allows for modification to
  3883. * internal driver logging.
  3884. */
  3885. if (nv->host_p[0] & BIT_7)
  3886. ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
  3887. ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
  3888. /* Always load RISC code on non ISP2[12]00 chips. */
  3889. if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
  3890. ha->flags.disable_risc_code_load = 0;
  3891. ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
  3892. ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
  3893. ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
  3894. ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
  3895. ha->flags.disable_serdes = 0;
  3896. ha->operating_mode =
  3897. (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
  3898. memcpy(ha->fw_seriallink_options, nv->seriallink_options,
  3899. sizeof(ha->fw_seriallink_options));
  3900. /* save HBA serial number */
  3901. ha->serial0 = icb->port_name[5];
  3902. ha->serial1 = icb->port_name[6];
  3903. ha->serial2 = icb->port_name[7];
  3904. memcpy(vha->node_name, icb->node_name, WWN_SIZE);
  3905. memcpy(vha->port_name, icb->port_name, WWN_SIZE);
  3906. icb->execution_throttle = cpu_to_le16(0xFFFF);
  3907. ha->retry_count = nv->retry_count;
  3908. /* Set minimum login_timeout to 4 seconds. */
  3909. if (nv->login_timeout != ql2xlogintimeout)
  3910. nv->login_timeout = ql2xlogintimeout;
  3911. if (nv->login_timeout < 4)
  3912. nv->login_timeout = 4;
  3913. ha->login_timeout = nv->login_timeout;
  3914. /* Set minimum RATOV to 100 tenths of a second. */
  3915. ha->r_a_tov = 100;
  3916. ha->loop_reset_delay = nv->reset_delay;
  3917. /* Link Down Timeout = 0:
  3918. *
  3919. * When Port Down timer expires we will start returning
  3920. * I/O's to OS with "DID_NO_CONNECT".
  3921. *
  3922. * Link Down Timeout != 0:
  3923. *
  3924. * The driver waits for the link to come up after link down
  3925. * before returning I/Os to OS with "DID_NO_CONNECT".
  3926. */
  3927. if (nv->link_down_timeout == 0) {
  3928. ha->loop_down_abort_time =
  3929. (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
  3930. } else {
  3931. ha->link_down_timeout = nv->link_down_timeout;
  3932. ha->loop_down_abort_time =
  3933. (LOOP_DOWN_TIME - ha->link_down_timeout);
  3934. }
  3935. /*
  3936. * Need enough time to try and get the port back.
  3937. */
  3938. ha->port_down_retry_count = nv->port_down_retry_count;
  3939. if (qlport_down_retry)
  3940. ha->port_down_retry_count = qlport_down_retry;
  3941. /* Set login_retry_count */
  3942. ha->login_retry_count = nv->retry_count;
  3943. if (ha->port_down_retry_count == nv->port_down_retry_count &&
  3944. ha->port_down_retry_count > 3)
  3945. ha->login_retry_count = ha->port_down_retry_count;
  3946. else if (ha->port_down_retry_count > (int)ha->login_retry_count)
  3947. ha->login_retry_count = ha->port_down_retry_count;
  3948. if (ql2xloginretrycount)
  3949. ha->login_retry_count = ql2xloginretrycount;
  3950. icb->lun_enables = cpu_to_le16(0);
  3951. icb->command_resource_count = 0;
  3952. icb->immediate_notify_resource_count = 0;
  3953. icb->timeout = cpu_to_le16(0);
  3954. if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
  3955. /* Enable RIO */
  3956. icb->firmware_options[0] &= ~BIT_3;
  3957. icb->add_firmware_options[0] &=
  3958. ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
  3959. icb->add_firmware_options[0] |= BIT_2;
  3960. icb->response_accumulation_timer = 3;
  3961. icb->interrupt_delay_timer = 5;
  3962. vha->flags.process_response_queue = 1;
  3963. } else {
  3964. /* Enable ZIO. */
  3965. if (!vha->flags.init_done) {
  3966. ha->zio_mode = icb->add_firmware_options[0] &
  3967. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  3968. ha->zio_timer = icb->interrupt_delay_timer ?
  3969. icb->interrupt_delay_timer: 2;
  3970. }
  3971. icb->add_firmware_options[0] &=
  3972. ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
  3973. vha->flags.process_response_queue = 0;
  3974. if (ha->zio_mode != QLA_ZIO_DISABLED) {
  3975. ha->zio_mode = QLA_ZIO_MODE_6;
  3976. ql_log(ql_log_info, vha, 0x0068,
  3977. "ZIO mode %d enabled; timer delay (%d us).\n",
  3978. ha->zio_mode, ha->zio_timer * 100);
  3979. icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
  3980. icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
  3981. vha->flags.process_response_queue = 1;
  3982. }
  3983. }
  3984. if (rval) {
  3985. ql_log(ql_log_warn, vha, 0x0069,
  3986. "NVRAM configuration failed.\n");
  3987. }
  3988. return (rval);
  3989. }
  3990. static void
  3991. qla2x00_rport_del(void *data)
  3992. {
  3993. fc_port_t *fcport = data;
  3994. struct fc_rport *rport;
  3995. unsigned long flags;
  3996. spin_lock_irqsave(fcport->vha->host->host_lock, flags);
  3997. rport = fcport->drport ? fcport->drport: fcport->rport;
  3998. fcport->drport = NULL;
  3999. spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
  4000. if (rport) {
  4001. ql_dbg(ql_dbg_disc, fcport->vha, 0x210b,
  4002. "%s %8phN. rport %p roles %x\n",
  4003. __func__, fcport->port_name, rport,
  4004. rport->roles);
  4005. fc_remote_port_delete(rport);
  4006. }
  4007. }
  4008. /**
  4009. * qla2x00_alloc_fcport() - Allocate a generic fcport.
  4010. * @vha: HA context
  4011. * @flags: allocation flags
  4012. *
  4013. * Returns a pointer to the allocated fcport, or NULL, if none available.
  4014. */
  4015. fc_port_t *
  4016. qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
  4017. {
  4018. fc_port_t *fcport;
  4019. fcport = kzalloc(sizeof(fc_port_t), flags);
  4020. if (!fcport)
  4021. return NULL;
  4022. /* Setup fcport template structure. */
  4023. fcport->vha = vha;
  4024. fcport->port_type = FCT_UNKNOWN;
  4025. fcport->loop_id = FC_NO_LOOP_ID;
  4026. qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
  4027. fcport->supported_classes = FC_COS_UNSPECIFIED;
  4028. fcport->fp_speed = PORT_SPEED_UNKNOWN;
  4029. fcport->ct_desc.ct_sns = dma_alloc_coherent(&vha->hw->pdev->dev,
  4030. sizeof(struct ct_sns_pkt), &fcport->ct_desc.ct_sns_dma,
  4031. flags);
  4032. fcport->disc_state = DSC_DELETED;
  4033. fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
  4034. fcport->deleted = QLA_SESS_DELETED;
  4035. fcport->login_retry = vha->hw->login_retry_count;
  4036. fcport->logout_on_delete = 1;
  4037. if (!fcport->ct_desc.ct_sns) {
  4038. ql_log(ql_log_warn, vha, 0xd049,
  4039. "Failed to allocate ct_sns request.\n");
  4040. kfree(fcport);
  4041. return NULL;
  4042. }
  4043. INIT_WORK(&fcport->del_work, qla24xx_delete_sess_fn);
  4044. INIT_LIST_HEAD(&fcport->gnl_entry);
  4045. INIT_LIST_HEAD(&fcport->list);
  4046. return fcport;
  4047. }
  4048. void
  4049. qla2x00_free_fcport(fc_port_t *fcport)
  4050. {
  4051. if (fcport->ct_desc.ct_sns) {
  4052. dma_free_coherent(&fcport->vha->hw->pdev->dev,
  4053. sizeof(struct ct_sns_pkt), fcport->ct_desc.ct_sns,
  4054. fcport->ct_desc.ct_sns_dma);
  4055. fcport->ct_desc.ct_sns = NULL;
  4056. }
  4057. kfree(fcport);
  4058. }
  4059. /*
  4060. * qla2x00_configure_loop
  4061. * Updates Fibre Channel Device Database with what is actually on loop.
  4062. *
  4063. * Input:
  4064. * ha = adapter block pointer.
  4065. *
  4066. * Returns:
  4067. * 0 = success.
  4068. * 1 = error.
  4069. * 2 = database was full and device was not configured.
  4070. */
  4071. static int
  4072. qla2x00_configure_loop(scsi_qla_host_t *vha)
  4073. {
  4074. int rval;
  4075. unsigned long flags, save_flags;
  4076. struct qla_hw_data *ha = vha->hw;
  4077. rval = QLA_SUCCESS;
  4078. /* Get Initiator ID */
  4079. if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
  4080. rval = qla2x00_configure_hba(vha);
  4081. if (rval != QLA_SUCCESS) {
  4082. ql_dbg(ql_dbg_disc, vha, 0x2013,
  4083. "Unable to configure HBA.\n");
  4084. return (rval);
  4085. }
  4086. }
  4087. save_flags = flags = vha->dpc_flags;
  4088. ql_dbg(ql_dbg_disc, vha, 0x2014,
  4089. "Configure loop -- dpc flags = 0x%lx.\n", flags);
  4090. /*
  4091. * If we have both an RSCN and PORT UPDATE pending then handle them
  4092. * both at the same time.
  4093. */
  4094. clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  4095. clear_bit(RSCN_UPDATE, &vha->dpc_flags);
  4096. qla2x00_get_data_rate(vha);
  4097. /* Determine what we need to do */
  4098. if (ha->current_topology == ISP_CFG_FL &&
  4099. (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
  4100. set_bit(RSCN_UPDATE, &flags);
  4101. } else if (ha->current_topology == ISP_CFG_F &&
  4102. (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
  4103. set_bit(RSCN_UPDATE, &flags);
  4104. clear_bit(LOCAL_LOOP_UPDATE, &flags);
  4105. } else if (ha->current_topology == ISP_CFG_NL ||
  4106. ha->current_topology == ISP_CFG_N) {
  4107. clear_bit(RSCN_UPDATE, &flags);
  4108. set_bit(LOCAL_LOOP_UPDATE, &flags);
  4109. } else if (!vha->flags.online ||
  4110. (test_bit(ABORT_ISP_ACTIVE, &flags))) {
  4111. set_bit(RSCN_UPDATE, &flags);
  4112. set_bit(LOCAL_LOOP_UPDATE, &flags);
  4113. }
  4114. if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
  4115. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
  4116. ql_dbg(ql_dbg_disc, vha, 0x2015,
  4117. "Loop resync needed, failing.\n");
  4118. rval = QLA_FUNCTION_FAILED;
  4119. } else
  4120. rval = qla2x00_configure_local_loop(vha);
  4121. }
  4122. if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
  4123. if (LOOP_TRANSITION(vha)) {
  4124. ql_dbg(ql_dbg_disc, vha, 0x2099,
  4125. "Needs RSCN update and loop transition.\n");
  4126. rval = QLA_FUNCTION_FAILED;
  4127. }
  4128. else
  4129. rval = qla2x00_configure_fabric(vha);
  4130. }
  4131. if (rval == QLA_SUCCESS) {
  4132. if (atomic_read(&vha->loop_down_timer) ||
  4133. test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
  4134. rval = QLA_FUNCTION_FAILED;
  4135. } else {
  4136. atomic_set(&vha->loop_state, LOOP_READY);
  4137. ql_dbg(ql_dbg_disc, vha, 0x2069,
  4138. "LOOP READY.\n");
  4139. ha->flags.fw_init_done = 1;
  4140. /*
  4141. * Process any ATIO queue entries that came in
  4142. * while we weren't online.
  4143. */
  4144. if (qla_tgt_mode_enabled(vha) ||
  4145. qla_dual_mode_enabled(vha)) {
  4146. spin_lock_irqsave(&ha->tgt.atio_lock, flags);
  4147. qlt_24xx_process_atio_queue(vha, 0);
  4148. spin_unlock_irqrestore(&ha->tgt.atio_lock,
  4149. flags);
  4150. }
  4151. }
  4152. }
  4153. if (rval) {
  4154. ql_dbg(ql_dbg_disc, vha, 0x206a,
  4155. "%s *** FAILED ***.\n", __func__);
  4156. } else {
  4157. ql_dbg(ql_dbg_disc, vha, 0x206b,
  4158. "%s: exiting normally.\n", __func__);
  4159. }
  4160. /* Restore state if a resync event occurred during processing */
  4161. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
  4162. if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
  4163. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  4164. if (test_bit(RSCN_UPDATE, &save_flags)) {
  4165. set_bit(RSCN_UPDATE, &vha->dpc_flags);
  4166. }
  4167. }
  4168. return (rval);
  4169. }
  4170. /*
  4171. * qla2x00_configure_local_loop
  4172. * Updates Fibre Channel Device Database with local loop devices.
  4173. *
  4174. * Input:
  4175. * ha = adapter block pointer.
  4176. *
  4177. * Returns:
  4178. * 0 = success.
  4179. */
  4180. static int
  4181. qla2x00_configure_local_loop(scsi_qla_host_t *vha)
  4182. {
  4183. int rval, rval2;
  4184. int found_devs;
  4185. int found;
  4186. fc_port_t *fcport, *new_fcport;
  4187. uint16_t index;
  4188. uint16_t entries;
  4189. char *id_iter;
  4190. uint16_t loop_id;
  4191. uint8_t domain, area, al_pa;
  4192. struct qla_hw_data *ha = vha->hw;
  4193. unsigned long flags;
  4194. /* Inititae N2N login. */
  4195. if (test_and_clear_bit(N2N_LOGIN_NEEDED, &vha->dpc_flags)) {
  4196. /* borrowing */
  4197. u32 *bp, i, sz;
  4198. memset(ha->init_cb, 0, ha->init_cb_size);
  4199. sz = min_t(int, sizeof(struct els_plogi_payload),
  4200. ha->init_cb_size);
  4201. rval = qla24xx_get_port_login_templ(vha, ha->init_cb_dma,
  4202. (void *)ha->init_cb, sz);
  4203. if (rval == QLA_SUCCESS) {
  4204. bp = (uint32_t *)ha->init_cb;
  4205. for (i = 0; i < sz/4 ; i++, bp++)
  4206. *bp = cpu_to_be32(*bp);
  4207. memcpy(&ha->plogi_els_payld.data, (void *)ha->init_cb,
  4208. sizeof(ha->plogi_els_payld.data));
  4209. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  4210. } else {
  4211. ql_dbg(ql_dbg_init, vha, 0x00d1,
  4212. "PLOGI ELS param read fail.\n");
  4213. }
  4214. return QLA_SUCCESS;
  4215. }
  4216. found_devs = 0;
  4217. new_fcport = NULL;
  4218. entries = MAX_FIBRE_DEVICES_LOOP;
  4219. /* Get list of logged in devices. */
  4220. memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
  4221. rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
  4222. &entries);
  4223. if (rval != QLA_SUCCESS)
  4224. goto cleanup_allocation;
  4225. ql_dbg(ql_dbg_disc, vha, 0x2011,
  4226. "Entries in ID list (%d).\n", entries);
  4227. ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
  4228. (uint8_t *)ha->gid_list,
  4229. entries * sizeof(struct gid_list_info));
  4230. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  4231. fcport->scan_state = QLA_FCPORT_SCAN;
  4232. }
  4233. /* Allocate temporary fcport for any new fcports discovered. */
  4234. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  4235. if (new_fcport == NULL) {
  4236. ql_log(ql_log_warn, vha, 0x2012,
  4237. "Memory allocation failed for fcport.\n");
  4238. rval = QLA_MEMORY_ALLOC_FAILED;
  4239. goto cleanup_allocation;
  4240. }
  4241. new_fcport->flags &= ~FCF_FABRIC_DEVICE;
  4242. /* Add devices to port list. */
  4243. id_iter = (char *)ha->gid_list;
  4244. for (index = 0; index < entries; index++) {
  4245. domain = ((struct gid_list_info *)id_iter)->domain;
  4246. area = ((struct gid_list_info *)id_iter)->area;
  4247. al_pa = ((struct gid_list_info *)id_iter)->al_pa;
  4248. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  4249. loop_id = (uint16_t)
  4250. ((struct gid_list_info *)id_iter)->loop_id_2100;
  4251. else
  4252. loop_id = le16_to_cpu(
  4253. ((struct gid_list_info *)id_iter)->loop_id);
  4254. id_iter += ha->gid_list_info_size;
  4255. /* Bypass reserved domain fields. */
  4256. if ((domain & 0xf0) == 0xf0)
  4257. continue;
  4258. /* Bypass if not same domain and area of adapter. */
  4259. if (area && domain &&
  4260. (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
  4261. continue;
  4262. /* Bypass invalid local loop ID. */
  4263. if (loop_id > LAST_LOCAL_LOOP_ID)
  4264. continue;
  4265. memset(new_fcport->port_name, 0, WWN_SIZE);
  4266. /* Fill in member data. */
  4267. new_fcport->d_id.b.domain = domain;
  4268. new_fcport->d_id.b.area = area;
  4269. new_fcport->d_id.b.al_pa = al_pa;
  4270. new_fcport->loop_id = loop_id;
  4271. new_fcport->scan_state = QLA_FCPORT_FOUND;
  4272. rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
  4273. if (rval2 != QLA_SUCCESS) {
  4274. ql_dbg(ql_dbg_disc, vha, 0x2097,
  4275. "Failed to retrieve fcport information "
  4276. "-- get_port_database=%x, loop_id=0x%04x.\n",
  4277. rval2, new_fcport->loop_id);
  4278. /* Skip retry if N2N */
  4279. if (ha->current_topology != ISP_CFG_N) {
  4280. ql_dbg(ql_dbg_disc, vha, 0x2105,
  4281. "Scheduling resync.\n");
  4282. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  4283. continue;
  4284. }
  4285. }
  4286. spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
  4287. /* Check for matching device in port list. */
  4288. found = 0;
  4289. fcport = NULL;
  4290. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  4291. if (memcmp(new_fcport->port_name, fcport->port_name,
  4292. WWN_SIZE))
  4293. continue;
  4294. fcport->flags &= ~FCF_FABRIC_DEVICE;
  4295. fcport->loop_id = new_fcport->loop_id;
  4296. fcport->port_type = new_fcport->port_type;
  4297. fcport->d_id.b24 = new_fcport->d_id.b24;
  4298. memcpy(fcport->node_name, new_fcport->node_name,
  4299. WWN_SIZE);
  4300. fcport->scan_state = QLA_FCPORT_FOUND;
  4301. found++;
  4302. break;
  4303. }
  4304. if (!found) {
  4305. /* New device, add to fcports list. */
  4306. list_add_tail(&new_fcport->list, &vha->vp_fcports);
  4307. /* Allocate a new replacement fcport. */
  4308. fcport = new_fcport;
  4309. spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
  4310. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  4311. if (new_fcport == NULL) {
  4312. ql_log(ql_log_warn, vha, 0xd031,
  4313. "Failed to allocate memory for fcport.\n");
  4314. rval = QLA_MEMORY_ALLOC_FAILED;
  4315. goto cleanup_allocation;
  4316. }
  4317. spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
  4318. new_fcport->flags &= ~FCF_FABRIC_DEVICE;
  4319. }
  4320. spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
  4321. /* Base iIDMA settings on HBA port speed. */
  4322. fcport->fp_speed = ha->link_data_rate;
  4323. found_devs++;
  4324. }
  4325. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  4326. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  4327. break;
  4328. if (fcport->scan_state == QLA_FCPORT_SCAN) {
  4329. if ((qla_dual_mode_enabled(vha) ||
  4330. qla_ini_mode_enabled(vha)) &&
  4331. atomic_read(&fcport->state) == FCS_ONLINE) {
  4332. qla2x00_mark_device_lost(vha, fcport,
  4333. ql2xplogiabsentdevice, 0);
  4334. if (fcport->loop_id != FC_NO_LOOP_ID &&
  4335. (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
  4336. fcport->port_type != FCT_INITIATOR &&
  4337. fcport->port_type != FCT_BROADCAST) {
  4338. ql_dbg(ql_dbg_disc, vha, 0x20f0,
  4339. "%s %d %8phC post del sess\n",
  4340. __func__, __LINE__,
  4341. fcport->port_name);
  4342. qlt_schedule_sess_for_deletion(fcport);
  4343. continue;
  4344. }
  4345. }
  4346. }
  4347. if (fcport->scan_state == QLA_FCPORT_FOUND)
  4348. qla24xx_fcport_handle_login(vha, fcport);
  4349. }
  4350. cleanup_allocation:
  4351. kfree(new_fcport);
  4352. if (rval != QLA_SUCCESS) {
  4353. ql_dbg(ql_dbg_disc, vha, 0x2098,
  4354. "Configure local loop error exit: rval=%x.\n", rval);
  4355. }
  4356. return (rval);
  4357. }
  4358. static void
  4359. qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
  4360. {
  4361. int rval;
  4362. uint16_t mb[MAILBOX_REGISTER_COUNT];
  4363. struct qla_hw_data *ha = vha->hw;
  4364. if (!IS_IIDMA_CAPABLE(ha))
  4365. return;
  4366. if (atomic_read(&fcport->state) != FCS_ONLINE)
  4367. return;
  4368. if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
  4369. fcport->fp_speed > ha->link_data_rate ||
  4370. !ha->flags.gpsc_supported)
  4371. return;
  4372. rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
  4373. mb);
  4374. if (rval != QLA_SUCCESS) {
  4375. ql_dbg(ql_dbg_disc, vha, 0x2004,
  4376. "Unable to adjust iIDMA %8phN -- %04x %x %04x %04x.\n",
  4377. fcport->port_name, rval, fcport->fp_speed, mb[0], mb[1]);
  4378. } else {
  4379. ql_dbg(ql_dbg_disc, vha, 0x2005,
  4380. "iIDMA adjusted to %s GB/s (%X) on %8phN.\n",
  4381. qla2x00_get_link_speed_str(ha, fcport->fp_speed),
  4382. fcport->fp_speed, fcport->port_name);
  4383. }
  4384. }
  4385. void qla_do_iidma_work(struct scsi_qla_host *vha, fc_port_t *fcport)
  4386. {
  4387. qla2x00_iidma_fcport(vha, fcport);
  4388. qla24xx_update_fcport_fcp_prio(vha, fcport);
  4389. }
  4390. int qla_post_iidma_work(struct scsi_qla_host *vha, fc_port_t *fcport)
  4391. {
  4392. struct qla_work_evt *e;
  4393. e = qla2x00_alloc_work(vha, QLA_EVT_IIDMA);
  4394. if (!e)
  4395. return QLA_FUNCTION_FAILED;
  4396. e->u.fcport.fcport = fcport;
  4397. return qla2x00_post_work(vha, e);
  4398. }
  4399. /* qla2x00_reg_remote_port is reserved for Initiator Mode only.*/
  4400. static void
  4401. qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
  4402. {
  4403. struct fc_rport_identifiers rport_ids;
  4404. struct fc_rport *rport;
  4405. unsigned long flags;
  4406. if (atomic_read(&fcport->state) == FCS_ONLINE)
  4407. return;
  4408. rport_ids.node_name = wwn_to_u64(fcport->node_name);
  4409. rport_ids.port_name = wwn_to_u64(fcport->port_name);
  4410. rport_ids.port_id = fcport->d_id.b.domain << 16 |
  4411. fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
  4412. rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
  4413. fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
  4414. if (!rport) {
  4415. ql_log(ql_log_warn, vha, 0x2006,
  4416. "Unable to allocate fc remote port.\n");
  4417. return;
  4418. }
  4419. spin_lock_irqsave(fcport->vha->host->host_lock, flags);
  4420. *((fc_port_t **)rport->dd_data) = fcport;
  4421. spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
  4422. rport->supported_classes = fcport->supported_classes;
  4423. rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
  4424. if (fcport->port_type == FCT_INITIATOR)
  4425. rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
  4426. if (fcport->port_type == FCT_TARGET)
  4427. rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
  4428. ql_dbg(ql_dbg_disc, vha, 0x20ee,
  4429. "%s %8phN. rport %p is %s mode\n",
  4430. __func__, fcport->port_name, rport,
  4431. (fcport->port_type == FCT_TARGET) ? "tgt" : "ini");
  4432. fc_remote_port_rolechg(rport, rport_ids.roles);
  4433. }
  4434. /*
  4435. * qla2x00_update_fcport
  4436. * Updates device on list.
  4437. *
  4438. * Input:
  4439. * ha = adapter block pointer.
  4440. * fcport = port structure pointer.
  4441. *
  4442. * Return:
  4443. * 0 - Success
  4444. * BIT_0 - error
  4445. *
  4446. * Context:
  4447. * Kernel context.
  4448. */
  4449. void
  4450. qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
  4451. {
  4452. fcport->vha = vha;
  4453. if (IS_SW_RESV_ADDR(fcport->d_id))
  4454. return;
  4455. fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
  4456. fcport->disc_state = DSC_LOGIN_COMPLETE;
  4457. fcport->deleted = 0;
  4458. fcport->logout_on_delete = 1;
  4459. fcport->login_retry = vha->hw->login_retry_count;
  4460. fcport->n2n_chip_reset = fcport->n2n_link_reset_cnt = 0;
  4461. qla2x00_iidma_fcport(vha, fcport);
  4462. switch (vha->hw->current_topology) {
  4463. case ISP_CFG_N:
  4464. case ISP_CFG_NL:
  4465. fcport->keep_nport_handle = 1;
  4466. break;
  4467. default:
  4468. break;
  4469. }
  4470. if (fcport->fc4f_nvme) {
  4471. qla_nvme_register_remote(vha, fcport);
  4472. fcport->disc_state = DSC_LOGIN_COMPLETE;
  4473. qla2x00_set_fcport_state(fcport, FCS_ONLINE);
  4474. return;
  4475. }
  4476. qla24xx_update_fcport_fcp_prio(vha, fcport);
  4477. switch (vha->host->active_mode) {
  4478. case MODE_INITIATOR:
  4479. qla2x00_reg_remote_port(vha, fcport);
  4480. break;
  4481. case MODE_TARGET:
  4482. if (!vha->vha_tgt.qla_tgt->tgt_stop &&
  4483. !vha->vha_tgt.qla_tgt->tgt_stopped)
  4484. qlt_fc_port_added(vha, fcport);
  4485. break;
  4486. case MODE_DUAL:
  4487. qla2x00_reg_remote_port(vha, fcport);
  4488. if (!vha->vha_tgt.qla_tgt->tgt_stop &&
  4489. !vha->vha_tgt.qla_tgt->tgt_stopped)
  4490. qlt_fc_port_added(vha, fcport);
  4491. break;
  4492. default:
  4493. break;
  4494. }
  4495. if (IS_IIDMA_CAPABLE(vha->hw) && vha->hw->flags.gpsc_supported) {
  4496. if (fcport->id_changed) {
  4497. fcport->id_changed = 0;
  4498. ql_dbg(ql_dbg_disc, vha, 0x20d7,
  4499. "%s %d %8phC post gfpnid fcp_cnt %d\n",
  4500. __func__, __LINE__, fcport->port_name,
  4501. vha->fcport_count);
  4502. qla24xx_post_gfpnid_work(vha, fcport);
  4503. } else {
  4504. ql_dbg(ql_dbg_disc, vha, 0x20d7,
  4505. "%s %d %8phC post gpsc fcp_cnt %d\n",
  4506. __func__, __LINE__, fcport->port_name,
  4507. vha->fcport_count);
  4508. qla24xx_post_gpsc_work(vha, fcport);
  4509. }
  4510. }
  4511. qla2x00_set_fcport_state(fcport, FCS_ONLINE);
  4512. }
  4513. /*
  4514. * qla2x00_configure_fabric
  4515. * Setup SNS devices with loop ID's.
  4516. *
  4517. * Input:
  4518. * ha = adapter block pointer.
  4519. *
  4520. * Returns:
  4521. * 0 = success.
  4522. * BIT_0 = error
  4523. */
  4524. static int
  4525. qla2x00_configure_fabric(scsi_qla_host_t *vha)
  4526. {
  4527. int rval;
  4528. fc_port_t *fcport;
  4529. uint16_t mb[MAILBOX_REGISTER_COUNT];
  4530. uint16_t loop_id;
  4531. LIST_HEAD(new_fcports);
  4532. struct qla_hw_data *ha = vha->hw;
  4533. int discovery_gen;
  4534. /* If FL port exists, then SNS is present */
  4535. if (IS_FWI2_CAPABLE(ha))
  4536. loop_id = NPH_F_PORT;
  4537. else
  4538. loop_id = SNS_FL_PORT;
  4539. rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
  4540. if (rval != QLA_SUCCESS) {
  4541. ql_dbg(ql_dbg_disc, vha, 0x20a0,
  4542. "MBX_GET_PORT_NAME failed, No FL Port.\n");
  4543. vha->device_flags &= ~SWITCH_FOUND;
  4544. return (QLA_SUCCESS);
  4545. }
  4546. vha->device_flags |= SWITCH_FOUND;
  4547. if (qla_tgt_mode_enabled(vha) || qla_dual_mode_enabled(vha)) {
  4548. rval = qla2x00_send_change_request(vha, 0x3, 0);
  4549. if (rval != QLA_SUCCESS)
  4550. ql_log(ql_log_warn, vha, 0x121,
  4551. "Failed to enable receiving of RSCN requests: 0x%x.\n",
  4552. rval);
  4553. }
  4554. do {
  4555. qla2x00_mgmt_svr_login(vha);
  4556. /* FDMI support. */
  4557. if (ql2xfdmienable &&
  4558. test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
  4559. qla2x00_fdmi_register(vha);
  4560. /* Ensure we are logged into the SNS. */
  4561. loop_id = NPH_SNS_LID(ha);
  4562. rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
  4563. 0xfc, mb, BIT_1|BIT_0);
  4564. if (rval != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
  4565. ql_dbg(ql_dbg_disc, vha, 0x20a1,
  4566. "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[6]=%x mb[7]=%x (%x).\n",
  4567. loop_id, mb[0], mb[1], mb[2], mb[6], mb[7], rval);
  4568. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  4569. return rval;
  4570. }
  4571. if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
  4572. if (qla2x00_rft_id(vha)) {
  4573. /* EMPTY */
  4574. ql_dbg(ql_dbg_disc, vha, 0x20a2,
  4575. "Register FC-4 TYPE failed.\n");
  4576. if (test_bit(LOOP_RESYNC_NEEDED,
  4577. &vha->dpc_flags))
  4578. break;
  4579. }
  4580. if (qla2x00_rff_id(vha, FC4_TYPE_FCP_SCSI)) {
  4581. /* EMPTY */
  4582. ql_dbg(ql_dbg_disc, vha, 0x209a,
  4583. "Register FC-4 Features failed.\n");
  4584. if (test_bit(LOOP_RESYNC_NEEDED,
  4585. &vha->dpc_flags))
  4586. break;
  4587. }
  4588. if (vha->flags.nvme_enabled) {
  4589. if (qla2x00_rff_id(vha, FC_TYPE_NVME)) {
  4590. ql_dbg(ql_dbg_disc, vha, 0x2049,
  4591. "Register NVME FC Type Features failed.\n");
  4592. }
  4593. }
  4594. if (qla2x00_rnn_id(vha)) {
  4595. /* EMPTY */
  4596. ql_dbg(ql_dbg_disc, vha, 0x2104,
  4597. "Register Node Name failed.\n");
  4598. if (test_bit(LOOP_RESYNC_NEEDED,
  4599. &vha->dpc_flags))
  4600. break;
  4601. } else if (qla2x00_rsnn_nn(vha)) {
  4602. /* EMPTY */
  4603. ql_dbg(ql_dbg_disc, vha, 0x209b,
  4604. "Register Symbolic Node Name failed.\n");
  4605. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  4606. break;
  4607. }
  4608. }
  4609. /* Mark the time right before querying FW for connected ports.
  4610. * This process is long, asynchronous and by the time it's done,
  4611. * collected information might not be accurate anymore. E.g.
  4612. * disconnected port might have re-connected and a brand new
  4613. * session has been created. In this case session's generation
  4614. * will be newer than discovery_gen. */
  4615. qlt_do_generation_tick(vha, &discovery_gen);
  4616. if (USE_ASYNC_SCAN(ha)) {
  4617. rval = qla24xx_async_gpnft(vha, FC4_TYPE_FCP_SCSI,
  4618. NULL);
  4619. if (rval)
  4620. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  4621. } else {
  4622. list_for_each_entry(fcport, &vha->vp_fcports, list)
  4623. fcport->scan_state = QLA_FCPORT_SCAN;
  4624. rval = qla2x00_find_all_fabric_devs(vha);
  4625. }
  4626. if (rval != QLA_SUCCESS)
  4627. break;
  4628. } while (0);
  4629. if (!vha->nvme_local_port && vha->flags.nvme_enabled)
  4630. qla_nvme_register_hba(vha);
  4631. if (rval)
  4632. ql_dbg(ql_dbg_disc, vha, 0x2068,
  4633. "Configure fabric error exit rval=%d.\n", rval);
  4634. return (rval);
  4635. }
  4636. /*
  4637. * qla2x00_find_all_fabric_devs
  4638. *
  4639. * Input:
  4640. * ha = adapter block pointer.
  4641. * dev = database device entry pointer.
  4642. *
  4643. * Returns:
  4644. * 0 = success.
  4645. *
  4646. * Context:
  4647. * Kernel context.
  4648. */
  4649. static int
  4650. qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha)
  4651. {
  4652. int rval;
  4653. uint16_t loop_id;
  4654. fc_port_t *fcport, *new_fcport;
  4655. int found;
  4656. sw_info_t *swl;
  4657. int swl_idx;
  4658. int first_dev, last_dev;
  4659. port_id_t wrap = {}, nxt_d_id;
  4660. struct qla_hw_data *ha = vha->hw;
  4661. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  4662. unsigned long flags;
  4663. rval = QLA_SUCCESS;
  4664. /* Try GID_PT to get device list, else GAN. */
  4665. if (!ha->swl)
  4666. ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
  4667. GFP_KERNEL);
  4668. swl = ha->swl;
  4669. if (!swl) {
  4670. /*EMPTY*/
  4671. ql_dbg(ql_dbg_disc, vha, 0x209c,
  4672. "GID_PT allocations failed, fallback on GA_NXT.\n");
  4673. } else {
  4674. memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
  4675. if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
  4676. swl = NULL;
  4677. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  4678. return rval;
  4679. } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
  4680. swl = NULL;
  4681. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  4682. return rval;
  4683. } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
  4684. swl = NULL;
  4685. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  4686. return rval;
  4687. } else if (qla2x00_gfpn_id(vha, swl) != QLA_SUCCESS) {
  4688. swl = NULL;
  4689. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  4690. return rval;
  4691. }
  4692. /* If other queries succeeded probe for FC-4 type */
  4693. if (swl) {
  4694. qla2x00_gff_id(vha, swl);
  4695. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  4696. return rval;
  4697. }
  4698. }
  4699. swl_idx = 0;
  4700. /* Allocate temporary fcport for any new fcports discovered. */
  4701. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  4702. if (new_fcport == NULL) {
  4703. ql_log(ql_log_warn, vha, 0x209d,
  4704. "Failed to allocate memory for fcport.\n");
  4705. return (QLA_MEMORY_ALLOC_FAILED);
  4706. }
  4707. new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
  4708. /* Set start port ID scan at adapter ID. */
  4709. first_dev = 1;
  4710. last_dev = 0;
  4711. /* Starting free loop ID. */
  4712. loop_id = ha->min_external_loopid;
  4713. for (; loop_id <= ha->max_loop_id; loop_id++) {
  4714. if (qla2x00_is_reserved_id(vha, loop_id))
  4715. continue;
  4716. if (ha->current_topology == ISP_CFG_FL &&
  4717. (atomic_read(&vha->loop_down_timer) ||
  4718. LOOP_TRANSITION(vha))) {
  4719. atomic_set(&vha->loop_down_timer, 0);
  4720. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  4721. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  4722. break;
  4723. }
  4724. if (swl != NULL) {
  4725. if (last_dev) {
  4726. wrap.b24 = new_fcport->d_id.b24;
  4727. } else {
  4728. new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
  4729. memcpy(new_fcport->node_name,
  4730. swl[swl_idx].node_name, WWN_SIZE);
  4731. memcpy(new_fcport->port_name,
  4732. swl[swl_idx].port_name, WWN_SIZE);
  4733. memcpy(new_fcport->fabric_port_name,
  4734. swl[swl_idx].fabric_port_name, WWN_SIZE);
  4735. new_fcport->fp_speed = swl[swl_idx].fp_speed;
  4736. new_fcport->fc4_type = swl[swl_idx].fc4_type;
  4737. new_fcport->nvme_flag = 0;
  4738. new_fcport->fc4f_nvme = 0;
  4739. if (vha->flags.nvme_enabled &&
  4740. swl[swl_idx].fc4f_nvme) {
  4741. new_fcport->fc4f_nvme =
  4742. swl[swl_idx].fc4f_nvme;
  4743. ql_log(ql_log_info, vha, 0x2131,
  4744. "FOUND: NVME port %8phC as FC Type 28h\n",
  4745. new_fcport->port_name);
  4746. }
  4747. if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
  4748. last_dev = 1;
  4749. }
  4750. swl_idx++;
  4751. }
  4752. } else {
  4753. /* Send GA_NXT to the switch */
  4754. rval = qla2x00_ga_nxt(vha, new_fcport);
  4755. if (rval != QLA_SUCCESS) {
  4756. ql_log(ql_log_warn, vha, 0x209e,
  4757. "SNS scan failed -- assuming "
  4758. "zero-entry result.\n");
  4759. rval = QLA_SUCCESS;
  4760. break;
  4761. }
  4762. }
  4763. /* If wrap on switch device list, exit. */
  4764. if (first_dev) {
  4765. wrap.b24 = new_fcport->d_id.b24;
  4766. first_dev = 0;
  4767. } else if (new_fcport->d_id.b24 == wrap.b24) {
  4768. ql_dbg(ql_dbg_disc, vha, 0x209f,
  4769. "Device wrap (%02x%02x%02x).\n",
  4770. new_fcport->d_id.b.domain,
  4771. new_fcport->d_id.b.area,
  4772. new_fcport->d_id.b.al_pa);
  4773. break;
  4774. }
  4775. /* Bypass if same physical adapter. */
  4776. if (new_fcport->d_id.b24 == base_vha->d_id.b24)
  4777. continue;
  4778. /* Bypass virtual ports of the same host. */
  4779. if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24))
  4780. continue;
  4781. /* Bypass if same domain and area of adapter. */
  4782. if (((new_fcport->d_id.b24 & 0xffff00) ==
  4783. (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
  4784. ISP_CFG_FL)
  4785. continue;
  4786. /* Bypass reserved domain fields. */
  4787. if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
  4788. continue;
  4789. /* Bypass ports whose FCP-4 type is not FCP_SCSI */
  4790. if (ql2xgffidenable &&
  4791. (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
  4792. new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
  4793. continue;
  4794. spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
  4795. /* Locate matching device in database. */
  4796. found = 0;
  4797. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  4798. if (memcmp(new_fcport->port_name, fcport->port_name,
  4799. WWN_SIZE))
  4800. continue;
  4801. fcport->scan_state = QLA_FCPORT_FOUND;
  4802. found++;
  4803. /* Update port state. */
  4804. memcpy(fcport->fabric_port_name,
  4805. new_fcport->fabric_port_name, WWN_SIZE);
  4806. fcport->fp_speed = new_fcport->fp_speed;
  4807. /*
  4808. * If address the same and state FCS_ONLINE
  4809. * (or in target mode), nothing changed.
  4810. */
  4811. if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
  4812. (atomic_read(&fcport->state) == FCS_ONLINE ||
  4813. (vha->host->active_mode == MODE_TARGET))) {
  4814. break;
  4815. }
  4816. /*
  4817. * If device was not a fabric device before.
  4818. */
  4819. if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
  4820. fcport->d_id.b24 = new_fcport->d_id.b24;
  4821. qla2x00_clear_loop_id(fcport);
  4822. fcport->flags |= (FCF_FABRIC_DEVICE |
  4823. FCF_LOGIN_NEEDED);
  4824. break;
  4825. }
  4826. /*
  4827. * Port ID changed or device was marked to be updated;
  4828. * Log it out if still logged in and mark it for
  4829. * relogin later.
  4830. */
  4831. if (qla_tgt_mode_enabled(base_vha)) {
  4832. ql_dbg(ql_dbg_tgt_mgt, vha, 0xf080,
  4833. "port changed FC ID, %8phC"
  4834. " old %x:%x:%x (loop_id 0x%04x)-> new %x:%x:%x\n",
  4835. fcport->port_name,
  4836. fcport->d_id.b.domain,
  4837. fcport->d_id.b.area,
  4838. fcport->d_id.b.al_pa,
  4839. fcport->loop_id,
  4840. new_fcport->d_id.b.domain,
  4841. new_fcport->d_id.b.area,
  4842. new_fcport->d_id.b.al_pa);
  4843. fcport->d_id.b24 = new_fcport->d_id.b24;
  4844. break;
  4845. }
  4846. fcport->d_id.b24 = new_fcport->d_id.b24;
  4847. fcport->flags |= FCF_LOGIN_NEEDED;
  4848. break;
  4849. }
  4850. if (fcport->fc4f_nvme) {
  4851. if (fcport->disc_state == DSC_DELETE_PEND) {
  4852. fcport->disc_state = DSC_GNL;
  4853. vha->fcport_count--;
  4854. fcport->login_succ = 0;
  4855. }
  4856. }
  4857. if (found) {
  4858. spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
  4859. continue;
  4860. }
  4861. /* If device was not in our fcports list, then add it. */
  4862. new_fcport->scan_state = QLA_FCPORT_FOUND;
  4863. list_add_tail(&new_fcport->list, &vha->vp_fcports);
  4864. spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
  4865. /* Allocate a new replacement fcport. */
  4866. nxt_d_id.b24 = new_fcport->d_id.b24;
  4867. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  4868. if (new_fcport == NULL) {
  4869. ql_log(ql_log_warn, vha, 0xd032,
  4870. "Memory allocation failed for fcport.\n");
  4871. return (QLA_MEMORY_ALLOC_FAILED);
  4872. }
  4873. new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
  4874. new_fcport->d_id.b24 = nxt_d_id.b24;
  4875. }
  4876. qla2x00_free_fcport(new_fcport);
  4877. /*
  4878. * Logout all previous fabric dev marked lost, except FCP2 devices.
  4879. */
  4880. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  4881. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  4882. break;
  4883. if ((fcport->flags & FCF_FABRIC_DEVICE) == 0)
  4884. continue;
  4885. if (fcport->scan_state == QLA_FCPORT_SCAN) {
  4886. if ((qla_dual_mode_enabled(vha) ||
  4887. qla_ini_mode_enabled(vha)) &&
  4888. atomic_read(&fcport->state) == FCS_ONLINE) {
  4889. qla2x00_mark_device_lost(vha, fcport,
  4890. ql2xplogiabsentdevice, 0);
  4891. if (fcport->loop_id != FC_NO_LOOP_ID &&
  4892. (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
  4893. fcport->port_type != FCT_INITIATOR &&
  4894. fcport->port_type != FCT_BROADCAST) {
  4895. ql_dbg(ql_dbg_disc, vha, 0x20f0,
  4896. "%s %d %8phC post del sess\n",
  4897. __func__, __LINE__,
  4898. fcport->port_name);
  4899. qlt_schedule_sess_for_deletion(fcport);
  4900. continue;
  4901. }
  4902. }
  4903. }
  4904. if (fcport->scan_state == QLA_FCPORT_FOUND &&
  4905. (fcport->flags & FCF_LOGIN_NEEDED) != 0)
  4906. qla24xx_fcport_handle_login(vha, fcport);
  4907. }
  4908. return (rval);
  4909. }
  4910. /*
  4911. * qla2x00_find_new_loop_id
  4912. * Scan through our port list and find a new usable loop ID.
  4913. *
  4914. * Input:
  4915. * ha: adapter state pointer.
  4916. * dev: port structure pointer.
  4917. *
  4918. * Returns:
  4919. * qla2x00 local function return status code.
  4920. *
  4921. * Context:
  4922. * Kernel context.
  4923. */
  4924. int
  4925. qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
  4926. {
  4927. int rval;
  4928. struct qla_hw_data *ha = vha->hw;
  4929. unsigned long flags = 0;
  4930. rval = QLA_SUCCESS;
  4931. spin_lock_irqsave(&ha->vport_slock, flags);
  4932. dev->loop_id = find_first_zero_bit(ha->loop_id_map,
  4933. LOOPID_MAP_SIZE);
  4934. if (dev->loop_id >= LOOPID_MAP_SIZE ||
  4935. qla2x00_is_reserved_id(vha, dev->loop_id)) {
  4936. dev->loop_id = FC_NO_LOOP_ID;
  4937. rval = QLA_FUNCTION_FAILED;
  4938. } else
  4939. set_bit(dev->loop_id, ha->loop_id_map);
  4940. spin_unlock_irqrestore(&ha->vport_slock, flags);
  4941. if (rval == QLA_SUCCESS)
  4942. ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
  4943. "Assigning new loopid=%x, portid=%x.\n",
  4944. dev->loop_id, dev->d_id.b24);
  4945. else
  4946. ql_log(ql_log_warn, dev->vha, 0x2087,
  4947. "No loop_id's available, portid=%x.\n",
  4948. dev->d_id.b24);
  4949. return (rval);
  4950. }
  4951. /* FW does not set aside Loop id for MGMT Server/FFFFFAh */
  4952. int
  4953. qla2x00_reserve_mgmt_server_loop_id(scsi_qla_host_t *vha)
  4954. {
  4955. int loop_id = FC_NO_LOOP_ID;
  4956. int lid = NPH_MGMT_SERVER - vha->vp_idx;
  4957. unsigned long flags;
  4958. struct qla_hw_data *ha = vha->hw;
  4959. if (vha->vp_idx == 0) {
  4960. set_bit(NPH_MGMT_SERVER, ha->loop_id_map);
  4961. return NPH_MGMT_SERVER;
  4962. }
  4963. /* pick id from high and work down to low */
  4964. spin_lock_irqsave(&ha->vport_slock, flags);
  4965. for (; lid > 0; lid--) {
  4966. if (!test_bit(lid, vha->hw->loop_id_map)) {
  4967. set_bit(lid, vha->hw->loop_id_map);
  4968. loop_id = lid;
  4969. break;
  4970. }
  4971. }
  4972. spin_unlock_irqrestore(&ha->vport_slock, flags);
  4973. return loop_id;
  4974. }
  4975. /*
  4976. * qla2x00_fabric_login
  4977. * Issue fabric login command.
  4978. *
  4979. * Input:
  4980. * ha = adapter block pointer.
  4981. * device = pointer to FC device type structure.
  4982. *
  4983. * Returns:
  4984. * 0 - Login successfully
  4985. * 1 - Login failed
  4986. * 2 - Initiator device
  4987. * 3 - Fatal error
  4988. */
  4989. int
  4990. qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
  4991. uint16_t *next_loopid)
  4992. {
  4993. int rval;
  4994. int retry;
  4995. uint16_t tmp_loopid;
  4996. uint16_t mb[MAILBOX_REGISTER_COUNT];
  4997. struct qla_hw_data *ha = vha->hw;
  4998. retry = 0;
  4999. tmp_loopid = 0;
  5000. for (;;) {
  5001. ql_dbg(ql_dbg_disc, vha, 0x2000,
  5002. "Trying Fabric Login w/loop id 0x%04x for port "
  5003. "%02x%02x%02x.\n",
  5004. fcport->loop_id, fcport->d_id.b.domain,
  5005. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  5006. /* Login fcport on switch. */
  5007. rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
  5008. fcport->d_id.b.domain, fcport->d_id.b.area,
  5009. fcport->d_id.b.al_pa, mb, BIT_0);
  5010. if (rval != QLA_SUCCESS) {
  5011. return rval;
  5012. }
  5013. if (mb[0] == MBS_PORT_ID_USED) {
  5014. /*
  5015. * Device has another loop ID. The firmware team
  5016. * recommends the driver perform an implicit login with
  5017. * the specified ID again. The ID we just used is save
  5018. * here so we return with an ID that can be tried by
  5019. * the next login.
  5020. */
  5021. retry++;
  5022. tmp_loopid = fcport->loop_id;
  5023. fcport->loop_id = mb[1];
  5024. ql_dbg(ql_dbg_disc, vha, 0x2001,
  5025. "Fabric Login: port in use - next loop "
  5026. "id=0x%04x, port id= %02x%02x%02x.\n",
  5027. fcport->loop_id, fcport->d_id.b.domain,
  5028. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  5029. } else if (mb[0] == MBS_COMMAND_COMPLETE) {
  5030. /*
  5031. * Login succeeded.
  5032. */
  5033. if (retry) {
  5034. /* A retry occurred before. */
  5035. *next_loopid = tmp_loopid;
  5036. } else {
  5037. /*
  5038. * No retry occurred before. Just increment the
  5039. * ID value for next login.
  5040. */
  5041. *next_loopid = (fcport->loop_id + 1);
  5042. }
  5043. if (mb[1] & BIT_0) {
  5044. fcport->port_type = FCT_INITIATOR;
  5045. } else {
  5046. fcport->port_type = FCT_TARGET;
  5047. if (mb[1] & BIT_1) {
  5048. fcport->flags |= FCF_FCP2_DEVICE;
  5049. }
  5050. }
  5051. if (mb[10] & BIT_0)
  5052. fcport->supported_classes |= FC_COS_CLASS2;
  5053. if (mb[10] & BIT_1)
  5054. fcport->supported_classes |= FC_COS_CLASS3;
  5055. if (IS_FWI2_CAPABLE(ha)) {
  5056. if (mb[10] & BIT_7)
  5057. fcport->flags |=
  5058. FCF_CONF_COMP_SUPPORTED;
  5059. }
  5060. rval = QLA_SUCCESS;
  5061. break;
  5062. } else if (mb[0] == MBS_LOOP_ID_USED) {
  5063. /*
  5064. * Loop ID already used, try next loop ID.
  5065. */
  5066. fcport->loop_id++;
  5067. rval = qla2x00_find_new_loop_id(vha, fcport);
  5068. if (rval != QLA_SUCCESS) {
  5069. /* Ran out of loop IDs to use */
  5070. break;
  5071. }
  5072. } else if (mb[0] == MBS_COMMAND_ERROR) {
  5073. /*
  5074. * Firmware possibly timed out during login. If NO
  5075. * retries are left to do then the device is declared
  5076. * dead.
  5077. */
  5078. *next_loopid = fcport->loop_id;
  5079. ha->isp_ops->fabric_logout(vha, fcport->loop_id,
  5080. fcport->d_id.b.domain, fcport->d_id.b.area,
  5081. fcport->d_id.b.al_pa);
  5082. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  5083. rval = 1;
  5084. break;
  5085. } else {
  5086. /*
  5087. * unrecoverable / not handled error
  5088. */
  5089. ql_dbg(ql_dbg_disc, vha, 0x2002,
  5090. "Failed=%x port_id=%02x%02x%02x loop_id=%x "
  5091. "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
  5092. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  5093. fcport->loop_id, jiffies);
  5094. *next_loopid = fcport->loop_id;
  5095. ha->isp_ops->fabric_logout(vha, fcport->loop_id,
  5096. fcport->d_id.b.domain, fcport->d_id.b.area,
  5097. fcport->d_id.b.al_pa);
  5098. qla2x00_clear_loop_id(fcport);
  5099. fcport->login_retry = 0;
  5100. rval = 3;
  5101. break;
  5102. }
  5103. }
  5104. return (rval);
  5105. }
  5106. /*
  5107. * qla2x00_local_device_login
  5108. * Issue local device login command.
  5109. *
  5110. * Input:
  5111. * ha = adapter block pointer.
  5112. * loop_id = loop id of device to login to.
  5113. *
  5114. * Returns (Where's the #define!!!!):
  5115. * 0 - Login successfully
  5116. * 1 - Login failed
  5117. * 3 - Fatal error
  5118. */
  5119. int
  5120. qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
  5121. {
  5122. int rval;
  5123. uint16_t mb[MAILBOX_REGISTER_COUNT];
  5124. memset(mb, 0, sizeof(mb));
  5125. rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
  5126. if (rval == QLA_SUCCESS) {
  5127. /* Interrogate mailbox registers for any errors */
  5128. if (mb[0] == MBS_COMMAND_ERROR)
  5129. rval = 1;
  5130. else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
  5131. /* device not in PCB table */
  5132. rval = 3;
  5133. }
  5134. return (rval);
  5135. }
  5136. /*
  5137. * qla2x00_loop_resync
  5138. * Resync with fibre channel devices.
  5139. *
  5140. * Input:
  5141. * ha = adapter block pointer.
  5142. *
  5143. * Returns:
  5144. * 0 = success
  5145. */
  5146. int
  5147. qla2x00_loop_resync(scsi_qla_host_t *vha)
  5148. {
  5149. int rval = QLA_SUCCESS;
  5150. uint32_t wait_time;
  5151. struct req_que *req;
  5152. struct rsp_que *rsp;
  5153. req = vha->req;
  5154. rsp = req->rsp;
  5155. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  5156. if (vha->flags.online) {
  5157. if (!(rval = qla2x00_fw_ready(vha))) {
  5158. /* Wait at most MAX_TARGET RSCNs for a stable link. */
  5159. wait_time = 256;
  5160. do {
  5161. if (!IS_QLAFX00(vha->hw)) {
  5162. /*
  5163. * Issue a marker after FW becomes
  5164. * ready.
  5165. */
  5166. qla2x00_marker(vha, req, rsp, 0, 0,
  5167. MK_SYNC_ALL);
  5168. vha->marker_needed = 0;
  5169. }
  5170. /* Remap devices on Loop. */
  5171. clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  5172. if (IS_QLAFX00(vha->hw))
  5173. qlafx00_configure_devices(vha);
  5174. else
  5175. qla2x00_configure_loop(vha);
  5176. wait_time--;
  5177. } while (!atomic_read(&vha->loop_down_timer) &&
  5178. !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
  5179. && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
  5180. &vha->dpc_flags)));
  5181. }
  5182. }
  5183. if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
  5184. return (QLA_FUNCTION_FAILED);
  5185. if (rval)
  5186. ql_dbg(ql_dbg_disc, vha, 0x206c,
  5187. "%s *** FAILED ***.\n", __func__);
  5188. return (rval);
  5189. }
  5190. /*
  5191. * qla2x00_perform_loop_resync
  5192. * Description: This function will set the appropriate flags and call
  5193. * qla2x00_loop_resync. If successful loop will be resynced
  5194. * Arguments : scsi_qla_host_t pointer
  5195. * returm : Success or Failure
  5196. */
  5197. int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
  5198. {
  5199. int32_t rval = 0;
  5200. if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
  5201. /*Configure the flags so that resync happens properly*/
  5202. atomic_set(&ha->loop_down_timer, 0);
  5203. if (!(ha->device_flags & DFLG_NO_CABLE)) {
  5204. atomic_set(&ha->loop_state, LOOP_UP);
  5205. set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
  5206. set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
  5207. set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
  5208. rval = qla2x00_loop_resync(ha);
  5209. } else
  5210. atomic_set(&ha->loop_state, LOOP_DEAD);
  5211. clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
  5212. }
  5213. return rval;
  5214. }
  5215. void
  5216. qla2x00_update_fcports(scsi_qla_host_t *base_vha)
  5217. {
  5218. fc_port_t *fcport;
  5219. struct scsi_qla_host *vha;
  5220. struct qla_hw_data *ha = base_vha->hw;
  5221. unsigned long flags;
  5222. spin_lock_irqsave(&ha->vport_slock, flags);
  5223. /* Go with deferred removal of rport references. */
  5224. list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
  5225. atomic_inc(&vha->vref_count);
  5226. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  5227. if (fcport->drport &&
  5228. atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
  5229. spin_unlock_irqrestore(&ha->vport_slock, flags);
  5230. qla2x00_rport_del(fcport);
  5231. spin_lock_irqsave(&ha->vport_slock, flags);
  5232. }
  5233. }
  5234. atomic_dec(&vha->vref_count);
  5235. wake_up(&vha->vref_waitq);
  5236. }
  5237. spin_unlock_irqrestore(&ha->vport_slock, flags);
  5238. }
  5239. /* Assumes idc_lock always held on entry */
  5240. void
  5241. qla83xx_reset_ownership(scsi_qla_host_t *vha)
  5242. {
  5243. struct qla_hw_data *ha = vha->hw;
  5244. uint32_t drv_presence, drv_presence_mask;
  5245. uint32_t dev_part_info1, dev_part_info2, class_type;
  5246. uint32_t class_type_mask = 0x3;
  5247. uint16_t fcoe_other_function = 0xffff, i;
  5248. if (IS_QLA8044(ha)) {
  5249. drv_presence = qla8044_rd_direct(vha,
  5250. QLA8044_CRB_DRV_ACTIVE_INDEX);
  5251. dev_part_info1 = qla8044_rd_direct(vha,
  5252. QLA8044_CRB_DEV_PART_INFO_INDEX);
  5253. dev_part_info2 = qla8044_rd_direct(vha,
  5254. QLA8044_CRB_DEV_PART_INFO2);
  5255. } else {
  5256. qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
  5257. qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1);
  5258. qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2);
  5259. }
  5260. for (i = 0; i < 8; i++) {
  5261. class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask);
  5262. if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
  5263. (i != ha->portnum)) {
  5264. fcoe_other_function = i;
  5265. break;
  5266. }
  5267. }
  5268. if (fcoe_other_function == 0xffff) {
  5269. for (i = 0; i < 8; i++) {
  5270. class_type = ((dev_part_info2 >> (i * 4)) &
  5271. class_type_mask);
  5272. if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
  5273. ((i + 8) != ha->portnum)) {
  5274. fcoe_other_function = i + 8;
  5275. break;
  5276. }
  5277. }
  5278. }
  5279. /*
  5280. * Prepare drv-presence mask based on fcoe functions present.
  5281. * However consider only valid physical fcoe function numbers (0-15).
  5282. */
  5283. drv_presence_mask = ~((1 << (ha->portnum)) |
  5284. ((fcoe_other_function == 0xffff) ?
  5285. 0 : (1 << (fcoe_other_function))));
  5286. /* We are the reset owner iff:
  5287. * - No other protocol drivers present.
  5288. * - This is the lowest among fcoe functions. */
  5289. if (!(drv_presence & drv_presence_mask) &&
  5290. (ha->portnum < fcoe_other_function)) {
  5291. ql_dbg(ql_dbg_p3p, vha, 0xb07f,
  5292. "This host is Reset owner.\n");
  5293. ha->flags.nic_core_reset_owner = 1;
  5294. }
  5295. }
  5296. static int
  5297. __qla83xx_set_drv_ack(scsi_qla_host_t *vha)
  5298. {
  5299. int rval = QLA_SUCCESS;
  5300. struct qla_hw_data *ha = vha->hw;
  5301. uint32_t drv_ack;
  5302. rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
  5303. if (rval == QLA_SUCCESS) {
  5304. drv_ack |= (1 << ha->portnum);
  5305. rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
  5306. }
  5307. return rval;
  5308. }
  5309. static int
  5310. __qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
  5311. {
  5312. int rval = QLA_SUCCESS;
  5313. struct qla_hw_data *ha = vha->hw;
  5314. uint32_t drv_ack;
  5315. rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
  5316. if (rval == QLA_SUCCESS) {
  5317. drv_ack &= ~(1 << ha->portnum);
  5318. rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
  5319. }
  5320. return rval;
  5321. }
  5322. static const char *
  5323. qla83xx_dev_state_to_string(uint32_t dev_state)
  5324. {
  5325. switch (dev_state) {
  5326. case QLA8XXX_DEV_COLD:
  5327. return "COLD/RE-INIT";
  5328. case QLA8XXX_DEV_INITIALIZING:
  5329. return "INITIALIZING";
  5330. case QLA8XXX_DEV_READY:
  5331. return "READY";
  5332. case QLA8XXX_DEV_NEED_RESET:
  5333. return "NEED RESET";
  5334. case QLA8XXX_DEV_NEED_QUIESCENT:
  5335. return "NEED QUIESCENT";
  5336. case QLA8XXX_DEV_FAILED:
  5337. return "FAILED";
  5338. case QLA8XXX_DEV_QUIESCENT:
  5339. return "QUIESCENT";
  5340. default:
  5341. return "Unknown";
  5342. }
  5343. }
  5344. /* Assumes idc-lock always held on entry */
  5345. void
  5346. qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type)
  5347. {
  5348. struct qla_hw_data *ha = vha->hw;
  5349. uint32_t idc_audit_reg = 0, duration_secs = 0;
  5350. switch (audit_type) {
  5351. case IDC_AUDIT_TIMESTAMP:
  5352. ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000);
  5353. idc_audit_reg = (ha->portnum) |
  5354. (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8);
  5355. qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
  5356. break;
  5357. case IDC_AUDIT_COMPLETION:
  5358. duration_secs = ((jiffies_to_msecs(jiffies) -
  5359. jiffies_to_msecs(ha->idc_audit_ts)) / 1000);
  5360. idc_audit_reg = (ha->portnum) |
  5361. (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8);
  5362. qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
  5363. break;
  5364. default:
  5365. ql_log(ql_log_warn, vha, 0xb078,
  5366. "Invalid audit type specified.\n");
  5367. break;
  5368. }
  5369. }
  5370. /* Assumes idc_lock always held on entry */
  5371. static int
  5372. qla83xx_initiating_reset(scsi_qla_host_t *vha)
  5373. {
  5374. struct qla_hw_data *ha = vha->hw;
  5375. uint32_t idc_control, dev_state;
  5376. __qla83xx_get_idc_control(vha, &idc_control);
  5377. if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) {
  5378. ql_log(ql_log_info, vha, 0xb080,
  5379. "NIC Core reset has been disabled. idc-control=0x%x\n",
  5380. idc_control);
  5381. return QLA_FUNCTION_FAILED;
  5382. }
  5383. /* Set NEED-RESET iff in READY state and we are the reset-owner */
  5384. qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
  5385. if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) {
  5386. qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
  5387. QLA8XXX_DEV_NEED_RESET);
  5388. ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n");
  5389. qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP);
  5390. } else {
  5391. const char *state = qla83xx_dev_state_to_string(dev_state);
  5392. ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state);
  5393. /* SV: XXX: Is timeout required here? */
  5394. /* Wait for IDC state change READY -> NEED_RESET */
  5395. while (dev_state == QLA8XXX_DEV_READY) {
  5396. qla83xx_idc_unlock(vha, 0);
  5397. msleep(200);
  5398. qla83xx_idc_lock(vha, 0);
  5399. qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
  5400. }
  5401. }
  5402. /* Send IDC ack by writing to drv-ack register */
  5403. __qla83xx_set_drv_ack(vha);
  5404. return QLA_SUCCESS;
  5405. }
  5406. int
  5407. __qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
  5408. {
  5409. return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
  5410. }
  5411. int
  5412. __qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
  5413. {
  5414. return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
  5415. }
  5416. static int
  5417. qla83xx_check_driver_presence(scsi_qla_host_t *vha)
  5418. {
  5419. uint32_t drv_presence = 0;
  5420. struct qla_hw_data *ha = vha->hw;
  5421. qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
  5422. if (drv_presence & (1 << ha->portnum))
  5423. return QLA_SUCCESS;
  5424. else
  5425. return QLA_TEST_FAILED;
  5426. }
  5427. int
  5428. qla83xx_nic_core_reset(scsi_qla_host_t *vha)
  5429. {
  5430. int rval = QLA_SUCCESS;
  5431. struct qla_hw_data *ha = vha->hw;
  5432. ql_dbg(ql_dbg_p3p, vha, 0xb058,
  5433. "Entered %s().\n", __func__);
  5434. if (vha->device_flags & DFLG_DEV_FAILED) {
  5435. ql_log(ql_log_warn, vha, 0xb059,
  5436. "Device in unrecoverable FAILED state.\n");
  5437. return QLA_FUNCTION_FAILED;
  5438. }
  5439. qla83xx_idc_lock(vha, 0);
  5440. if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) {
  5441. ql_log(ql_log_warn, vha, 0xb05a,
  5442. "Function=0x%x has been removed from IDC participation.\n",
  5443. ha->portnum);
  5444. rval = QLA_FUNCTION_FAILED;
  5445. goto exit;
  5446. }
  5447. qla83xx_reset_ownership(vha);
  5448. rval = qla83xx_initiating_reset(vha);
  5449. /*
  5450. * Perform reset if we are the reset-owner,
  5451. * else wait till IDC state changes to READY/FAILED.
  5452. */
  5453. if (rval == QLA_SUCCESS) {
  5454. rval = qla83xx_idc_state_handler(vha);
  5455. if (rval == QLA_SUCCESS)
  5456. ha->flags.nic_core_hung = 0;
  5457. __qla83xx_clear_drv_ack(vha);
  5458. }
  5459. exit:
  5460. qla83xx_idc_unlock(vha, 0);
  5461. ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__);
  5462. return rval;
  5463. }
  5464. int
  5465. qla2xxx_mctp_dump(scsi_qla_host_t *vha)
  5466. {
  5467. struct qla_hw_data *ha = vha->hw;
  5468. int rval = QLA_FUNCTION_FAILED;
  5469. if (!IS_MCTP_CAPABLE(ha)) {
  5470. /* This message can be removed from the final version */
  5471. ql_log(ql_log_info, vha, 0x506d,
  5472. "This board is not MCTP capable\n");
  5473. return rval;
  5474. }
  5475. if (!ha->mctp_dump) {
  5476. ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev,
  5477. MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL);
  5478. if (!ha->mctp_dump) {
  5479. ql_log(ql_log_warn, vha, 0x506e,
  5480. "Failed to allocate memory for mctp dump\n");
  5481. return rval;
  5482. }
  5483. }
  5484. #define MCTP_DUMP_STR_ADDR 0x00000000
  5485. rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma,
  5486. MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4);
  5487. if (rval != QLA_SUCCESS) {
  5488. ql_log(ql_log_warn, vha, 0x506f,
  5489. "Failed to capture mctp dump\n");
  5490. } else {
  5491. ql_log(ql_log_info, vha, 0x5070,
  5492. "Mctp dump capture for host (%ld/%p).\n",
  5493. vha->host_no, ha->mctp_dump);
  5494. ha->mctp_dumped = 1;
  5495. }
  5496. if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) {
  5497. ha->flags.nic_core_reset_hdlr_active = 1;
  5498. rval = qla83xx_restart_nic_firmware(vha);
  5499. if (rval)
  5500. /* NIC Core reset failed. */
  5501. ql_log(ql_log_warn, vha, 0x5071,
  5502. "Failed to restart nic firmware\n");
  5503. else
  5504. ql_dbg(ql_dbg_p3p, vha, 0xb084,
  5505. "Restarted NIC firmware successfully.\n");
  5506. ha->flags.nic_core_reset_hdlr_active = 0;
  5507. }
  5508. return rval;
  5509. }
  5510. /*
  5511. * qla2x00_quiesce_io
  5512. * Description: This function will block the new I/Os
  5513. * Its not aborting any I/Os as context
  5514. * is not destroyed during quiescence
  5515. * Arguments: scsi_qla_host_t
  5516. * return : void
  5517. */
  5518. void
  5519. qla2x00_quiesce_io(scsi_qla_host_t *vha)
  5520. {
  5521. struct qla_hw_data *ha = vha->hw;
  5522. struct scsi_qla_host *vp;
  5523. ql_dbg(ql_dbg_dpc, vha, 0x401d,
  5524. "Quiescing I/O - ha=%p.\n", ha);
  5525. atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
  5526. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  5527. atomic_set(&vha->loop_state, LOOP_DOWN);
  5528. qla2x00_mark_all_devices_lost(vha, 0);
  5529. list_for_each_entry(vp, &ha->vp_list, list)
  5530. qla2x00_mark_all_devices_lost(vp, 0);
  5531. } else {
  5532. if (!atomic_read(&vha->loop_down_timer))
  5533. atomic_set(&vha->loop_down_timer,
  5534. LOOP_DOWN_TIME);
  5535. }
  5536. /* Wait for pending cmds to complete */
  5537. qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
  5538. }
  5539. void
  5540. qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
  5541. {
  5542. struct qla_hw_data *ha = vha->hw;
  5543. struct scsi_qla_host *vp;
  5544. unsigned long flags;
  5545. fc_port_t *fcport;
  5546. u16 i;
  5547. /* For ISP82XX, driver waits for completion of the commands.
  5548. * online flag should be set.
  5549. */
  5550. if (!(IS_P3P_TYPE(ha)))
  5551. vha->flags.online = 0;
  5552. ha->flags.chip_reset_done = 0;
  5553. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  5554. vha->qla_stats.total_isp_aborts++;
  5555. ql_log(ql_log_info, vha, 0x00af,
  5556. "Performing ISP error recovery - ha=%p.\n", ha);
  5557. ha->flags.purge_mbox = 1;
  5558. /* For ISP82XX, reset_chip is just disabling interrupts.
  5559. * Driver waits for the completion of the commands.
  5560. * the interrupts need to be enabled.
  5561. */
  5562. if (!(IS_P3P_TYPE(ha)))
  5563. ha->isp_ops->reset_chip(vha);
  5564. ha->link_data_rate = PORT_SPEED_UNKNOWN;
  5565. SAVE_TOPO(ha);
  5566. ha->flags.rida_fmt2 = 0;
  5567. ha->flags.n2n_ae = 0;
  5568. ha->flags.lip_ae = 0;
  5569. ha->current_topology = 0;
  5570. ha->flags.fw_started = 0;
  5571. ha->flags.fw_init_done = 0;
  5572. ha->chip_reset++;
  5573. ha->base_qpair->chip_reset = ha->chip_reset;
  5574. for (i = 0; i < ha->max_qpairs; i++) {
  5575. if (ha->queue_pair_map[i])
  5576. ha->queue_pair_map[i]->chip_reset =
  5577. ha->base_qpair->chip_reset;
  5578. }
  5579. /* purge MBox commands */
  5580. if (atomic_read(&ha->num_pend_mbx_stage3)) {
  5581. clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
  5582. complete(&ha->mbx_intr_comp);
  5583. }
  5584. i = 0;
  5585. while (atomic_read(&ha->num_pend_mbx_stage3) ||
  5586. atomic_read(&ha->num_pend_mbx_stage2) ||
  5587. atomic_read(&ha->num_pend_mbx_stage1)) {
  5588. msleep(20);
  5589. i++;
  5590. if (i > 50)
  5591. break;
  5592. }
  5593. ha->flags.purge_mbox = 0;
  5594. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  5595. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  5596. atomic_set(&vha->loop_state, LOOP_DOWN);
  5597. qla2x00_mark_all_devices_lost(vha, 0);
  5598. spin_lock_irqsave(&ha->vport_slock, flags);
  5599. list_for_each_entry(vp, &ha->vp_list, list) {
  5600. atomic_inc(&vp->vref_count);
  5601. spin_unlock_irqrestore(&ha->vport_slock, flags);
  5602. qla2x00_mark_all_devices_lost(vp, 0);
  5603. spin_lock_irqsave(&ha->vport_slock, flags);
  5604. atomic_dec(&vp->vref_count);
  5605. }
  5606. spin_unlock_irqrestore(&ha->vport_slock, flags);
  5607. } else {
  5608. if (!atomic_read(&vha->loop_down_timer))
  5609. atomic_set(&vha->loop_down_timer,
  5610. LOOP_DOWN_TIME);
  5611. }
  5612. /* Clear all async request states across all VPs. */
  5613. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  5614. fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
  5615. fcport->scan_state = 0;
  5616. }
  5617. spin_lock_irqsave(&ha->vport_slock, flags);
  5618. list_for_each_entry(vp, &ha->vp_list, list) {
  5619. atomic_inc(&vp->vref_count);
  5620. spin_unlock_irqrestore(&ha->vport_slock, flags);
  5621. list_for_each_entry(fcport, &vp->vp_fcports, list)
  5622. fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
  5623. spin_lock_irqsave(&ha->vport_slock, flags);
  5624. atomic_dec(&vp->vref_count);
  5625. }
  5626. spin_unlock_irqrestore(&ha->vport_slock, flags);
  5627. if (!ha->flags.eeh_busy) {
  5628. /* Make sure for ISP 82XX IO DMA is complete */
  5629. if (IS_P3P_TYPE(ha)) {
  5630. qla82xx_chip_reset_cleanup(vha);
  5631. ql_log(ql_log_info, vha, 0x00b4,
  5632. "Done chip reset cleanup.\n");
  5633. /* Done waiting for pending commands.
  5634. * Reset the online flag.
  5635. */
  5636. vha->flags.online = 0;
  5637. }
  5638. /* Requeue all commands in outstanding command list. */
  5639. qla2x00_abort_all_cmds(vha, DID_RESET << 16);
  5640. }
  5641. /* memory barrier */
  5642. wmb();
  5643. }
  5644. /*
  5645. * qla2x00_abort_isp
  5646. * Resets ISP and aborts all outstanding commands.
  5647. *
  5648. * Input:
  5649. * ha = adapter block pointer.
  5650. *
  5651. * Returns:
  5652. * 0 = success
  5653. */
  5654. int
  5655. qla2x00_abort_isp(scsi_qla_host_t *vha)
  5656. {
  5657. int rval;
  5658. uint8_t status = 0;
  5659. struct qla_hw_data *ha = vha->hw;
  5660. struct scsi_qla_host *vp;
  5661. struct req_que *req = ha->req_q_map[0];
  5662. unsigned long flags;
  5663. if (vha->flags.online) {
  5664. qla2x00_abort_isp_cleanup(vha);
  5665. if (IS_QLA8031(ha)) {
  5666. ql_dbg(ql_dbg_p3p, vha, 0xb05c,
  5667. "Clearing fcoe driver presence.\n");
  5668. if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS)
  5669. ql_dbg(ql_dbg_p3p, vha, 0xb073,
  5670. "Error while clearing DRV-Presence.\n");
  5671. }
  5672. if (unlikely(pci_channel_offline(ha->pdev) &&
  5673. ha->flags.pci_channel_io_perm_failure)) {
  5674. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  5675. status = 0;
  5676. return status;
  5677. }
  5678. ha->isp_ops->get_flash_version(vha, req->ring);
  5679. ha->isp_ops->nvram_config(vha);
  5680. if (!qla2x00_restart_isp(vha)) {
  5681. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  5682. if (!atomic_read(&vha->loop_down_timer)) {
  5683. /*
  5684. * Issue marker command only when we are going
  5685. * to start the I/O .
  5686. */
  5687. vha->marker_needed = 1;
  5688. }
  5689. vha->flags.online = 1;
  5690. ha->isp_ops->enable_intrs(ha);
  5691. ha->isp_abort_cnt = 0;
  5692. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  5693. if (IS_QLA81XX(ha) || IS_QLA8031(ha))
  5694. qla2x00_get_fw_version(vha);
  5695. if (ha->fce) {
  5696. ha->flags.fce_enabled = 1;
  5697. memset(ha->fce, 0,
  5698. fce_calc_size(ha->fce_bufs));
  5699. rval = qla2x00_enable_fce_trace(vha,
  5700. ha->fce_dma, ha->fce_bufs, ha->fce_mb,
  5701. &ha->fce_bufs);
  5702. if (rval) {
  5703. ql_log(ql_log_warn, vha, 0x8033,
  5704. "Unable to reinitialize FCE "
  5705. "(%d).\n", rval);
  5706. ha->flags.fce_enabled = 0;
  5707. }
  5708. }
  5709. if (ha->eft) {
  5710. memset(ha->eft, 0, EFT_SIZE);
  5711. rval = qla2x00_enable_eft_trace(vha,
  5712. ha->eft_dma, EFT_NUM_BUFFERS);
  5713. if (rval) {
  5714. ql_log(ql_log_warn, vha, 0x8034,
  5715. "Unable to reinitialize EFT "
  5716. "(%d).\n", rval);
  5717. }
  5718. }
  5719. } else { /* failed the ISP abort */
  5720. vha->flags.online = 1;
  5721. if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  5722. if (ha->isp_abort_cnt == 0) {
  5723. ql_log(ql_log_fatal, vha, 0x8035,
  5724. "ISP error recover failed - "
  5725. "board disabled.\n");
  5726. /*
  5727. * The next call disables the board
  5728. * completely.
  5729. */
  5730. qla2x00_abort_isp_cleanup(vha);
  5731. vha->flags.online = 0;
  5732. clear_bit(ISP_ABORT_RETRY,
  5733. &vha->dpc_flags);
  5734. status = 0;
  5735. } else { /* schedule another ISP abort */
  5736. ha->isp_abort_cnt--;
  5737. ql_dbg(ql_dbg_taskm, vha, 0x8020,
  5738. "ISP abort - retry remaining %d.\n",
  5739. ha->isp_abort_cnt);
  5740. status = 1;
  5741. }
  5742. } else {
  5743. ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
  5744. ql_dbg(ql_dbg_taskm, vha, 0x8021,
  5745. "ISP error recovery - retrying (%d) "
  5746. "more times.\n", ha->isp_abort_cnt);
  5747. set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  5748. status = 1;
  5749. }
  5750. }
  5751. }
  5752. if (!status) {
  5753. ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
  5754. qla2x00_configure_hba(vha);
  5755. spin_lock_irqsave(&ha->vport_slock, flags);
  5756. list_for_each_entry(vp, &ha->vp_list, list) {
  5757. if (vp->vp_idx) {
  5758. atomic_inc(&vp->vref_count);
  5759. spin_unlock_irqrestore(&ha->vport_slock, flags);
  5760. qla2x00_vp_abort_isp(vp);
  5761. spin_lock_irqsave(&ha->vport_slock, flags);
  5762. atomic_dec(&vp->vref_count);
  5763. }
  5764. }
  5765. spin_unlock_irqrestore(&ha->vport_slock, flags);
  5766. if (IS_QLA8031(ha)) {
  5767. ql_dbg(ql_dbg_p3p, vha, 0xb05d,
  5768. "Setting back fcoe driver presence.\n");
  5769. if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS)
  5770. ql_dbg(ql_dbg_p3p, vha, 0xb074,
  5771. "Error while setting DRV-Presence.\n");
  5772. }
  5773. } else {
  5774. ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
  5775. __func__);
  5776. }
  5777. return(status);
  5778. }
  5779. /*
  5780. * qla2x00_restart_isp
  5781. * restarts the ISP after a reset
  5782. *
  5783. * Input:
  5784. * ha = adapter block pointer.
  5785. *
  5786. * Returns:
  5787. * 0 = success
  5788. */
  5789. static int
  5790. qla2x00_restart_isp(scsi_qla_host_t *vha)
  5791. {
  5792. int status = 0;
  5793. struct qla_hw_data *ha = vha->hw;
  5794. struct req_que *req = ha->req_q_map[0];
  5795. struct rsp_que *rsp = ha->rsp_q_map[0];
  5796. /* If firmware needs to be loaded */
  5797. if (qla2x00_isp_firmware(vha)) {
  5798. vha->flags.online = 0;
  5799. status = ha->isp_ops->chip_diag(vha);
  5800. if (!status)
  5801. status = qla2x00_setup_chip(vha);
  5802. }
  5803. if (!status && !(status = qla2x00_init_rings(vha))) {
  5804. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  5805. ha->flags.chip_reset_done = 1;
  5806. /* Initialize the queues in use */
  5807. qla25xx_init_queues(ha);
  5808. status = qla2x00_fw_ready(vha);
  5809. if (!status) {
  5810. /* Issue a marker after FW becomes ready. */
  5811. qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
  5812. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  5813. }
  5814. /* if no cable then assume it's good */
  5815. if ((vha->device_flags & DFLG_NO_CABLE))
  5816. status = 0;
  5817. }
  5818. return (status);
  5819. }
  5820. static int
  5821. qla25xx_init_queues(struct qla_hw_data *ha)
  5822. {
  5823. struct rsp_que *rsp = NULL;
  5824. struct req_que *req = NULL;
  5825. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  5826. int ret = -1;
  5827. int i;
  5828. for (i = 1; i < ha->max_rsp_queues; i++) {
  5829. rsp = ha->rsp_q_map[i];
  5830. if (rsp && test_bit(i, ha->rsp_qid_map)) {
  5831. rsp->options &= ~BIT_0;
  5832. ret = qla25xx_init_rsp_que(base_vha, rsp);
  5833. if (ret != QLA_SUCCESS)
  5834. ql_dbg(ql_dbg_init, base_vha, 0x00ff,
  5835. "%s Rsp que: %d init failed.\n",
  5836. __func__, rsp->id);
  5837. else
  5838. ql_dbg(ql_dbg_init, base_vha, 0x0100,
  5839. "%s Rsp que: %d inited.\n",
  5840. __func__, rsp->id);
  5841. }
  5842. }
  5843. for (i = 1; i < ha->max_req_queues; i++) {
  5844. req = ha->req_q_map[i];
  5845. if (req && test_bit(i, ha->req_qid_map)) {
  5846. /* Clear outstanding commands array. */
  5847. req->options &= ~BIT_0;
  5848. ret = qla25xx_init_req_que(base_vha, req);
  5849. if (ret != QLA_SUCCESS)
  5850. ql_dbg(ql_dbg_init, base_vha, 0x0101,
  5851. "%s Req que: %d init failed.\n",
  5852. __func__, req->id);
  5853. else
  5854. ql_dbg(ql_dbg_init, base_vha, 0x0102,
  5855. "%s Req que: %d inited.\n",
  5856. __func__, req->id);
  5857. }
  5858. }
  5859. return ret;
  5860. }
  5861. /*
  5862. * qla2x00_reset_adapter
  5863. * Reset adapter.
  5864. *
  5865. * Input:
  5866. * ha = adapter block pointer.
  5867. */
  5868. void
  5869. qla2x00_reset_adapter(scsi_qla_host_t *vha)
  5870. {
  5871. unsigned long flags = 0;
  5872. struct qla_hw_data *ha = vha->hw;
  5873. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  5874. vha->flags.online = 0;
  5875. ha->isp_ops->disable_intrs(ha);
  5876. spin_lock_irqsave(&ha->hardware_lock, flags);
  5877. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  5878. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  5879. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  5880. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  5881. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  5882. }
  5883. void
  5884. qla24xx_reset_adapter(scsi_qla_host_t *vha)
  5885. {
  5886. unsigned long flags = 0;
  5887. struct qla_hw_data *ha = vha->hw;
  5888. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  5889. if (IS_P3P_TYPE(ha))
  5890. return;
  5891. vha->flags.online = 0;
  5892. ha->isp_ops->disable_intrs(ha);
  5893. spin_lock_irqsave(&ha->hardware_lock, flags);
  5894. WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
  5895. RD_REG_DWORD(&reg->hccr);
  5896. WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
  5897. RD_REG_DWORD(&reg->hccr);
  5898. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  5899. if (IS_NOPOLLING_TYPE(ha))
  5900. ha->isp_ops->enable_intrs(ha);
  5901. }
  5902. /* On sparc systems, obtain port and node WWN from firmware
  5903. * properties.
  5904. */
  5905. static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
  5906. struct nvram_24xx *nv)
  5907. {
  5908. #ifdef CONFIG_SPARC
  5909. struct qla_hw_data *ha = vha->hw;
  5910. struct pci_dev *pdev = ha->pdev;
  5911. struct device_node *dp = pci_device_to_OF_node(pdev);
  5912. const u8 *val;
  5913. int len;
  5914. val = of_get_property(dp, "port-wwn", &len);
  5915. if (val && len >= WWN_SIZE)
  5916. memcpy(nv->port_name, val, WWN_SIZE);
  5917. val = of_get_property(dp, "node-wwn", &len);
  5918. if (val && len >= WWN_SIZE)
  5919. memcpy(nv->node_name, val, WWN_SIZE);
  5920. #endif
  5921. }
  5922. int
  5923. qla24xx_nvram_config(scsi_qla_host_t *vha)
  5924. {
  5925. int rval;
  5926. struct init_cb_24xx *icb;
  5927. struct nvram_24xx *nv;
  5928. uint32_t *dptr;
  5929. uint8_t *dptr1, *dptr2;
  5930. uint32_t chksum;
  5931. uint16_t cnt;
  5932. struct qla_hw_data *ha = vha->hw;
  5933. rval = QLA_SUCCESS;
  5934. icb = (struct init_cb_24xx *)ha->init_cb;
  5935. nv = ha->nvram;
  5936. /* Determine NVRAM starting address. */
  5937. if (ha->port_no == 0) {
  5938. ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
  5939. ha->vpd_base = FA_NVRAM_VPD0_ADDR;
  5940. } else {
  5941. ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
  5942. ha->vpd_base = FA_NVRAM_VPD1_ADDR;
  5943. }
  5944. ha->nvram_size = sizeof(struct nvram_24xx);
  5945. ha->vpd_size = FA_NVRAM_VPD_SIZE;
  5946. /* Get VPD data into cache */
  5947. ha->vpd = ha->nvram + VPD_OFFSET;
  5948. ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
  5949. ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
  5950. /* Get NVRAM data into cache and calculate checksum. */
  5951. dptr = (uint32_t *)nv;
  5952. ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
  5953. ha->nvram_size);
  5954. for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++)
  5955. chksum += le32_to_cpu(*dptr);
  5956. ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
  5957. "Contents of NVRAM\n");
  5958. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
  5959. (uint8_t *)nv, ha->nvram_size);
  5960. /* Bad NVRAM data, set defaults parameters. */
  5961. if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
  5962. || nv->id[3] != ' ' ||
  5963. nv->nvram_version < cpu_to_le16(ICB_VERSION)) {
  5964. /* Reset NVRAM data. */
  5965. ql_log(ql_log_warn, vha, 0x006b,
  5966. "Inconsistent NVRAM detected: checksum=0x%x id=%c "
  5967. "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
  5968. ql_log(ql_log_warn, vha, 0x006c,
  5969. "Falling back to functioning (yet invalid -- WWPN) "
  5970. "defaults.\n");
  5971. /*
  5972. * Set default initialization control block.
  5973. */
  5974. memset(nv, 0, ha->nvram_size);
  5975. nv->nvram_version = cpu_to_le16(ICB_VERSION);
  5976. nv->version = cpu_to_le16(ICB_VERSION);
  5977. nv->frame_payload_size = 2048;
  5978. nv->execution_throttle = cpu_to_le16(0xFFFF);
  5979. nv->exchange_count = cpu_to_le16(0);
  5980. nv->hard_address = cpu_to_le16(124);
  5981. nv->port_name[0] = 0x21;
  5982. nv->port_name[1] = 0x00 + ha->port_no + 1;
  5983. nv->port_name[2] = 0x00;
  5984. nv->port_name[3] = 0xe0;
  5985. nv->port_name[4] = 0x8b;
  5986. nv->port_name[5] = 0x1c;
  5987. nv->port_name[6] = 0x55;
  5988. nv->port_name[7] = 0x86;
  5989. nv->node_name[0] = 0x20;
  5990. nv->node_name[1] = 0x00;
  5991. nv->node_name[2] = 0x00;
  5992. nv->node_name[3] = 0xe0;
  5993. nv->node_name[4] = 0x8b;
  5994. nv->node_name[5] = 0x1c;
  5995. nv->node_name[6] = 0x55;
  5996. nv->node_name[7] = 0x86;
  5997. qla24xx_nvram_wwn_from_ofw(vha, nv);
  5998. nv->login_retry_count = cpu_to_le16(8);
  5999. nv->interrupt_delay_timer = cpu_to_le16(0);
  6000. nv->login_timeout = cpu_to_le16(0);
  6001. nv->firmware_options_1 =
  6002. cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
  6003. nv->firmware_options_2 = cpu_to_le32(2 << 4);
  6004. nv->firmware_options_2 |= cpu_to_le32(BIT_12);
  6005. nv->firmware_options_3 = cpu_to_le32(2 << 13);
  6006. nv->host_p = cpu_to_le32(BIT_11|BIT_10);
  6007. nv->efi_parameters = cpu_to_le32(0);
  6008. nv->reset_delay = 5;
  6009. nv->max_luns_per_target = cpu_to_le16(128);
  6010. nv->port_down_retry_count = cpu_to_le16(30);
  6011. nv->link_down_timeout = cpu_to_le16(30);
  6012. rval = 1;
  6013. }
  6014. if (qla_tgt_mode_enabled(vha)) {
  6015. /* Don't enable full login after initial LIP */
  6016. nv->firmware_options_1 &= cpu_to_le32(~BIT_13);
  6017. /* Don't enable LIP full login for initiator */
  6018. nv->host_p &= cpu_to_le32(~BIT_10);
  6019. }
  6020. qlt_24xx_config_nvram_stage1(vha, nv);
  6021. /* Reset Initialization control block */
  6022. memset(icb, 0, ha->init_cb_size);
  6023. /* Copy 1st segment. */
  6024. dptr1 = (uint8_t *)icb;
  6025. dptr2 = (uint8_t *)&nv->version;
  6026. cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
  6027. while (cnt--)
  6028. *dptr1++ = *dptr2++;
  6029. icb->login_retry_count = nv->login_retry_count;
  6030. icb->link_down_on_nos = nv->link_down_on_nos;
  6031. /* Copy 2nd segment. */
  6032. dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
  6033. dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
  6034. cnt = (uint8_t *)&icb->reserved_3 -
  6035. (uint8_t *)&icb->interrupt_delay_timer;
  6036. while (cnt--)
  6037. *dptr1++ = *dptr2++;
  6038. ha->frame_payload_size = le16_to_cpu(icb->frame_payload_size);
  6039. /*
  6040. * Setup driver NVRAM options.
  6041. */
  6042. qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
  6043. "QLA2462");
  6044. qlt_24xx_config_nvram_stage2(vha, icb);
  6045. if (nv->host_p & cpu_to_le32(BIT_15)) {
  6046. /* Use alternate WWN? */
  6047. memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
  6048. memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
  6049. }
  6050. /* Prepare nodename */
  6051. if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) {
  6052. /*
  6053. * Firmware will apply the following mask if the nodename was
  6054. * not provided.
  6055. */
  6056. memcpy(icb->node_name, icb->port_name, WWN_SIZE);
  6057. icb->node_name[0] &= 0xF0;
  6058. }
  6059. /* Set host adapter parameters. */
  6060. ha->flags.disable_risc_code_load = 0;
  6061. ha->flags.enable_lip_reset = 0;
  6062. ha->flags.enable_lip_full_login =
  6063. le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
  6064. ha->flags.enable_target_reset =
  6065. le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
  6066. ha->flags.enable_led_scheme = 0;
  6067. ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
  6068. ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
  6069. (BIT_6 | BIT_5 | BIT_4)) >> 4;
  6070. memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
  6071. sizeof(ha->fw_seriallink_options24));
  6072. /* save HBA serial number */
  6073. ha->serial0 = icb->port_name[5];
  6074. ha->serial1 = icb->port_name[6];
  6075. ha->serial2 = icb->port_name[7];
  6076. memcpy(vha->node_name, icb->node_name, WWN_SIZE);
  6077. memcpy(vha->port_name, icb->port_name, WWN_SIZE);
  6078. icb->execution_throttle = cpu_to_le16(0xFFFF);
  6079. ha->retry_count = le16_to_cpu(nv->login_retry_count);
  6080. /* Set minimum login_timeout to 4 seconds. */
  6081. if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
  6082. nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
  6083. if (le16_to_cpu(nv->login_timeout) < 4)
  6084. nv->login_timeout = cpu_to_le16(4);
  6085. ha->login_timeout = le16_to_cpu(nv->login_timeout);
  6086. /* Set minimum RATOV to 100 tenths of a second. */
  6087. ha->r_a_tov = 100;
  6088. ha->loop_reset_delay = nv->reset_delay;
  6089. /* Link Down Timeout = 0:
  6090. *
  6091. * When Port Down timer expires we will start returning
  6092. * I/O's to OS with "DID_NO_CONNECT".
  6093. *
  6094. * Link Down Timeout != 0:
  6095. *
  6096. * The driver waits for the link to come up after link down
  6097. * before returning I/Os to OS with "DID_NO_CONNECT".
  6098. */
  6099. if (le16_to_cpu(nv->link_down_timeout) == 0) {
  6100. ha->loop_down_abort_time =
  6101. (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
  6102. } else {
  6103. ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
  6104. ha->loop_down_abort_time =
  6105. (LOOP_DOWN_TIME - ha->link_down_timeout);
  6106. }
  6107. /* Need enough time to try and get the port back. */
  6108. ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
  6109. if (qlport_down_retry)
  6110. ha->port_down_retry_count = qlport_down_retry;
  6111. /* Set login_retry_count */
  6112. ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
  6113. if (ha->port_down_retry_count ==
  6114. le16_to_cpu(nv->port_down_retry_count) &&
  6115. ha->port_down_retry_count > 3)
  6116. ha->login_retry_count = ha->port_down_retry_count;
  6117. else if (ha->port_down_retry_count > (int)ha->login_retry_count)
  6118. ha->login_retry_count = ha->port_down_retry_count;
  6119. if (ql2xloginretrycount)
  6120. ha->login_retry_count = ql2xloginretrycount;
  6121. /* N2N: driver will initiate Login instead of FW */
  6122. icb->firmware_options_3 |= BIT_8;
  6123. /* Enable ZIO. */
  6124. if (!vha->flags.init_done) {
  6125. ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
  6126. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  6127. ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
  6128. le16_to_cpu(icb->interrupt_delay_timer): 2;
  6129. }
  6130. icb->firmware_options_2 &= cpu_to_le32(
  6131. ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
  6132. if (ha->zio_mode != QLA_ZIO_DISABLED) {
  6133. ha->zio_mode = QLA_ZIO_MODE_6;
  6134. ql_log(ql_log_info, vha, 0x006f,
  6135. "ZIO mode %d enabled; timer delay (%d us).\n",
  6136. ha->zio_mode, ha->zio_timer * 100);
  6137. icb->firmware_options_2 |= cpu_to_le32(
  6138. (uint32_t)ha->zio_mode);
  6139. icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
  6140. }
  6141. if (rval) {
  6142. ql_log(ql_log_warn, vha, 0x0070,
  6143. "NVRAM configuration failed.\n");
  6144. }
  6145. return (rval);
  6146. }
  6147. uint8_t qla27xx_find_valid_image(struct scsi_qla_host *vha)
  6148. {
  6149. struct qla27xx_image_status pri_image_status, sec_image_status;
  6150. uint8_t valid_pri_image, valid_sec_image;
  6151. uint32_t *wptr;
  6152. uint32_t cnt, chksum, size;
  6153. struct qla_hw_data *ha = vha->hw;
  6154. valid_pri_image = valid_sec_image = 1;
  6155. ha->active_image = 0;
  6156. size = sizeof(struct qla27xx_image_status) / sizeof(uint32_t);
  6157. if (!ha->flt_region_img_status_pri) {
  6158. valid_pri_image = 0;
  6159. goto check_sec_image;
  6160. }
  6161. qla24xx_read_flash_data(vha, (uint32_t *)(&pri_image_status),
  6162. ha->flt_region_img_status_pri, size);
  6163. if (pri_image_status.signature != QLA27XX_IMG_STATUS_SIGN) {
  6164. ql_dbg(ql_dbg_init, vha, 0x018b,
  6165. "Primary image signature (0x%x) not valid\n",
  6166. pri_image_status.signature);
  6167. valid_pri_image = 0;
  6168. goto check_sec_image;
  6169. }
  6170. wptr = (uint32_t *)(&pri_image_status);
  6171. cnt = size;
  6172. for (chksum = 0; cnt--; wptr++)
  6173. chksum += le32_to_cpu(*wptr);
  6174. if (chksum) {
  6175. ql_dbg(ql_dbg_init, vha, 0x018c,
  6176. "Checksum validation failed for primary image (0x%x)\n",
  6177. chksum);
  6178. valid_pri_image = 0;
  6179. }
  6180. check_sec_image:
  6181. if (!ha->flt_region_img_status_sec) {
  6182. valid_sec_image = 0;
  6183. goto check_valid_image;
  6184. }
  6185. qla24xx_read_flash_data(vha, (uint32_t *)(&sec_image_status),
  6186. ha->flt_region_img_status_sec, size);
  6187. if (sec_image_status.signature != QLA27XX_IMG_STATUS_SIGN) {
  6188. ql_dbg(ql_dbg_init, vha, 0x018d,
  6189. "Secondary image signature(0x%x) not valid\n",
  6190. sec_image_status.signature);
  6191. valid_sec_image = 0;
  6192. goto check_valid_image;
  6193. }
  6194. wptr = (uint32_t *)(&sec_image_status);
  6195. cnt = size;
  6196. for (chksum = 0; cnt--; wptr++)
  6197. chksum += le32_to_cpu(*wptr);
  6198. if (chksum) {
  6199. ql_dbg(ql_dbg_init, vha, 0x018e,
  6200. "Checksum validation failed for secondary image (0x%x)\n",
  6201. chksum);
  6202. valid_sec_image = 0;
  6203. }
  6204. check_valid_image:
  6205. if (valid_pri_image && (pri_image_status.image_status_mask & 0x1))
  6206. ha->active_image = QLA27XX_PRIMARY_IMAGE;
  6207. if (valid_sec_image && (sec_image_status.image_status_mask & 0x1)) {
  6208. if (!ha->active_image ||
  6209. pri_image_status.generation_number <
  6210. sec_image_status.generation_number)
  6211. ha->active_image = QLA27XX_SECONDARY_IMAGE;
  6212. }
  6213. ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x018f, "%s image\n",
  6214. ha->active_image == 0 ? "default bootld and fw" :
  6215. ha->active_image == 1 ? "primary" :
  6216. ha->active_image == 2 ? "secondary" :
  6217. "Invalid");
  6218. return ha->active_image;
  6219. }
  6220. static int
  6221. qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
  6222. uint32_t faddr)
  6223. {
  6224. int rval = QLA_SUCCESS;
  6225. int segments, fragment;
  6226. uint32_t *dcode, dlen;
  6227. uint32_t risc_addr;
  6228. uint32_t risc_size;
  6229. uint32_t i;
  6230. struct qla_hw_data *ha = vha->hw;
  6231. struct req_que *req = ha->req_q_map[0];
  6232. ql_dbg(ql_dbg_init, vha, 0x008b,
  6233. "FW: Loading firmware from flash (%x).\n", faddr);
  6234. rval = QLA_SUCCESS;
  6235. segments = FA_RISC_CODE_SEGMENTS;
  6236. dcode = (uint32_t *)req->ring;
  6237. *srisc_addr = 0;
  6238. if (IS_QLA27XX(ha) &&
  6239. qla27xx_find_valid_image(vha) == QLA27XX_SECONDARY_IMAGE)
  6240. faddr = ha->flt_region_fw_sec;
  6241. /* Validate firmware image by checking version. */
  6242. qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
  6243. for (i = 0; i < 4; i++)
  6244. dcode[i] = be32_to_cpu(dcode[i]);
  6245. if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
  6246. dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
  6247. (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
  6248. dcode[3] == 0)) {
  6249. ql_log(ql_log_fatal, vha, 0x008c,
  6250. "Unable to verify the integrity of flash firmware "
  6251. "image.\n");
  6252. ql_log(ql_log_fatal, vha, 0x008d,
  6253. "Firmware data: %08x %08x %08x %08x.\n",
  6254. dcode[0], dcode[1], dcode[2], dcode[3]);
  6255. return QLA_FUNCTION_FAILED;
  6256. }
  6257. while (segments && rval == QLA_SUCCESS) {
  6258. /* Read segment's load information. */
  6259. qla24xx_read_flash_data(vha, dcode, faddr, 4);
  6260. risc_addr = be32_to_cpu(dcode[2]);
  6261. *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
  6262. risc_size = be32_to_cpu(dcode[3]);
  6263. fragment = 0;
  6264. while (risc_size > 0 && rval == QLA_SUCCESS) {
  6265. dlen = (uint32_t)(ha->fw_transfer_size >> 2);
  6266. if (dlen > risc_size)
  6267. dlen = risc_size;
  6268. ql_dbg(ql_dbg_init, vha, 0x008e,
  6269. "Loading risc segment@ risc addr %x "
  6270. "number of dwords 0x%x offset 0x%x.\n",
  6271. risc_addr, dlen, faddr);
  6272. qla24xx_read_flash_data(vha, dcode, faddr, dlen);
  6273. for (i = 0; i < dlen; i++)
  6274. dcode[i] = swab32(dcode[i]);
  6275. rval = qla2x00_load_ram(vha, req->dma, risc_addr,
  6276. dlen);
  6277. if (rval) {
  6278. ql_log(ql_log_fatal, vha, 0x008f,
  6279. "Failed to load segment %d of firmware.\n",
  6280. fragment);
  6281. return QLA_FUNCTION_FAILED;
  6282. }
  6283. faddr += dlen;
  6284. risc_addr += dlen;
  6285. risc_size -= dlen;
  6286. fragment++;
  6287. }
  6288. /* Next segment. */
  6289. segments--;
  6290. }
  6291. if (!IS_QLA27XX(ha))
  6292. return rval;
  6293. if (ha->fw_dump_template)
  6294. vfree(ha->fw_dump_template);
  6295. ha->fw_dump_template = NULL;
  6296. ha->fw_dump_template_len = 0;
  6297. ql_dbg(ql_dbg_init, vha, 0x0161,
  6298. "Loading fwdump template from %x\n", faddr);
  6299. qla24xx_read_flash_data(vha, dcode, faddr, 7);
  6300. risc_size = be32_to_cpu(dcode[2]);
  6301. ql_dbg(ql_dbg_init, vha, 0x0162,
  6302. "-> array size %x dwords\n", risc_size);
  6303. if (risc_size == 0 || risc_size == ~0)
  6304. goto default_template;
  6305. dlen = (risc_size - 8) * sizeof(*dcode);
  6306. ql_dbg(ql_dbg_init, vha, 0x0163,
  6307. "-> template allocating %x bytes...\n", dlen);
  6308. ha->fw_dump_template = vmalloc(dlen);
  6309. if (!ha->fw_dump_template) {
  6310. ql_log(ql_log_warn, vha, 0x0164,
  6311. "Failed fwdump template allocate %x bytes.\n", risc_size);
  6312. goto default_template;
  6313. }
  6314. faddr += 7;
  6315. risc_size -= 8;
  6316. dcode = ha->fw_dump_template;
  6317. qla24xx_read_flash_data(vha, dcode, faddr, risc_size);
  6318. for (i = 0; i < risc_size; i++)
  6319. dcode[i] = le32_to_cpu(dcode[i]);
  6320. if (!qla27xx_fwdt_template_valid(dcode)) {
  6321. ql_log(ql_log_warn, vha, 0x0165,
  6322. "Failed fwdump template validate\n");
  6323. goto default_template;
  6324. }
  6325. dlen = qla27xx_fwdt_template_size(dcode);
  6326. ql_dbg(ql_dbg_init, vha, 0x0166,
  6327. "-> template size %x bytes\n", dlen);
  6328. if (dlen > risc_size * sizeof(*dcode)) {
  6329. ql_log(ql_log_warn, vha, 0x0167,
  6330. "Failed fwdump template exceeds array by %zx bytes\n",
  6331. (size_t)(dlen - risc_size * sizeof(*dcode)));
  6332. goto default_template;
  6333. }
  6334. ha->fw_dump_template_len = dlen;
  6335. return rval;
  6336. default_template:
  6337. ql_log(ql_log_warn, vha, 0x0168, "Using default fwdump template\n");
  6338. if (ha->fw_dump_template)
  6339. vfree(ha->fw_dump_template);
  6340. ha->fw_dump_template = NULL;
  6341. ha->fw_dump_template_len = 0;
  6342. dlen = qla27xx_fwdt_template_default_size();
  6343. ql_dbg(ql_dbg_init, vha, 0x0169,
  6344. "-> template allocating %x bytes...\n", dlen);
  6345. ha->fw_dump_template = vmalloc(dlen);
  6346. if (!ha->fw_dump_template) {
  6347. ql_log(ql_log_warn, vha, 0x016a,
  6348. "Failed fwdump template allocate %x bytes.\n", risc_size);
  6349. goto failed_template;
  6350. }
  6351. dcode = ha->fw_dump_template;
  6352. risc_size = dlen / sizeof(*dcode);
  6353. memcpy(dcode, qla27xx_fwdt_template_default(), dlen);
  6354. for (i = 0; i < risc_size; i++)
  6355. dcode[i] = be32_to_cpu(dcode[i]);
  6356. if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
  6357. ql_log(ql_log_warn, vha, 0x016b,
  6358. "Failed fwdump template validate\n");
  6359. goto failed_template;
  6360. }
  6361. dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
  6362. ql_dbg(ql_dbg_init, vha, 0x016c,
  6363. "-> template size %x bytes\n", dlen);
  6364. ha->fw_dump_template_len = dlen;
  6365. return rval;
  6366. failed_template:
  6367. ql_log(ql_log_warn, vha, 0x016d, "Failed default fwdump template\n");
  6368. if (ha->fw_dump_template)
  6369. vfree(ha->fw_dump_template);
  6370. ha->fw_dump_template = NULL;
  6371. ha->fw_dump_template_len = 0;
  6372. return rval;
  6373. }
  6374. #define QLA_FW_URL "http://ldriver.qlogic.com/firmware/"
  6375. int
  6376. qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
  6377. {
  6378. int rval;
  6379. int i, fragment;
  6380. uint16_t *wcode, *fwcode;
  6381. uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
  6382. struct fw_blob *blob;
  6383. struct qla_hw_data *ha = vha->hw;
  6384. struct req_que *req = ha->req_q_map[0];
  6385. /* Load firmware blob. */
  6386. blob = qla2x00_request_firmware(vha);
  6387. if (!blob) {
  6388. ql_log(ql_log_info, vha, 0x0084,
  6389. "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
  6390. return QLA_FUNCTION_FAILED;
  6391. }
  6392. rval = QLA_SUCCESS;
  6393. wcode = (uint16_t *)req->ring;
  6394. *srisc_addr = 0;
  6395. fwcode = (uint16_t *)blob->fw->data;
  6396. fwclen = 0;
  6397. /* Validate firmware image by checking version. */
  6398. if (blob->fw->size < 8 * sizeof(uint16_t)) {
  6399. ql_log(ql_log_fatal, vha, 0x0085,
  6400. "Unable to verify integrity of firmware image (%zd).\n",
  6401. blob->fw->size);
  6402. goto fail_fw_integrity;
  6403. }
  6404. for (i = 0; i < 4; i++)
  6405. wcode[i] = be16_to_cpu(fwcode[i + 4]);
  6406. if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
  6407. wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
  6408. wcode[2] == 0 && wcode[3] == 0)) {
  6409. ql_log(ql_log_fatal, vha, 0x0086,
  6410. "Unable to verify integrity of firmware image.\n");
  6411. ql_log(ql_log_fatal, vha, 0x0087,
  6412. "Firmware data: %04x %04x %04x %04x.\n",
  6413. wcode[0], wcode[1], wcode[2], wcode[3]);
  6414. goto fail_fw_integrity;
  6415. }
  6416. seg = blob->segs;
  6417. while (*seg && rval == QLA_SUCCESS) {
  6418. risc_addr = *seg;
  6419. *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
  6420. risc_size = be16_to_cpu(fwcode[3]);
  6421. /* Validate firmware image size. */
  6422. fwclen += risc_size * sizeof(uint16_t);
  6423. if (blob->fw->size < fwclen) {
  6424. ql_log(ql_log_fatal, vha, 0x0088,
  6425. "Unable to verify integrity of firmware image "
  6426. "(%zd).\n", blob->fw->size);
  6427. goto fail_fw_integrity;
  6428. }
  6429. fragment = 0;
  6430. while (risc_size > 0 && rval == QLA_SUCCESS) {
  6431. wlen = (uint16_t)(ha->fw_transfer_size >> 1);
  6432. if (wlen > risc_size)
  6433. wlen = risc_size;
  6434. ql_dbg(ql_dbg_init, vha, 0x0089,
  6435. "Loading risc segment@ risc addr %x number of "
  6436. "words 0x%x.\n", risc_addr, wlen);
  6437. for (i = 0; i < wlen; i++)
  6438. wcode[i] = swab16(fwcode[i]);
  6439. rval = qla2x00_load_ram(vha, req->dma, risc_addr,
  6440. wlen);
  6441. if (rval) {
  6442. ql_log(ql_log_fatal, vha, 0x008a,
  6443. "Failed to load segment %d of firmware.\n",
  6444. fragment);
  6445. break;
  6446. }
  6447. fwcode += wlen;
  6448. risc_addr += wlen;
  6449. risc_size -= wlen;
  6450. fragment++;
  6451. }
  6452. /* Next segment. */
  6453. seg++;
  6454. }
  6455. return rval;
  6456. fail_fw_integrity:
  6457. return QLA_FUNCTION_FAILED;
  6458. }
  6459. static int
  6460. qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
  6461. {
  6462. int rval;
  6463. int segments, fragment;
  6464. uint32_t *dcode, dlen;
  6465. uint32_t risc_addr;
  6466. uint32_t risc_size;
  6467. uint32_t i;
  6468. struct fw_blob *blob;
  6469. const uint32_t *fwcode;
  6470. uint32_t fwclen;
  6471. struct qla_hw_data *ha = vha->hw;
  6472. struct req_que *req = ha->req_q_map[0];
  6473. /* Load firmware blob. */
  6474. blob = qla2x00_request_firmware(vha);
  6475. if (!blob) {
  6476. ql_log(ql_log_warn, vha, 0x0091,
  6477. "Firmware images can be retrieved from: "
  6478. QLA_FW_URL ".\n");
  6479. return QLA_FUNCTION_FAILED;
  6480. }
  6481. ql_dbg(ql_dbg_init, vha, 0x0092,
  6482. "FW: Loading via request-firmware.\n");
  6483. rval = QLA_SUCCESS;
  6484. segments = FA_RISC_CODE_SEGMENTS;
  6485. dcode = (uint32_t *)req->ring;
  6486. *srisc_addr = 0;
  6487. fwcode = (uint32_t *)blob->fw->data;
  6488. fwclen = 0;
  6489. /* Validate firmware image by checking version. */
  6490. if (blob->fw->size < 8 * sizeof(uint32_t)) {
  6491. ql_log(ql_log_fatal, vha, 0x0093,
  6492. "Unable to verify integrity of firmware image (%zd).\n",
  6493. blob->fw->size);
  6494. return QLA_FUNCTION_FAILED;
  6495. }
  6496. for (i = 0; i < 4; i++)
  6497. dcode[i] = be32_to_cpu(fwcode[i + 4]);
  6498. if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
  6499. dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
  6500. (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
  6501. dcode[3] == 0)) {
  6502. ql_log(ql_log_fatal, vha, 0x0094,
  6503. "Unable to verify integrity of firmware image (%zd).\n",
  6504. blob->fw->size);
  6505. ql_log(ql_log_fatal, vha, 0x0095,
  6506. "Firmware data: %08x %08x %08x %08x.\n",
  6507. dcode[0], dcode[1], dcode[2], dcode[3]);
  6508. return QLA_FUNCTION_FAILED;
  6509. }
  6510. while (segments && rval == QLA_SUCCESS) {
  6511. risc_addr = be32_to_cpu(fwcode[2]);
  6512. *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
  6513. risc_size = be32_to_cpu(fwcode[3]);
  6514. /* Validate firmware image size. */
  6515. fwclen += risc_size * sizeof(uint32_t);
  6516. if (blob->fw->size < fwclen) {
  6517. ql_log(ql_log_fatal, vha, 0x0096,
  6518. "Unable to verify integrity of firmware image "
  6519. "(%zd).\n", blob->fw->size);
  6520. return QLA_FUNCTION_FAILED;
  6521. }
  6522. fragment = 0;
  6523. while (risc_size > 0 && rval == QLA_SUCCESS) {
  6524. dlen = (uint32_t)(ha->fw_transfer_size >> 2);
  6525. if (dlen > risc_size)
  6526. dlen = risc_size;
  6527. ql_dbg(ql_dbg_init, vha, 0x0097,
  6528. "Loading risc segment@ risc addr %x "
  6529. "number of dwords 0x%x.\n", risc_addr, dlen);
  6530. for (i = 0; i < dlen; i++)
  6531. dcode[i] = swab32(fwcode[i]);
  6532. rval = qla2x00_load_ram(vha, req->dma, risc_addr,
  6533. dlen);
  6534. if (rval) {
  6535. ql_log(ql_log_fatal, vha, 0x0098,
  6536. "Failed to load segment %d of firmware.\n",
  6537. fragment);
  6538. return QLA_FUNCTION_FAILED;
  6539. }
  6540. fwcode += dlen;
  6541. risc_addr += dlen;
  6542. risc_size -= dlen;
  6543. fragment++;
  6544. }
  6545. /* Next segment. */
  6546. segments--;
  6547. }
  6548. if (!IS_QLA27XX(ha))
  6549. return rval;
  6550. if (ha->fw_dump_template)
  6551. vfree(ha->fw_dump_template);
  6552. ha->fw_dump_template = NULL;
  6553. ha->fw_dump_template_len = 0;
  6554. ql_dbg(ql_dbg_init, vha, 0x171,
  6555. "Loading fwdump template from %x\n",
  6556. (uint32_t)((void *)fwcode - (void *)blob->fw->data));
  6557. risc_size = be32_to_cpu(fwcode[2]);
  6558. ql_dbg(ql_dbg_init, vha, 0x172,
  6559. "-> array size %x dwords\n", risc_size);
  6560. if (risc_size == 0 || risc_size == ~0)
  6561. goto default_template;
  6562. dlen = (risc_size - 8) * sizeof(*fwcode);
  6563. ql_dbg(ql_dbg_init, vha, 0x0173,
  6564. "-> template allocating %x bytes...\n", dlen);
  6565. ha->fw_dump_template = vmalloc(dlen);
  6566. if (!ha->fw_dump_template) {
  6567. ql_log(ql_log_warn, vha, 0x0174,
  6568. "Failed fwdump template allocate %x bytes.\n", risc_size);
  6569. goto default_template;
  6570. }
  6571. fwcode += 7;
  6572. risc_size -= 8;
  6573. dcode = ha->fw_dump_template;
  6574. for (i = 0; i < risc_size; i++)
  6575. dcode[i] = le32_to_cpu(fwcode[i]);
  6576. if (!qla27xx_fwdt_template_valid(dcode)) {
  6577. ql_log(ql_log_warn, vha, 0x0175,
  6578. "Failed fwdump template validate\n");
  6579. goto default_template;
  6580. }
  6581. dlen = qla27xx_fwdt_template_size(dcode);
  6582. ql_dbg(ql_dbg_init, vha, 0x0176,
  6583. "-> template size %x bytes\n", dlen);
  6584. if (dlen > risc_size * sizeof(*fwcode)) {
  6585. ql_log(ql_log_warn, vha, 0x0177,
  6586. "Failed fwdump template exceeds array by %zx bytes\n",
  6587. (size_t)(dlen - risc_size * sizeof(*fwcode)));
  6588. goto default_template;
  6589. }
  6590. ha->fw_dump_template_len = dlen;
  6591. return rval;
  6592. default_template:
  6593. ql_log(ql_log_warn, vha, 0x0178, "Using default fwdump template\n");
  6594. if (ha->fw_dump_template)
  6595. vfree(ha->fw_dump_template);
  6596. ha->fw_dump_template = NULL;
  6597. ha->fw_dump_template_len = 0;
  6598. dlen = qla27xx_fwdt_template_default_size();
  6599. ql_dbg(ql_dbg_init, vha, 0x0179,
  6600. "-> template allocating %x bytes...\n", dlen);
  6601. ha->fw_dump_template = vmalloc(dlen);
  6602. if (!ha->fw_dump_template) {
  6603. ql_log(ql_log_warn, vha, 0x017a,
  6604. "Failed fwdump template allocate %x bytes.\n", risc_size);
  6605. goto failed_template;
  6606. }
  6607. dcode = ha->fw_dump_template;
  6608. risc_size = dlen / sizeof(*fwcode);
  6609. fwcode = qla27xx_fwdt_template_default();
  6610. for (i = 0; i < risc_size; i++)
  6611. dcode[i] = be32_to_cpu(fwcode[i]);
  6612. if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
  6613. ql_log(ql_log_warn, vha, 0x017b,
  6614. "Failed fwdump template validate\n");
  6615. goto failed_template;
  6616. }
  6617. dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
  6618. ql_dbg(ql_dbg_init, vha, 0x017c,
  6619. "-> template size %x bytes\n", dlen);
  6620. ha->fw_dump_template_len = dlen;
  6621. return rval;
  6622. failed_template:
  6623. ql_log(ql_log_warn, vha, 0x017d, "Failed default fwdump template\n");
  6624. if (ha->fw_dump_template)
  6625. vfree(ha->fw_dump_template);
  6626. ha->fw_dump_template = NULL;
  6627. ha->fw_dump_template_len = 0;
  6628. return rval;
  6629. }
  6630. int
  6631. qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
  6632. {
  6633. int rval;
  6634. if (ql2xfwloadbin == 1)
  6635. return qla81xx_load_risc(vha, srisc_addr);
  6636. /*
  6637. * FW Load priority:
  6638. * 1) Firmware via request-firmware interface (.bin file).
  6639. * 2) Firmware residing in flash.
  6640. */
  6641. rval = qla24xx_load_risc_blob(vha, srisc_addr);
  6642. if (rval == QLA_SUCCESS)
  6643. return rval;
  6644. return qla24xx_load_risc_flash(vha, srisc_addr,
  6645. vha->hw->flt_region_fw);
  6646. }
  6647. int
  6648. qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
  6649. {
  6650. int rval;
  6651. struct qla_hw_data *ha = vha->hw;
  6652. if (ql2xfwloadbin == 2)
  6653. goto try_blob_fw;
  6654. /*
  6655. * FW Load priority:
  6656. * 1) Firmware residing in flash.
  6657. * 2) Firmware via request-firmware interface (.bin file).
  6658. * 3) Golden-Firmware residing in flash -- limited operation.
  6659. */
  6660. rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
  6661. if (rval == QLA_SUCCESS)
  6662. return rval;
  6663. try_blob_fw:
  6664. rval = qla24xx_load_risc_blob(vha, srisc_addr);
  6665. if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
  6666. return rval;
  6667. ql_log(ql_log_info, vha, 0x0099,
  6668. "Attempting to fallback to golden firmware.\n");
  6669. rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
  6670. if (rval != QLA_SUCCESS)
  6671. return rval;
  6672. ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
  6673. ha->flags.running_gold_fw = 1;
  6674. return rval;
  6675. }
  6676. void
  6677. qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
  6678. {
  6679. int ret, retries;
  6680. struct qla_hw_data *ha = vha->hw;
  6681. if (ha->flags.pci_channel_io_perm_failure)
  6682. return;
  6683. if (!IS_FWI2_CAPABLE(ha))
  6684. return;
  6685. if (!ha->fw_major_version)
  6686. return;
  6687. if (!ha->flags.fw_started)
  6688. return;
  6689. ret = qla2x00_stop_firmware(vha);
  6690. for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
  6691. ret != QLA_INVALID_COMMAND && retries ; retries--) {
  6692. ha->isp_ops->reset_chip(vha);
  6693. if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
  6694. continue;
  6695. if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
  6696. continue;
  6697. ql_log(ql_log_info, vha, 0x8015,
  6698. "Attempting retry of stop-firmware command.\n");
  6699. ret = qla2x00_stop_firmware(vha);
  6700. }
  6701. QLA_FW_STOPPED(ha);
  6702. ha->flags.fw_init_done = 0;
  6703. }
  6704. int
  6705. qla24xx_configure_vhba(scsi_qla_host_t *vha)
  6706. {
  6707. int rval = QLA_SUCCESS;
  6708. int rval2;
  6709. uint16_t mb[MAILBOX_REGISTER_COUNT];
  6710. struct qla_hw_data *ha = vha->hw;
  6711. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  6712. struct req_que *req;
  6713. struct rsp_que *rsp;
  6714. if (!vha->vp_idx)
  6715. return -EINVAL;
  6716. rval = qla2x00_fw_ready(base_vha);
  6717. if (vha->qpair)
  6718. req = vha->qpair->req;
  6719. else
  6720. req = ha->req_q_map[0];
  6721. rsp = req->rsp;
  6722. if (rval == QLA_SUCCESS) {
  6723. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  6724. qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
  6725. }
  6726. vha->flags.management_server_logged_in = 0;
  6727. /* Login to SNS first */
  6728. rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
  6729. BIT_1);
  6730. if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
  6731. if (rval2 == QLA_MEMORY_ALLOC_FAILED)
  6732. ql_dbg(ql_dbg_init, vha, 0x0120,
  6733. "Failed SNS login: loop_id=%x, rval2=%d\n",
  6734. NPH_SNS, rval2);
  6735. else
  6736. ql_dbg(ql_dbg_init, vha, 0x0103,
  6737. "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
  6738. "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
  6739. NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
  6740. return (QLA_FUNCTION_FAILED);
  6741. }
  6742. atomic_set(&vha->loop_down_timer, 0);
  6743. atomic_set(&vha->loop_state, LOOP_UP);
  6744. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  6745. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  6746. rval = qla2x00_loop_resync(base_vha);
  6747. return rval;
  6748. }
  6749. /* 84XX Support **************************************************************/
  6750. static LIST_HEAD(qla_cs84xx_list);
  6751. static DEFINE_MUTEX(qla_cs84xx_mutex);
  6752. static struct qla_chip_state_84xx *
  6753. qla84xx_get_chip(struct scsi_qla_host *vha)
  6754. {
  6755. struct qla_chip_state_84xx *cs84xx;
  6756. struct qla_hw_data *ha = vha->hw;
  6757. mutex_lock(&qla_cs84xx_mutex);
  6758. /* Find any shared 84xx chip. */
  6759. list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
  6760. if (cs84xx->bus == ha->pdev->bus) {
  6761. kref_get(&cs84xx->kref);
  6762. goto done;
  6763. }
  6764. }
  6765. cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
  6766. if (!cs84xx)
  6767. goto done;
  6768. kref_init(&cs84xx->kref);
  6769. spin_lock_init(&cs84xx->access_lock);
  6770. mutex_init(&cs84xx->fw_update_mutex);
  6771. cs84xx->bus = ha->pdev->bus;
  6772. list_add_tail(&cs84xx->list, &qla_cs84xx_list);
  6773. done:
  6774. mutex_unlock(&qla_cs84xx_mutex);
  6775. return cs84xx;
  6776. }
  6777. static void
  6778. __qla84xx_chip_release(struct kref *kref)
  6779. {
  6780. struct qla_chip_state_84xx *cs84xx =
  6781. container_of(kref, struct qla_chip_state_84xx, kref);
  6782. mutex_lock(&qla_cs84xx_mutex);
  6783. list_del(&cs84xx->list);
  6784. mutex_unlock(&qla_cs84xx_mutex);
  6785. kfree(cs84xx);
  6786. }
  6787. void
  6788. qla84xx_put_chip(struct scsi_qla_host *vha)
  6789. {
  6790. struct qla_hw_data *ha = vha->hw;
  6791. if (ha->cs84xx)
  6792. kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
  6793. }
  6794. static int
  6795. qla84xx_init_chip(scsi_qla_host_t *vha)
  6796. {
  6797. int rval;
  6798. uint16_t status[2];
  6799. struct qla_hw_data *ha = vha->hw;
  6800. mutex_lock(&ha->cs84xx->fw_update_mutex);
  6801. rval = qla84xx_verify_chip(vha, status);
  6802. mutex_unlock(&ha->cs84xx->fw_update_mutex);
  6803. return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
  6804. QLA_SUCCESS;
  6805. }
  6806. /* 81XX Support **************************************************************/
  6807. int
  6808. qla81xx_nvram_config(scsi_qla_host_t *vha)
  6809. {
  6810. int rval;
  6811. struct init_cb_81xx *icb;
  6812. struct nvram_81xx *nv;
  6813. uint32_t *dptr;
  6814. uint8_t *dptr1, *dptr2;
  6815. uint32_t chksum;
  6816. uint16_t cnt;
  6817. struct qla_hw_data *ha = vha->hw;
  6818. rval = QLA_SUCCESS;
  6819. icb = (struct init_cb_81xx *)ha->init_cb;
  6820. nv = ha->nvram;
  6821. /* Determine NVRAM starting address. */
  6822. ha->nvram_size = sizeof(struct nvram_81xx);
  6823. ha->vpd_size = FA_NVRAM_VPD_SIZE;
  6824. if (IS_P3P_TYPE(ha) || IS_QLA8031(ha))
  6825. ha->vpd_size = FA_VPD_SIZE_82XX;
  6826. /* Get VPD data into cache */
  6827. ha->vpd = ha->nvram + VPD_OFFSET;
  6828. ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
  6829. ha->vpd_size);
  6830. /* Get NVRAM data into cache and calculate checksum. */
  6831. ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
  6832. ha->nvram_size);
  6833. dptr = (uint32_t *)nv;
  6834. for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++)
  6835. chksum += le32_to_cpu(*dptr);
  6836. ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
  6837. "Contents of NVRAM:\n");
  6838. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
  6839. (uint8_t *)nv, ha->nvram_size);
  6840. /* Bad NVRAM data, set defaults parameters. */
  6841. if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
  6842. || nv->id[3] != ' ' ||
  6843. nv->nvram_version < cpu_to_le16(ICB_VERSION)) {
  6844. /* Reset NVRAM data. */
  6845. ql_log(ql_log_info, vha, 0x0073,
  6846. "Inconsistent NVRAM detected: checksum=0x%x id=%c "
  6847. "version=0x%x.\n", chksum, nv->id[0],
  6848. le16_to_cpu(nv->nvram_version));
  6849. ql_log(ql_log_info, vha, 0x0074,
  6850. "Falling back to functioning (yet invalid -- WWPN) "
  6851. "defaults.\n");
  6852. /*
  6853. * Set default initialization control block.
  6854. */
  6855. memset(nv, 0, ha->nvram_size);
  6856. nv->nvram_version = cpu_to_le16(ICB_VERSION);
  6857. nv->version = cpu_to_le16(ICB_VERSION);
  6858. nv->frame_payload_size = 2048;
  6859. nv->execution_throttle = cpu_to_le16(0xFFFF);
  6860. nv->exchange_count = cpu_to_le16(0);
  6861. nv->port_name[0] = 0x21;
  6862. nv->port_name[1] = 0x00 + ha->port_no + 1;
  6863. nv->port_name[2] = 0x00;
  6864. nv->port_name[3] = 0xe0;
  6865. nv->port_name[4] = 0x8b;
  6866. nv->port_name[5] = 0x1c;
  6867. nv->port_name[6] = 0x55;
  6868. nv->port_name[7] = 0x86;
  6869. nv->node_name[0] = 0x20;
  6870. nv->node_name[1] = 0x00;
  6871. nv->node_name[2] = 0x00;
  6872. nv->node_name[3] = 0xe0;
  6873. nv->node_name[4] = 0x8b;
  6874. nv->node_name[5] = 0x1c;
  6875. nv->node_name[6] = 0x55;
  6876. nv->node_name[7] = 0x86;
  6877. nv->login_retry_count = cpu_to_le16(8);
  6878. nv->interrupt_delay_timer = cpu_to_le16(0);
  6879. nv->login_timeout = cpu_to_le16(0);
  6880. nv->firmware_options_1 =
  6881. cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
  6882. nv->firmware_options_2 = cpu_to_le32(2 << 4);
  6883. nv->firmware_options_2 |= cpu_to_le32(BIT_12);
  6884. nv->firmware_options_3 = cpu_to_le32(2 << 13);
  6885. nv->host_p = cpu_to_le32(BIT_11|BIT_10);
  6886. nv->efi_parameters = cpu_to_le32(0);
  6887. nv->reset_delay = 5;
  6888. nv->max_luns_per_target = cpu_to_le16(128);
  6889. nv->port_down_retry_count = cpu_to_le16(30);
  6890. nv->link_down_timeout = cpu_to_le16(180);
  6891. nv->enode_mac[0] = 0x00;
  6892. nv->enode_mac[1] = 0xC0;
  6893. nv->enode_mac[2] = 0xDD;
  6894. nv->enode_mac[3] = 0x04;
  6895. nv->enode_mac[4] = 0x05;
  6896. nv->enode_mac[5] = 0x06 + ha->port_no + 1;
  6897. rval = 1;
  6898. }
  6899. if (IS_T10_PI_CAPABLE(ha))
  6900. nv->frame_payload_size &= ~7;
  6901. qlt_81xx_config_nvram_stage1(vha, nv);
  6902. /* Reset Initialization control block */
  6903. memset(icb, 0, ha->init_cb_size);
  6904. /* Copy 1st segment. */
  6905. dptr1 = (uint8_t *)icb;
  6906. dptr2 = (uint8_t *)&nv->version;
  6907. cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
  6908. while (cnt--)
  6909. *dptr1++ = *dptr2++;
  6910. icb->login_retry_count = nv->login_retry_count;
  6911. /* Copy 2nd segment. */
  6912. dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
  6913. dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
  6914. cnt = (uint8_t *)&icb->reserved_5 -
  6915. (uint8_t *)&icb->interrupt_delay_timer;
  6916. while (cnt--)
  6917. *dptr1++ = *dptr2++;
  6918. memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
  6919. /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
  6920. if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
  6921. icb->enode_mac[0] = 0x00;
  6922. icb->enode_mac[1] = 0xC0;
  6923. icb->enode_mac[2] = 0xDD;
  6924. icb->enode_mac[3] = 0x04;
  6925. icb->enode_mac[4] = 0x05;
  6926. icb->enode_mac[5] = 0x06 + ha->port_no + 1;
  6927. }
  6928. /* Use extended-initialization control block. */
  6929. memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
  6930. ha->frame_payload_size = le16_to_cpu(icb->frame_payload_size);
  6931. /*
  6932. * Setup driver NVRAM options.
  6933. */
  6934. qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
  6935. "QLE8XXX");
  6936. qlt_81xx_config_nvram_stage2(vha, icb);
  6937. /* Use alternate WWN? */
  6938. if (nv->host_p & cpu_to_le32(BIT_15)) {
  6939. memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
  6940. memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
  6941. }
  6942. /* Prepare nodename */
  6943. if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) {
  6944. /*
  6945. * Firmware will apply the following mask if the nodename was
  6946. * not provided.
  6947. */
  6948. memcpy(icb->node_name, icb->port_name, WWN_SIZE);
  6949. icb->node_name[0] &= 0xF0;
  6950. }
  6951. /* Set host adapter parameters. */
  6952. ha->flags.disable_risc_code_load = 0;
  6953. ha->flags.enable_lip_reset = 0;
  6954. ha->flags.enable_lip_full_login =
  6955. le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
  6956. ha->flags.enable_target_reset =
  6957. le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
  6958. ha->flags.enable_led_scheme = 0;
  6959. ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
  6960. ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
  6961. (BIT_6 | BIT_5 | BIT_4)) >> 4;
  6962. /* save HBA serial number */
  6963. ha->serial0 = icb->port_name[5];
  6964. ha->serial1 = icb->port_name[6];
  6965. ha->serial2 = icb->port_name[7];
  6966. memcpy(vha->node_name, icb->node_name, WWN_SIZE);
  6967. memcpy(vha->port_name, icb->port_name, WWN_SIZE);
  6968. icb->execution_throttle = cpu_to_le16(0xFFFF);
  6969. ha->retry_count = le16_to_cpu(nv->login_retry_count);
  6970. /* Set minimum login_timeout to 4 seconds. */
  6971. if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
  6972. nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
  6973. if (le16_to_cpu(nv->login_timeout) < 4)
  6974. nv->login_timeout = cpu_to_le16(4);
  6975. ha->login_timeout = le16_to_cpu(nv->login_timeout);
  6976. /* Set minimum RATOV to 100 tenths of a second. */
  6977. ha->r_a_tov = 100;
  6978. ha->loop_reset_delay = nv->reset_delay;
  6979. /* Link Down Timeout = 0:
  6980. *
  6981. * When Port Down timer expires we will start returning
  6982. * I/O's to OS with "DID_NO_CONNECT".
  6983. *
  6984. * Link Down Timeout != 0:
  6985. *
  6986. * The driver waits for the link to come up after link down
  6987. * before returning I/Os to OS with "DID_NO_CONNECT".
  6988. */
  6989. if (le16_to_cpu(nv->link_down_timeout) == 0) {
  6990. ha->loop_down_abort_time =
  6991. (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
  6992. } else {
  6993. ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
  6994. ha->loop_down_abort_time =
  6995. (LOOP_DOWN_TIME - ha->link_down_timeout);
  6996. }
  6997. /* Need enough time to try and get the port back. */
  6998. ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
  6999. if (qlport_down_retry)
  7000. ha->port_down_retry_count = qlport_down_retry;
  7001. /* Set login_retry_count */
  7002. ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
  7003. if (ha->port_down_retry_count ==
  7004. le16_to_cpu(nv->port_down_retry_count) &&
  7005. ha->port_down_retry_count > 3)
  7006. ha->login_retry_count = ha->port_down_retry_count;
  7007. else if (ha->port_down_retry_count > (int)ha->login_retry_count)
  7008. ha->login_retry_count = ha->port_down_retry_count;
  7009. if (ql2xloginretrycount)
  7010. ha->login_retry_count = ql2xloginretrycount;
  7011. /* if not running MSI-X we need handshaking on interrupts */
  7012. if (!vha->hw->flags.msix_enabled && (IS_QLA83XX(ha) || IS_QLA27XX(ha)))
  7013. icb->firmware_options_2 |= cpu_to_le32(BIT_22);
  7014. /* Enable ZIO. */
  7015. if (!vha->flags.init_done) {
  7016. ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
  7017. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  7018. ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
  7019. le16_to_cpu(icb->interrupt_delay_timer): 2;
  7020. }
  7021. icb->firmware_options_2 &= cpu_to_le32(
  7022. ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
  7023. vha->flags.process_response_queue = 0;
  7024. if (ha->zio_mode != QLA_ZIO_DISABLED) {
  7025. ha->zio_mode = QLA_ZIO_MODE_6;
  7026. ql_log(ql_log_info, vha, 0x0075,
  7027. "ZIO mode %d enabled; timer delay (%d us).\n",
  7028. ha->zio_mode,
  7029. ha->zio_timer * 100);
  7030. icb->firmware_options_2 |= cpu_to_le32(
  7031. (uint32_t)ha->zio_mode);
  7032. icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
  7033. vha->flags.process_response_queue = 1;
  7034. }
  7035. /* enable RIDA Format2 */
  7036. icb->firmware_options_3 |= BIT_0;
  7037. /* N2N: driver will initiate Login instead of FW */
  7038. icb->firmware_options_3 |= BIT_8;
  7039. if (IS_QLA27XX(ha)) {
  7040. icb->firmware_options_3 |= BIT_8;
  7041. ql_dbg(ql_log_info, vha, 0x0075,
  7042. "Enabling direct connection.\n");
  7043. }
  7044. if (rval) {
  7045. ql_log(ql_log_warn, vha, 0x0076,
  7046. "NVRAM configuration failed.\n");
  7047. }
  7048. return (rval);
  7049. }
  7050. int
  7051. qla82xx_restart_isp(scsi_qla_host_t *vha)
  7052. {
  7053. int status, rval;
  7054. struct qla_hw_data *ha = vha->hw;
  7055. struct req_que *req = ha->req_q_map[0];
  7056. struct rsp_que *rsp = ha->rsp_q_map[0];
  7057. struct scsi_qla_host *vp;
  7058. unsigned long flags;
  7059. status = qla2x00_init_rings(vha);
  7060. if (!status) {
  7061. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  7062. ha->flags.chip_reset_done = 1;
  7063. status = qla2x00_fw_ready(vha);
  7064. if (!status) {
  7065. /* Issue a marker after FW becomes ready. */
  7066. qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
  7067. vha->flags.online = 1;
  7068. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  7069. }
  7070. /* if no cable then assume it's good */
  7071. if ((vha->device_flags & DFLG_NO_CABLE))
  7072. status = 0;
  7073. }
  7074. if (!status) {
  7075. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  7076. if (!atomic_read(&vha->loop_down_timer)) {
  7077. /*
  7078. * Issue marker command only when we are going
  7079. * to start the I/O .
  7080. */
  7081. vha->marker_needed = 1;
  7082. }
  7083. ha->isp_ops->enable_intrs(ha);
  7084. ha->isp_abort_cnt = 0;
  7085. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  7086. /* Update the firmware version */
  7087. status = qla82xx_check_md_needed(vha);
  7088. if (ha->fce) {
  7089. ha->flags.fce_enabled = 1;
  7090. memset(ha->fce, 0,
  7091. fce_calc_size(ha->fce_bufs));
  7092. rval = qla2x00_enable_fce_trace(vha,
  7093. ha->fce_dma, ha->fce_bufs, ha->fce_mb,
  7094. &ha->fce_bufs);
  7095. if (rval) {
  7096. ql_log(ql_log_warn, vha, 0x8001,
  7097. "Unable to reinitialize FCE (%d).\n",
  7098. rval);
  7099. ha->flags.fce_enabled = 0;
  7100. }
  7101. }
  7102. if (ha->eft) {
  7103. memset(ha->eft, 0, EFT_SIZE);
  7104. rval = qla2x00_enable_eft_trace(vha,
  7105. ha->eft_dma, EFT_NUM_BUFFERS);
  7106. if (rval) {
  7107. ql_log(ql_log_warn, vha, 0x8010,
  7108. "Unable to reinitialize EFT (%d).\n",
  7109. rval);
  7110. }
  7111. }
  7112. }
  7113. if (!status) {
  7114. ql_dbg(ql_dbg_taskm, vha, 0x8011,
  7115. "qla82xx_restart_isp succeeded.\n");
  7116. spin_lock_irqsave(&ha->vport_slock, flags);
  7117. list_for_each_entry(vp, &ha->vp_list, list) {
  7118. if (vp->vp_idx) {
  7119. atomic_inc(&vp->vref_count);
  7120. spin_unlock_irqrestore(&ha->vport_slock, flags);
  7121. qla2x00_vp_abort_isp(vp);
  7122. spin_lock_irqsave(&ha->vport_slock, flags);
  7123. atomic_dec(&vp->vref_count);
  7124. }
  7125. }
  7126. spin_unlock_irqrestore(&ha->vport_slock, flags);
  7127. } else {
  7128. ql_log(ql_log_warn, vha, 0x8016,
  7129. "qla82xx_restart_isp **** FAILED ****.\n");
  7130. }
  7131. return status;
  7132. }
  7133. void
  7134. qla81xx_update_fw_options(scsi_qla_host_t *vha)
  7135. {
  7136. struct qla_hw_data *ha = vha->hw;
  7137. /* Hold status IOCBs until ABTS response received. */
  7138. if (ql2xfwholdabts)
  7139. ha->fw_options[3] |= BIT_12;
  7140. /* Set Retry FLOGI in case of P2P connection */
  7141. if (ha->operating_mode == P2P) {
  7142. ha->fw_options[2] |= BIT_3;
  7143. ql_dbg(ql_dbg_disc, vha, 0x2103,
  7144. "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
  7145. __func__, ha->fw_options[2]);
  7146. }
  7147. /* Move PUREX, ABTS RX & RIDA to ATIOQ */
  7148. if (ql2xmvasynctoatio) {
  7149. if (qla_tgt_mode_enabled(vha) ||
  7150. qla_dual_mode_enabled(vha))
  7151. ha->fw_options[2] |= BIT_11;
  7152. else
  7153. ha->fw_options[2] &= ~BIT_11;
  7154. }
  7155. if (qla_tgt_mode_enabled(vha) ||
  7156. qla_dual_mode_enabled(vha)) {
  7157. /* FW auto send SCSI status during */
  7158. ha->fw_options[1] |= BIT_8;
  7159. ha->fw_options[10] |= (u16)SAM_STAT_BUSY << 8;
  7160. /* FW perform Exchange validation */
  7161. ha->fw_options[2] |= BIT_4;
  7162. } else {
  7163. ha->fw_options[1] &= ~BIT_8;
  7164. ha->fw_options[10] &= 0x00ff;
  7165. ha->fw_options[2] &= ~BIT_4;
  7166. }
  7167. if (ql2xetsenable) {
  7168. /* Enable ETS Burst. */
  7169. memset(ha->fw_options, 0, sizeof(ha->fw_options));
  7170. ha->fw_options[2] |= BIT_9;
  7171. }
  7172. ql_dbg(ql_dbg_init, vha, 0x00e9,
  7173. "%s, add FW options 1-3 = 0x%04x 0x%04x 0x%04x mode %x\n",
  7174. __func__, ha->fw_options[1], ha->fw_options[2],
  7175. ha->fw_options[3], vha->host->active_mode);
  7176. qla2x00_set_fw_options(vha, ha->fw_options);
  7177. }
  7178. /*
  7179. * qla24xx_get_fcp_prio
  7180. * Gets the fcp cmd priority value for the logged in port.
  7181. * Looks for a match of the port descriptors within
  7182. * each of the fcp prio config entries. If a match is found,
  7183. * the tag (priority) value is returned.
  7184. *
  7185. * Input:
  7186. * vha = scsi host structure pointer.
  7187. * fcport = port structure pointer.
  7188. *
  7189. * Return:
  7190. * non-zero (if found)
  7191. * -1 (if not found)
  7192. *
  7193. * Context:
  7194. * Kernel context
  7195. */
  7196. static int
  7197. qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
  7198. {
  7199. int i, entries;
  7200. uint8_t pid_match, wwn_match;
  7201. int priority;
  7202. uint32_t pid1, pid2;
  7203. uint64_t wwn1, wwn2;
  7204. struct qla_fcp_prio_entry *pri_entry;
  7205. struct qla_hw_data *ha = vha->hw;
  7206. if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
  7207. return -1;
  7208. priority = -1;
  7209. entries = ha->fcp_prio_cfg->num_entries;
  7210. pri_entry = &ha->fcp_prio_cfg->entry[0];
  7211. for (i = 0; i < entries; i++) {
  7212. pid_match = wwn_match = 0;
  7213. if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
  7214. pri_entry++;
  7215. continue;
  7216. }
  7217. /* check source pid for a match */
  7218. if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
  7219. pid1 = pri_entry->src_pid & INVALID_PORT_ID;
  7220. pid2 = vha->d_id.b24 & INVALID_PORT_ID;
  7221. if (pid1 == INVALID_PORT_ID)
  7222. pid_match++;
  7223. else if (pid1 == pid2)
  7224. pid_match++;
  7225. }
  7226. /* check destination pid for a match */
  7227. if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
  7228. pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
  7229. pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
  7230. if (pid1 == INVALID_PORT_ID)
  7231. pid_match++;
  7232. else if (pid1 == pid2)
  7233. pid_match++;
  7234. }
  7235. /* check source WWN for a match */
  7236. if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
  7237. wwn1 = wwn_to_u64(vha->port_name);
  7238. wwn2 = wwn_to_u64(pri_entry->src_wwpn);
  7239. if (wwn2 == (uint64_t)-1)
  7240. wwn_match++;
  7241. else if (wwn1 == wwn2)
  7242. wwn_match++;
  7243. }
  7244. /* check destination WWN for a match */
  7245. if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
  7246. wwn1 = wwn_to_u64(fcport->port_name);
  7247. wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
  7248. if (wwn2 == (uint64_t)-1)
  7249. wwn_match++;
  7250. else if (wwn1 == wwn2)
  7251. wwn_match++;
  7252. }
  7253. if (pid_match == 2 || wwn_match == 2) {
  7254. /* Found a matching entry */
  7255. if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
  7256. priority = pri_entry->tag;
  7257. break;
  7258. }
  7259. pri_entry++;
  7260. }
  7261. return priority;
  7262. }
  7263. /*
  7264. * qla24xx_update_fcport_fcp_prio
  7265. * Activates fcp priority for the logged in fc port
  7266. *
  7267. * Input:
  7268. * vha = scsi host structure pointer.
  7269. * fcp = port structure pointer.
  7270. *
  7271. * Return:
  7272. * QLA_SUCCESS or QLA_FUNCTION_FAILED
  7273. *
  7274. * Context:
  7275. * Kernel context.
  7276. */
  7277. int
  7278. qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
  7279. {
  7280. int ret;
  7281. int priority;
  7282. uint16_t mb[5];
  7283. if (fcport->port_type != FCT_TARGET ||
  7284. fcport->loop_id == FC_NO_LOOP_ID)
  7285. return QLA_FUNCTION_FAILED;
  7286. priority = qla24xx_get_fcp_prio(vha, fcport);
  7287. if (priority < 0)
  7288. return QLA_FUNCTION_FAILED;
  7289. if (IS_P3P_TYPE(vha->hw)) {
  7290. fcport->fcp_prio = priority & 0xf;
  7291. return QLA_SUCCESS;
  7292. }
  7293. ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
  7294. if (ret == QLA_SUCCESS) {
  7295. if (fcport->fcp_prio != priority)
  7296. ql_dbg(ql_dbg_user, vha, 0x709e,
  7297. "Updated FCP_CMND priority - value=%d loop_id=%d "
  7298. "port_id=%02x%02x%02x.\n", priority,
  7299. fcport->loop_id, fcport->d_id.b.domain,
  7300. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  7301. fcport->fcp_prio = priority & 0xf;
  7302. } else
  7303. ql_dbg(ql_dbg_user, vha, 0x704f,
  7304. "Unable to update FCP_CMND priority - ret=0x%x for "
  7305. "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
  7306. fcport->d_id.b.domain, fcport->d_id.b.area,
  7307. fcport->d_id.b.al_pa);
  7308. return ret;
  7309. }
  7310. /*
  7311. * qla24xx_update_all_fcp_prio
  7312. * Activates fcp priority for all the logged in ports
  7313. *
  7314. * Input:
  7315. * ha = adapter block pointer.
  7316. *
  7317. * Return:
  7318. * QLA_SUCCESS or QLA_FUNCTION_FAILED
  7319. *
  7320. * Context:
  7321. * Kernel context.
  7322. */
  7323. int
  7324. qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
  7325. {
  7326. int ret;
  7327. fc_port_t *fcport;
  7328. ret = QLA_FUNCTION_FAILED;
  7329. /* We need to set priority for all logged in ports */
  7330. list_for_each_entry(fcport, &vha->vp_fcports, list)
  7331. ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
  7332. return ret;
  7333. }
  7334. struct qla_qpair *qla2xxx_create_qpair(struct scsi_qla_host *vha, int qos,
  7335. int vp_idx, bool startqp)
  7336. {
  7337. int rsp_id = 0;
  7338. int req_id = 0;
  7339. int i;
  7340. struct qla_hw_data *ha = vha->hw;
  7341. uint16_t qpair_id = 0;
  7342. struct qla_qpair *qpair = NULL;
  7343. struct qla_msix_entry *msix;
  7344. if (!(ha->fw_attributes & BIT_6) || !ha->flags.msix_enabled) {
  7345. ql_log(ql_log_warn, vha, 0x00181,
  7346. "FW/Driver is not multi-queue capable.\n");
  7347. return NULL;
  7348. }
  7349. if (ql2xmqsupport || ql2xnvmeenable) {
  7350. qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
  7351. if (qpair == NULL) {
  7352. ql_log(ql_log_warn, vha, 0x0182,
  7353. "Failed to allocate memory for queue pair.\n");
  7354. return NULL;
  7355. }
  7356. memset(qpair, 0, sizeof(struct qla_qpair));
  7357. qpair->hw = vha->hw;
  7358. qpair->vha = vha;
  7359. qpair->qp_lock_ptr = &qpair->qp_lock;
  7360. spin_lock_init(&qpair->qp_lock);
  7361. qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
  7362. /* Assign available que pair id */
  7363. mutex_lock(&ha->mq_lock);
  7364. qpair_id = find_first_zero_bit(ha->qpair_qid_map, ha->max_qpairs);
  7365. if (ha->num_qpairs >= ha->max_qpairs) {
  7366. mutex_unlock(&ha->mq_lock);
  7367. ql_log(ql_log_warn, vha, 0x0183,
  7368. "No resources to create additional q pair.\n");
  7369. goto fail_qid_map;
  7370. }
  7371. ha->num_qpairs++;
  7372. set_bit(qpair_id, ha->qpair_qid_map);
  7373. ha->queue_pair_map[qpair_id] = qpair;
  7374. qpair->id = qpair_id;
  7375. qpair->vp_idx = vp_idx;
  7376. qpair->fw_started = ha->flags.fw_started;
  7377. INIT_LIST_HEAD(&qpair->hints_list);
  7378. qpair->chip_reset = ha->base_qpair->chip_reset;
  7379. qpair->enable_class_2 = ha->base_qpair->enable_class_2;
  7380. qpair->enable_explicit_conf =
  7381. ha->base_qpair->enable_explicit_conf;
  7382. for (i = 0; i < ha->msix_count; i++) {
  7383. msix = &ha->msix_entries[i];
  7384. if (msix->in_use)
  7385. continue;
  7386. qpair->msix = msix;
  7387. ql_dbg(ql_dbg_multiq, vha, 0xc00f,
  7388. "Vector %x selected for qpair\n", msix->vector);
  7389. break;
  7390. }
  7391. if (!qpair->msix) {
  7392. ql_log(ql_log_warn, vha, 0x0184,
  7393. "Out of MSI-X vectors!.\n");
  7394. goto fail_msix;
  7395. }
  7396. qpair->msix->in_use = 1;
  7397. list_add_tail(&qpair->qp_list_elem, &vha->qp_list);
  7398. qpair->pdev = ha->pdev;
  7399. if (IS_QLA27XX(ha) || IS_QLA83XX(ha))
  7400. qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
  7401. mutex_unlock(&ha->mq_lock);
  7402. /* Create response queue first */
  7403. rsp_id = qla25xx_create_rsp_que(ha, 0, 0, 0, qpair, startqp);
  7404. if (!rsp_id) {
  7405. ql_log(ql_log_warn, vha, 0x0185,
  7406. "Failed to create response queue.\n");
  7407. goto fail_rsp;
  7408. }
  7409. qpair->rsp = ha->rsp_q_map[rsp_id];
  7410. /* Create request queue */
  7411. req_id = qla25xx_create_req_que(ha, 0, vp_idx, 0, rsp_id, qos,
  7412. startqp);
  7413. if (!req_id) {
  7414. ql_log(ql_log_warn, vha, 0x0186,
  7415. "Failed to create request queue.\n");
  7416. goto fail_req;
  7417. }
  7418. qpair->req = ha->req_q_map[req_id];
  7419. qpair->rsp->req = qpair->req;
  7420. qpair->rsp->qpair = qpair;
  7421. /* init qpair to this cpu. Will adjust at run time. */
  7422. qla_cpu_update(qpair, smp_processor_id());
  7423. if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
  7424. if (ha->fw_attributes & BIT_4)
  7425. qpair->difdix_supported = 1;
  7426. }
  7427. qpair->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
  7428. if (!qpair->srb_mempool) {
  7429. ql_log(ql_log_warn, vha, 0xd036,
  7430. "Failed to create srb mempool for qpair %d\n",
  7431. qpair->id);
  7432. goto fail_mempool;
  7433. }
  7434. /* Mark as online */
  7435. qpair->online = 1;
  7436. if (!vha->flags.qpairs_available)
  7437. vha->flags.qpairs_available = 1;
  7438. ql_dbg(ql_dbg_multiq, vha, 0xc00d,
  7439. "Request/Response queue pair created, id %d\n",
  7440. qpair->id);
  7441. ql_dbg(ql_dbg_init, vha, 0x0187,
  7442. "Request/Response queue pair created, id %d\n",
  7443. qpair->id);
  7444. }
  7445. return qpair;
  7446. fail_mempool:
  7447. fail_req:
  7448. qla25xx_delete_rsp_que(vha, qpair->rsp);
  7449. fail_rsp:
  7450. mutex_lock(&ha->mq_lock);
  7451. qpair->msix->in_use = 0;
  7452. list_del(&qpair->qp_list_elem);
  7453. if (list_empty(&vha->qp_list))
  7454. vha->flags.qpairs_available = 0;
  7455. fail_msix:
  7456. ha->queue_pair_map[qpair_id] = NULL;
  7457. clear_bit(qpair_id, ha->qpair_qid_map);
  7458. ha->num_qpairs--;
  7459. mutex_unlock(&ha->mq_lock);
  7460. fail_qid_map:
  7461. kfree(qpair);
  7462. return NULL;
  7463. }
  7464. int qla2xxx_delete_qpair(struct scsi_qla_host *vha, struct qla_qpair *qpair)
  7465. {
  7466. int ret = QLA_FUNCTION_FAILED;
  7467. struct qla_hw_data *ha = qpair->hw;
  7468. qpair->delete_in_progress = 1;
  7469. ret = qla25xx_delete_req_que(vha, qpair->req);
  7470. if (ret != QLA_SUCCESS)
  7471. goto fail;
  7472. ret = qla25xx_delete_rsp_que(vha, qpair->rsp);
  7473. if (ret != QLA_SUCCESS)
  7474. goto fail;
  7475. mutex_lock(&ha->mq_lock);
  7476. ha->queue_pair_map[qpair->id] = NULL;
  7477. clear_bit(qpair->id, ha->qpair_qid_map);
  7478. ha->num_qpairs--;
  7479. list_del(&qpair->qp_list_elem);
  7480. if (list_empty(&vha->qp_list)) {
  7481. vha->flags.qpairs_available = 0;
  7482. vha->flags.qpairs_req_created = 0;
  7483. vha->flags.qpairs_rsp_created = 0;
  7484. }
  7485. mempool_destroy(qpair->srb_mempool);
  7486. kfree(qpair);
  7487. mutex_unlock(&ha->mq_lock);
  7488. return QLA_SUCCESS;
  7489. fail:
  7490. return ret;
  7491. }