gdth.c 174 KB

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  1. /************************************************************************
  2. * Linux driver for *
  3. * ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers *
  4. * Intel Corporation: Storage RAID Controllers *
  5. * *
  6. * gdth.c *
  7. * Copyright (C) 1995-06 ICP vortex GmbH, Achim Leubner *
  8. * Copyright (C) 2002-04 Intel Corporation *
  9. * Copyright (C) 2003-06 Adaptec Inc. *
  10. * <achim_leubner@adaptec.com> *
  11. * *
  12. * Additions/Fixes: *
  13. * Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> *
  14. * Johannes Dinner <johannes_dinner@adaptec.com> *
  15. * *
  16. * This program is free software; you can redistribute it and/or modify *
  17. * it under the terms of the GNU General Public License as published *
  18. * by the Free Software Foundation; either version 2 of the License, *
  19. * or (at your option) any later version. *
  20. * *
  21. * This program is distributed in the hope that it will be useful, *
  22. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  23. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  24. * GNU General Public License for more details. *
  25. * *
  26. * You should have received a copy of the GNU General Public License *
  27. * along with this kernel; if not, write to the Free Software *
  28. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
  29. * *
  30. * Linux kernel 2.6.x supported *
  31. * *
  32. ************************************************************************/
  33. /* All GDT Disk Array Controllers are fully supported by this driver.
  34. * This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the
  35. * PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete
  36. * list of all controller types.
  37. *
  38. * If you have one or more GDT3000/3020 EISA controllers with
  39. * controller BIOS disabled, you have to set the IRQ values with the
  40. * command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are
  41. * the IRQ values for the EISA controllers.
  42. *
  43. * After the optional list of IRQ values, other possible
  44. * command line options are:
  45. * disable:Y disable driver
  46. * disable:N enable driver
  47. * reserve_mode:0 reserve no drives for the raw service
  48. * reserve_mode:1 reserve all not init., removable drives
  49. * reserve_mode:2 reserve all not init. drives
  50. * reserve_list:h,b,t,l,h,b,t,l,... reserve particular drive(s) with
  51. * h- controller no., b- channel no.,
  52. * t- target ID, l- LUN
  53. * reverse_scan:Y reverse scan order for PCI controllers
  54. * reverse_scan:N scan PCI controllers like BIOS
  55. * max_ids:x x - target ID count per channel (1..MAXID)
  56. * rescan:Y rescan all channels/IDs
  57. * rescan:N use all devices found until now
  58. * hdr_channel:x x - number of virtual bus for host drives
  59. * shared_access:Y disable driver reserve/release protocol to
  60. * access a shared resource from several nodes,
  61. * appropriate controller firmware required
  62. * shared_access:N enable driver reserve/release protocol
  63. * probe_eisa_isa:Y scan for EISA/ISA controllers
  64. * probe_eisa_isa:N do not scan for EISA/ISA controllers
  65. * force_dma32:Y use only 32 bit DMA mode
  66. * force_dma32:N use 64 bit DMA mode, if supported
  67. *
  68. * The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N,
  69. * max_ids:127,rescan:N,hdr_channel:0,
  70. * shared_access:Y,probe_eisa_isa:N,force_dma32:N".
  71. * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y".
  72. *
  73. * When loading the gdth driver as a module, the same options are available.
  74. * You can set the IRQs with "IRQ=...". However, the syntax to specify the
  75. * options changes slightly. You must replace all ',' between options
  76. * with ' ' and all ':' with '=' and you must use
  77. * '1' in place of 'Y' and '0' in place of 'N'.
  78. *
  79. * Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0
  80. * max_ids=127 rescan=0 hdr_channel=0 shared_access=0
  81. * probe_eisa_isa=0 force_dma32=0"
  82. * The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1".
  83. */
  84. /* The meaning of the Scsi_Pointer members in this driver is as follows:
  85. * ptr: Chaining
  86. * this_residual: unused
  87. * buffer: unused
  88. * dma_handle: unused
  89. * buffers_residual: unused
  90. * Status: unused
  91. * Message: unused
  92. * have_data_in: unused
  93. * sent_command: unused
  94. * phase: unused
  95. */
  96. /* interrupt coalescing */
  97. /* #define INT_COAL */
  98. /* statistics */
  99. #define GDTH_STATISTICS
  100. #include <linux/module.h>
  101. #include <linux/version.h>
  102. #include <linux/kernel.h>
  103. #include <linux/types.h>
  104. #include <linux/pci.h>
  105. #include <linux/string.h>
  106. #include <linux/ctype.h>
  107. #include <linux/ioport.h>
  108. #include <linux/delay.h>
  109. #include <linux/interrupt.h>
  110. #include <linux/in.h>
  111. #include <linux/proc_fs.h>
  112. #include <linux/time.h>
  113. #include <linux/timer.h>
  114. #include <linux/dma-mapping.h>
  115. #include <linux/list.h>
  116. #include <linux/mutex.h>
  117. #include <linux/slab.h>
  118. #ifdef GDTH_RTC
  119. #include <linux/mc146818rtc.h>
  120. #endif
  121. #include <linux/reboot.h>
  122. #include <asm/dma.h>
  123. #include <asm/io.h>
  124. #include <linux/uaccess.h>
  125. #include <linux/spinlock.h>
  126. #include <linux/blkdev.h>
  127. #include <linux/scatterlist.h>
  128. #include "scsi.h"
  129. #include <scsi/scsi_host.h>
  130. #include "gdth.h"
  131. static DEFINE_MUTEX(gdth_mutex);
  132. static void gdth_delay(int milliseconds);
  133. static void gdth_eval_mapping(u32 size, u32 *cyls, int *heads, int *secs);
  134. static irqreturn_t gdth_interrupt(int irq, void *dev_id);
  135. static irqreturn_t __gdth_interrupt(gdth_ha_str *ha,
  136. int gdth_from_wait, int* pIndex);
  137. static int gdth_sync_event(gdth_ha_str *ha, int service, u8 index,
  138. struct scsi_cmnd *scp);
  139. static int gdth_async_event(gdth_ha_str *ha);
  140. static void gdth_log_event(gdth_evt_data *dvr, char *buffer);
  141. static void gdth_putq(gdth_ha_str *ha, struct scsi_cmnd *scp, u8 priority);
  142. static void gdth_next(gdth_ha_str *ha);
  143. static int gdth_fill_raw_cmd(gdth_ha_str *ha, struct scsi_cmnd *scp, u8 b);
  144. static int gdth_special_cmd(gdth_ha_str *ha, struct scsi_cmnd *scp);
  145. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, u16 source,
  146. u16 idx, gdth_evt_data *evt);
  147. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr);
  148. static void gdth_readapp_event(gdth_ha_str *ha, u8 application,
  149. gdth_evt_str *estr);
  150. static void gdth_clear_events(void);
  151. static void gdth_copy_internal_data(gdth_ha_str *ha, struct scsi_cmnd *scp,
  152. char *buffer, u16 count);
  153. static int gdth_internal_cache_cmd(gdth_ha_str *ha, struct scsi_cmnd *scp);
  154. static int gdth_fill_cache_cmd(gdth_ha_str *ha, struct scsi_cmnd *scp,
  155. u16 hdrive);
  156. static void gdth_enable_int(gdth_ha_str *ha);
  157. static int gdth_test_busy(gdth_ha_str *ha);
  158. static int gdth_get_cmd_index(gdth_ha_str *ha);
  159. static void gdth_release_event(gdth_ha_str *ha);
  160. static int gdth_wait(gdth_ha_str *ha, int index,u32 time);
  161. static int gdth_internal_cmd(gdth_ha_str *ha, u8 service, u16 opcode,
  162. u32 p1, u64 p2,u64 p3);
  163. static int gdth_search_drives(gdth_ha_str *ha);
  164. static int gdth_analyse_hdrive(gdth_ha_str *ha, u16 hdrive);
  165. static const char *gdth_ctr_name(gdth_ha_str *ha);
  166. static int gdth_open(struct inode *inode, struct file *filep);
  167. static int gdth_close(struct inode *inode, struct file *filep);
  168. static long gdth_unlocked_ioctl(struct file *filep, unsigned int cmd,
  169. unsigned long arg);
  170. static void gdth_flush(gdth_ha_str *ha);
  171. static int gdth_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
  172. static int __gdth_queuecommand(gdth_ha_str *ha, struct scsi_cmnd *scp,
  173. struct gdth_cmndinfo *cmndinfo);
  174. static void gdth_scsi_done(struct scsi_cmnd *scp);
  175. #ifdef DEBUG_GDTH
  176. static u8 DebugState = DEBUG_GDTH;
  177. #ifdef __SERIAL__
  178. #define MAX_SERBUF 160
  179. static void ser_init(void);
  180. static void ser_puts(char *str);
  181. static void ser_putc(char c);
  182. static int ser_printk(const char *fmt, ...);
  183. static char strbuf[MAX_SERBUF+1];
  184. #ifdef __COM2__
  185. #define COM_BASE 0x2f8
  186. #else
  187. #define COM_BASE 0x3f8
  188. #endif
  189. static void ser_init()
  190. {
  191. unsigned port=COM_BASE;
  192. outb(0x80,port+3);
  193. outb(0,port+1);
  194. /* 19200 Baud, if 9600: outb(12,port) */
  195. outb(6, port);
  196. outb(3,port+3);
  197. outb(0,port+1);
  198. /*
  199. ser_putc('I');
  200. ser_putc(' ');
  201. */
  202. }
  203. static void ser_puts(char *str)
  204. {
  205. char *ptr;
  206. ser_init();
  207. for (ptr=str;*ptr;++ptr)
  208. ser_putc(*ptr);
  209. }
  210. static void ser_putc(char c)
  211. {
  212. unsigned port=COM_BASE;
  213. while ((inb(port+5) & 0x20)==0);
  214. outb(c,port);
  215. if (c==0x0a)
  216. {
  217. while ((inb(port+5) & 0x20)==0);
  218. outb(0x0d,port);
  219. }
  220. }
  221. static int ser_printk(const char *fmt, ...)
  222. {
  223. va_list args;
  224. int i;
  225. va_start(args,fmt);
  226. i = vsprintf(strbuf,fmt,args);
  227. ser_puts(strbuf);
  228. va_end(args);
  229. return i;
  230. }
  231. #define TRACE(a) {if (DebugState==1) {ser_printk a;}}
  232. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {ser_printk a;}}
  233. #define TRACE3(a) {if (DebugState!=0) {ser_printk a;}}
  234. #else /* !__SERIAL__ */
  235. #define TRACE(a) {if (DebugState==1) {printk a;}}
  236. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {printk a;}}
  237. #define TRACE3(a) {if (DebugState!=0) {printk a;}}
  238. #endif
  239. #else /* !DEBUG */
  240. #define TRACE(a)
  241. #define TRACE2(a)
  242. #define TRACE3(a)
  243. #endif
  244. #ifdef GDTH_STATISTICS
  245. static u32 max_rq=0, max_index=0, max_sg=0;
  246. #ifdef INT_COAL
  247. static u32 max_int_coal=0;
  248. #endif
  249. static u32 act_ints=0, act_ios=0, act_stats=0, act_rq=0;
  250. static struct timer_list gdth_timer;
  251. #endif
  252. #define PTR2USHORT(a) (u16)(unsigned long)(a)
  253. #define GDTOFFSOF(a,b) (size_t)&(((a*)0)->b)
  254. #define INDEX_OK(i,t) ((i)<ARRAY_SIZE(t))
  255. #define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b))
  256. #ifdef CONFIG_ISA
  257. static u8 gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */
  258. #endif
  259. #if defined(CONFIG_EISA) || defined(CONFIG_ISA)
  260. static u8 gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */
  261. #endif
  262. static u8 gdth_polling; /* polling if TRUE */
  263. static int gdth_ctr_count = 0; /* controller count */
  264. static LIST_HEAD(gdth_instances); /* controller list */
  265. static u8 gdth_write_through = FALSE; /* write through */
  266. static gdth_evt_str ebuffer[MAX_EVENTS]; /* event buffer */
  267. static int elastidx;
  268. static int eoldidx;
  269. static int major;
  270. #define DIN 1 /* IN data direction */
  271. #define DOU 2 /* OUT data direction */
  272. #define DNO DIN /* no data transfer */
  273. #define DUN DIN /* unknown data direction */
  274. static u8 gdth_direction_tab[0x100] = {
  275. DNO,DNO,DIN,DIN,DOU,DIN,DIN,DOU,DIN,DUN,DOU,DOU,DUN,DUN,DUN,DIN,
  276. DNO,DIN,DIN,DOU,DIN,DOU,DNO,DNO,DOU,DNO,DIN,DNO,DIN,DOU,DNO,DUN,
  277. DIN,DUN,DIN,DUN,DOU,DIN,DUN,DUN,DIN,DIN,DOU,DNO,DUN,DIN,DOU,DOU,
  278. DOU,DOU,DOU,DNO,DIN,DNO,DNO,DIN,DOU,DOU,DOU,DOU,DIN,DOU,DIN,DOU,
  279. DOU,DOU,DIN,DIN,DIN,DNO,DUN,DNO,DNO,DNO,DUN,DNO,DOU,DIN,DUN,DUN,
  280. DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DIN,DUN,DUN,DUN,DUN,DUN,
  281. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  282. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  283. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  284. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,
  285. DUN,DUN,DUN,DUN,DUN,DNO,DNO,DUN,DIN,DNO,DOU,DUN,DNO,DUN,DOU,DOU,
  286. DOU,DOU,DOU,DNO,DUN,DIN,DOU,DIN,DIN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  287. DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  288. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  289. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  290. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN
  291. };
  292. /* LILO and modprobe/insmod parameters */
  293. /* IRQ list for GDT3000/3020 EISA controllers */
  294. static int irq[MAXHA] __initdata =
  295. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  296. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  297. /* disable driver flag */
  298. static int disable __initdata = 0;
  299. /* reserve flag */
  300. static int reserve_mode = 1;
  301. /* reserve list */
  302. static int reserve_list[MAX_RES_ARGS] =
  303. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  304. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  305. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  306. /* scan order for PCI controllers */
  307. static int reverse_scan = 0;
  308. /* virtual channel for the host drives */
  309. static int hdr_channel = 0;
  310. /* max. IDs per channel */
  311. static int max_ids = MAXID;
  312. /* rescan all IDs */
  313. static int rescan = 0;
  314. /* shared access */
  315. static int shared_access = 1;
  316. /* enable support for EISA and ISA controllers */
  317. static int probe_eisa_isa = 0;
  318. /* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */
  319. static int force_dma32 = 0;
  320. /* parameters for modprobe/insmod */
  321. module_param_hw_array(irq, int, irq, NULL, 0);
  322. module_param(disable, int, 0);
  323. module_param(reserve_mode, int, 0);
  324. module_param_array(reserve_list, int, NULL, 0);
  325. module_param(reverse_scan, int, 0);
  326. module_param(hdr_channel, int, 0);
  327. module_param(max_ids, int, 0);
  328. module_param(rescan, int, 0);
  329. module_param(shared_access, int, 0);
  330. module_param(probe_eisa_isa, int, 0);
  331. module_param(force_dma32, int, 0);
  332. MODULE_AUTHOR("Achim Leubner");
  333. MODULE_LICENSE("GPL");
  334. /* ioctl interface */
  335. static const struct file_operations gdth_fops = {
  336. .unlocked_ioctl = gdth_unlocked_ioctl,
  337. .open = gdth_open,
  338. .release = gdth_close,
  339. .llseek = noop_llseek,
  340. };
  341. #include "gdth_proc.h"
  342. #include "gdth_proc.c"
  343. static gdth_ha_str *gdth_find_ha(int hanum)
  344. {
  345. gdth_ha_str *ha;
  346. list_for_each_entry(ha, &gdth_instances, list)
  347. if (hanum == ha->hanum)
  348. return ha;
  349. return NULL;
  350. }
  351. static struct gdth_cmndinfo *gdth_get_cmndinfo(gdth_ha_str *ha)
  352. {
  353. struct gdth_cmndinfo *priv = NULL;
  354. unsigned long flags;
  355. int i;
  356. spin_lock_irqsave(&ha->smp_lock, flags);
  357. for (i=0; i<GDTH_MAXCMDS; ++i) {
  358. if (ha->cmndinfo[i].index == 0) {
  359. priv = &ha->cmndinfo[i];
  360. memset(priv, 0, sizeof(*priv));
  361. priv->index = i+1;
  362. break;
  363. }
  364. }
  365. spin_unlock_irqrestore(&ha->smp_lock, flags);
  366. return priv;
  367. }
  368. static void gdth_put_cmndinfo(struct gdth_cmndinfo *priv)
  369. {
  370. BUG_ON(!priv);
  371. priv->index = 0;
  372. }
  373. static void gdth_delay(int milliseconds)
  374. {
  375. if (milliseconds == 0) {
  376. udelay(1);
  377. } else {
  378. mdelay(milliseconds);
  379. }
  380. }
  381. static void gdth_scsi_done(struct scsi_cmnd *scp)
  382. {
  383. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  384. int internal_command = cmndinfo->internal_command;
  385. TRACE2(("gdth_scsi_done()\n"));
  386. gdth_put_cmndinfo(cmndinfo);
  387. scp->host_scribble = NULL;
  388. if (internal_command)
  389. complete((struct completion *)scp->request);
  390. else
  391. scp->scsi_done(scp);
  392. }
  393. int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
  394. int timeout, u32 *info)
  395. {
  396. gdth_ha_str *ha = shost_priv(sdev->host);
  397. struct scsi_cmnd *scp;
  398. struct gdth_cmndinfo cmndinfo;
  399. DECLARE_COMPLETION_ONSTACK(wait);
  400. int rval;
  401. scp = kzalloc(sizeof(*scp), GFP_KERNEL);
  402. if (!scp)
  403. return -ENOMEM;
  404. scp->sense_buffer = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
  405. if (!scp->sense_buffer) {
  406. kfree(scp);
  407. return -ENOMEM;
  408. }
  409. scp->device = sdev;
  410. memset(&cmndinfo, 0, sizeof(cmndinfo));
  411. /* use request field to save the ptr. to completion struct. */
  412. scp->request = (struct request *)&wait;
  413. scp->cmd_len = 12;
  414. scp->cmnd = cmnd;
  415. cmndinfo.priority = IOCTL_PRI;
  416. cmndinfo.internal_cmd_str = gdtcmd;
  417. cmndinfo.internal_command = 1;
  418. TRACE(("__gdth_execute() cmd 0x%x\n", scp->cmnd[0]));
  419. __gdth_queuecommand(ha, scp, &cmndinfo);
  420. wait_for_completion(&wait);
  421. rval = cmndinfo.status;
  422. if (info)
  423. *info = cmndinfo.info;
  424. kfree(scp->sense_buffer);
  425. kfree(scp);
  426. return rval;
  427. }
  428. int gdth_execute(struct Scsi_Host *shost, gdth_cmd_str *gdtcmd, char *cmnd,
  429. int timeout, u32 *info)
  430. {
  431. struct scsi_device *sdev = scsi_get_host_dev(shost);
  432. int rval = __gdth_execute(sdev, gdtcmd, cmnd, timeout, info);
  433. scsi_free_host_dev(sdev);
  434. return rval;
  435. }
  436. static void gdth_eval_mapping(u32 size, u32 *cyls, int *heads, int *secs)
  437. {
  438. *cyls = size /HEADS/SECS;
  439. if (*cyls <= MAXCYLS) {
  440. *heads = HEADS;
  441. *secs = SECS;
  442. } else { /* too high for 64*32 */
  443. *cyls = size /MEDHEADS/MEDSECS;
  444. if (*cyls <= MAXCYLS) {
  445. *heads = MEDHEADS;
  446. *secs = MEDSECS;
  447. } else { /* too high for 127*63 */
  448. *cyls = size /BIGHEADS/BIGSECS;
  449. *heads = BIGHEADS;
  450. *secs = BIGSECS;
  451. }
  452. }
  453. }
  454. /* controller search and initialization functions */
  455. #ifdef CONFIG_EISA
  456. static int __init gdth_search_eisa(u16 eisa_adr)
  457. {
  458. u32 id;
  459. TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr));
  460. id = inl(eisa_adr+ID0REG);
  461. if (id == GDT3A_ID || id == GDT3B_ID) { /* GDT3000A or GDT3000B */
  462. if ((inb(eisa_adr+EISAREG) & 8) == 0)
  463. return 0; /* not EISA configured */
  464. return 1;
  465. }
  466. if (id == GDT3_ID) /* GDT3000 */
  467. return 1;
  468. return 0;
  469. }
  470. #endif /* CONFIG_EISA */
  471. #ifdef CONFIG_ISA
  472. static int __init gdth_search_isa(u32 bios_adr)
  473. {
  474. void __iomem *addr;
  475. u32 id;
  476. TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr));
  477. if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(u32))) != NULL) {
  478. id = readl(addr);
  479. iounmap(addr);
  480. if (id == GDT2_ID) /* GDT2000 */
  481. return 1;
  482. }
  483. return 0;
  484. }
  485. #endif /* CONFIG_ISA */
  486. #ifdef CONFIG_PCI
  487. static bool gdth_search_vortex(u16 device)
  488. {
  489. if (device <= PCI_DEVICE_ID_VORTEX_GDT6555)
  490. return true;
  491. if (device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP &&
  492. device <= PCI_DEVICE_ID_VORTEX_GDTMAXRP)
  493. return true;
  494. if (device == PCI_DEVICE_ID_VORTEX_GDTNEWRX ||
  495. device == PCI_DEVICE_ID_VORTEX_GDTNEWRX2)
  496. return true;
  497. return false;
  498. }
  499. static int gdth_pci_probe_one(gdth_pci_str *pcistr, gdth_ha_str **ha_out);
  500. static int gdth_pci_init_one(struct pci_dev *pdev,
  501. const struct pci_device_id *ent);
  502. static void gdth_pci_remove_one(struct pci_dev *pdev);
  503. static void gdth_remove_one(gdth_ha_str *ha);
  504. /* Vortex only makes RAID controllers.
  505. * We do not really want to specify all 550 ids here, so wildcard match.
  506. */
  507. static const struct pci_device_id gdthtable[] = {
  508. { PCI_VDEVICE(VORTEX, PCI_ANY_ID) },
  509. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SRC) },
  510. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SRC_XSCALE) },
  511. { } /* terminate list */
  512. };
  513. MODULE_DEVICE_TABLE(pci, gdthtable);
  514. static struct pci_driver gdth_pci_driver = {
  515. .name = "gdth",
  516. .id_table = gdthtable,
  517. .probe = gdth_pci_init_one,
  518. .remove = gdth_pci_remove_one,
  519. };
  520. static void gdth_pci_remove_one(struct pci_dev *pdev)
  521. {
  522. gdth_ha_str *ha = pci_get_drvdata(pdev);
  523. list_del(&ha->list);
  524. gdth_remove_one(ha);
  525. pci_disable_device(pdev);
  526. }
  527. static int gdth_pci_init_one(struct pci_dev *pdev,
  528. const struct pci_device_id *ent)
  529. {
  530. u16 vendor = pdev->vendor;
  531. u16 device = pdev->device;
  532. unsigned long base0, base1, base2;
  533. int rc;
  534. gdth_pci_str gdth_pcistr;
  535. gdth_ha_str *ha = NULL;
  536. TRACE(("gdth_search_dev() cnt %d vendor %x device %x\n",
  537. gdth_ctr_count, vendor, device));
  538. memset(&gdth_pcistr, 0, sizeof(gdth_pcistr));
  539. if (vendor == PCI_VENDOR_ID_VORTEX && !gdth_search_vortex(device))
  540. return -ENODEV;
  541. rc = pci_enable_device(pdev);
  542. if (rc)
  543. return rc;
  544. if (gdth_ctr_count >= MAXHA)
  545. return -EBUSY;
  546. /* GDT PCI controller found, resources are already in pdev */
  547. gdth_pcistr.pdev = pdev;
  548. base0 = pci_resource_flags(pdev, 0);
  549. base1 = pci_resource_flags(pdev, 1);
  550. base2 = pci_resource_flags(pdev, 2);
  551. if (device <= PCI_DEVICE_ID_VORTEX_GDT6000B || /* GDT6000/B */
  552. device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP) { /* MPR */
  553. if (!(base0 & IORESOURCE_MEM))
  554. return -ENODEV;
  555. gdth_pcistr.dpmem = pci_resource_start(pdev, 0);
  556. } else { /* GDT6110, GDT6120, .. */
  557. if (!(base0 & IORESOURCE_MEM) ||
  558. !(base2 & IORESOURCE_MEM) ||
  559. !(base1 & IORESOURCE_IO))
  560. return -ENODEV;
  561. gdth_pcistr.dpmem = pci_resource_start(pdev, 2);
  562. gdth_pcistr.io = pci_resource_start(pdev, 1);
  563. }
  564. TRACE2(("Controller found at %d/%d, irq %d, dpmem 0x%lx\n",
  565. gdth_pcistr.pdev->bus->number,
  566. PCI_SLOT(gdth_pcistr.pdev->devfn),
  567. gdth_pcistr.irq,
  568. gdth_pcistr.dpmem));
  569. rc = gdth_pci_probe_one(&gdth_pcistr, &ha);
  570. if (rc)
  571. return rc;
  572. return 0;
  573. }
  574. #endif /* CONFIG_PCI */
  575. #ifdef CONFIG_EISA
  576. static int __init gdth_init_eisa(u16 eisa_adr,gdth_ha_str *ha)
  577. {
  578. u32 retries,id;
  579. u8 prot_ver,eisacf,i,irq_found;
  580. TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr));
  581. /* disable board interrupts, deinitialize services */
  582. outb(0xff,eisa_adr+EDOORREG);
  583. outb(0x00,eisa_adr+EDENABREG);
  584. outb(0x00,eisa_adr+EINTENABREG);
  585. outb(0xff,eisa_adr+LDOORREG);
  586. retries = INIT_RETRIES;
  587. gdth_delay(20);
  588. while (inb(eisa_adr+EDOORREG) != 0xff) {
  589. if (--retries == 0) {
  590. printk("GDT-EISA: Initialization error (DEINIT failed)\n");
  591. return 0;
  592. }
  593. gdth_delay(1);
  594. TRACE2(("wait for DEINIT: retries=%d\n",retries));
  595. }
  596. prot_ver = inb(eisa_adr+MAILBOXREG);
  597. outb(0xff,eisa_adr+EDOORREG);
  598. if (prot_ver != PROTOCOL_VERSION) {
  599. printk("GDT-EISA: Illegal protocol version\n");
  600. return 0;
  601. }
  602. ha->bmic = eisa_adr;
  603. ha->brd_phys = (u32)eisa_adr >> 12;
  604. outl(0,eisa_adr+MAILBOXREG);
  605. outl(0,eisa_adr+MAILBOXREG+4);
  606. outl(0,eisa_adr+MAILBOXREG+8);
  607. outl(0,eisa_adr+MAILBOXREG+12);
  608. /* detect IRQ */
  609. if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) {
  610. ha->oem_id = OEM_ID_ICP;
  611. ha->type = GDT_EISA;
  612. ha->stype = id;
  613. outl(1,eisa_adr+MAILBOXREG+8);
  614. outb(0xfe,eisa_adr+LDOORREG);
  615. retries = INIT_RETRIES;
  616. gdth_delay(20);
  617. while (inb(eisa_adr+EDOORREG) != 0xfe) {
  618. if (--retries == 0) {
  619. printk("GDT-EISA: Initialization error (get IRQ failed)\n");
  620. return 0;
  621. }
  622. gdth_delay(1);
  623. }
  624. ha->irq = inb(eisa_adr+MAILBOXREG);
  625. outb(0xff,eisa_adr+EDOORREG);
  626. TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq));
  627. /* check the result */
  628. if (ha->irq == 0) {
  629. TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n"));
  630. for (i = 0, irq_found = FALSE;
  631. i < MAXHA && irq[i] != 0xff; ++i) {
  632. if (irq[i]==10 || irq[i]==11 || irq[i]==12 || irq[i]==14) {
  633. irq_found = TRUE;
  634. break;
  635. }
  636. }
  637. if (irq_found) {
  638. ha->irq = irq[i];
  639. irq[i] = 0;
  640. printk("GDT-EISA: Can not detect controller IRQ,\n");
  641. printk("Use IRQ setting from command line (IRQ = %d)\n",
  642. ha->irq);
  643. } else {
  644. printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n");
  645. printk("the controller BIOS or use command line parameters\n");
  646. return 0;
  647. }
  648. }
  649. } else {
  650. eisacf = inb(eisa_adr+EISAREG) & 7;
  651. if (eisacf > 4) /* level triggered */
  652. eisacf -= 4;
  653. ha->irq = gdth_irq_tab[eisacf];
  654. ha->oem_id = OEM_ID_ICP;
  655. ha->type = GDT_EISA;
  656. ha->stype = id;
  657. }
  658. ha->dma64_support = 0;
  659. return 1;
  660. }
  661. #endif /* CONFIG_EISA */
  662. #ifdef CONFIG_ISA
  663. static int __init gdth_init_isa(u32 bios_adr,gdth_ha_str *ha)
  664. {
  665. register gdt2_dpram_str __iomem *dp2_ptr;
  666. int i;
  667. u8 irq_drq,prot_ver;
  668. u32 retries;
  669. TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr));
  670. ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str));
  671. if (ha->brd == NULL) {
  672. printk("GDT-ISA: Initialization error (DPMEM remap error)\n");
  673. return 0;
  674. }
  675. dp2_ptr = ha->brd;
  676. writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */
  677. /* reset interface area */
  678. memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u));
  679. if (readl(&dp2_ptr->u) != 0) {
  680. printk("GDT-ISA: Initialization error (DPMEM write error)\n");
  681. iounmap(ha->brd);
  682. return 0;
  683. }
  684. /* disable board interrupts, read DRQ and IRQ */
  685. writeb(0xff, &dp2_ptr->io.irqdel);
  686. writeb(0x00, &dp2_ptr->io.irqen);
  687. writeb(0x00, &dp2_ptr->u.ic.S_Status);
  688. writeb(0x00, &dp2_ptr->u.ic.Cmd_Index);
  689. irq_drq = readb(&dp2_ptr->io.rq);
  690. for (i=0; i<3; ++i) {
  691. if ((irq_drq & 1)==0)
  692. break;
  693. irq_drq >>= 1;
  694. }
  695. ha->drq = gdth_drq_tab[i];
  696. irq_drq = readb(&dp2_ptr->io.rq) >> 3;
  697. for (i=1; i<5; ++i) {
  698. if ((irq_drq & 1)==0)
  699. break;
  700. irq_drq >>= 1;
  701. }
  702. ha->irq = gdth_irq_tab[i];
  703. /* deinitialize services */
  704. writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]);
  705. writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx);
  706. writeb(0, &dp2_ptr->io.event);
  707. retries = INIT_RETRIES;
  708. gdth_delay(20);
  709. while (readb(&dp2_ptr->u.ic.S_Status) != 0xff) {
  710. if (--retries == 0) {
  711. printk("GDT-ISA: Initialization error (DEINIT failed)\n");
  712. iounmap(ha->brd);
  713. return 0;
  714. }
  715. gdth_delay(1);
  716. }
  717. prot_ver = (u8)readl(&dp2_ptr->u.ic.S_Info[0]);
  718. writeb(0, &dp2_ptr->u.ic.Status);
  719. writeb(0xff, &dp2_ptr->io.irqdel);
  720. if (prot_ver != PROTOCOL_VERSION) {
  721. printk("GDT-ISA: Illegal protocol version\n");
  722. iounmap(ha->brd);
  723. return 0;
  724. }
  725. ha->oem_id = OEM_ID_ICP;
  726. ha->type = GDT_ISA;
  727. ha->ic_all_size = sizeof(dp2_ptr->u);
  728. ha->stype= GDT2_ID;
  729. ha->brd_phys = bios_adr >> 4;
  730. /* special request to controller BIOS */
  731. writel(0x00, &dp2_ptr->u.ic.S_Info[0]);
  732. writel(0x00, &dp2_ptr->u.ic.S_Info[1]);
  733. writel(0x01, &dp2_ptr->u.ic.S_Info[2]);
  734. writel(0x00, &dp2_ptr->u.ic.S_Info[3]);
  735. writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx);
  736. writeb(0, &dp2_ptr->io.event);
  737. retries = INIT_RETRIES;
  738. gdth_delay(20);
  739. while (readb(&dp2_ptr->u.ic.S_Status) != 0xfe) {
  740. if (--retries == 0) {
  741. printk("GDT-ISA: Initialization error\n");
  742. iounmap(ha->brd);
  743. return 0;
  744. }
  745. gdth_delay(1);
  746. }
  747. writeb(0, &dp2_ptr->u.ic.Status);
  748. writeb(0xff, &dp2_ptr->io.irqdel);
  749. ha->dma64_support = 0;
  750. return 1;
  751. }
  752. #endif /* CONFIG_ISA */
  753. #ifdef CONFIG_PCI
  754. static int gdth_init_pci(struct pci_dev *pdev, gdth_pci_str *pcistr,
  755. gdth_ha_str *ha)
  756. {
  757. register gdt6_dpram_str __iomem *dp6_ptr;
  758. register gdt6c_dpram_str __iomem *dp6c_ptr;
  759. register gdt6m_dpram_str __iomem *dp6m_ptr;
  760. u32 retries;
  761. u8 prot_ver;
  762. u16 command;
  763. int i, found = FALSE;
  764. TRACE(("gdth_init_pci()\n"));
  765. if (pdev->vendor == PCI_VENDOR_ID_INTEL)
  766. ha->oem_id = OEM_ID_INTEL;
  767. else
  768. ha->oem_id = OEM_ID_ICP;
  769. ha->brd_phys = (pdev->bus->number << 8) | (pdev->devfn & 0xf8);
  770. ha->stype = (u32)pdev->device;
  771. ha->irq = pdev->irq;
  772. ha->pdev = pdev;
  773. if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6000B) { /* GDT6000/B */
  774. TRACE2(("init_pci() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  775. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6_dpram_str));
  776. if (ha->brd == NULL) {
  777. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  778. return 0;
  779. }
  780. /* check and reset interface area */
  781. dp6_ptr = ha->brd;
  782. writel(DPMEM_MAGIC, &dp6_ptr->u);
  783. if (readl(&dp6_ptr->u) != DPMEM_MAGIC) {
  784. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  785. pcistr->dpmem);
  786. found = FALSE;
  787. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  788. iounmap(ha->brd);
  789. ha->brd = ioremap(i, sizeof(u16));
  790. if (ha->brd == NULL) {
  791. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  792. return 0;
  793. }
  794. if (readw(ha->brd) != 0xffff) {
  795. TRACE2(("init_pci_old() address 0x%x busy\n", i));
  796. continue;
  797. }
  798. iounmap(ha->brd);
  799. pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, i);
  800. ha->brd = ioremap(i, sizeof(gdt6_dpram_str));
  801. if (ha->brd == NULL) {
  802. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  803. return 0;
  804. }
  805. dp6_ptr = ha->brd;
  806. writel(DPMEM_MAGIC, &dp6_ptr->u);
  807. if (readl(&dp6_ptr->u) == DPMEM_MAGIC) {
  808. printk("GDT-PCI: Use free address at 0x%x\n", i);
  809. found = TRUE;
  810. break;
  811. }
  812. }
  813. if (!found) {
  814. printk("GDT-PCI: No free address found!\n");
  815. iounmap(ha->brd);
  816. return 0;
  817. }
  818. }
  819. memset_io(&dp6_ptr->u, 0, sizeof(dp6_ptr->u));
  820. if (readl(&dp6_ptr->u) != 0) {
  821. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  822. iounmap(ha->brd);
  823. return 0;
  824. }
  825. /* disable board interrupts, deinit services */
  826. writeb(0xff, &dp6_ptr->io.irqdel);
  827. writeb(0x00, &dp6_ptr->io.irqen);
  828. writeb(0x00, &dp6_ptr->u.ic.S_Status);
  829. writeb(0x00, &dp6_ptr->u.ic.Cmd_Index);
  830. writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]);
  831. writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx);
  832. writeb(0, &dp6_ptr->io.event);
  833. retries = INIT_RETRIES;
  834. gdth_delay(20);
  835. while (readb(&dp6_ptr->u.ic.S_Status) != 0xff) {
  836. if (--retries == 0) {
  837. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  838. iounmap(ha->brd);
  839. return 0;
  840. }
  841. gdth_delay(1);
  842. }
  843. prot_ver = (u8)readl(&dp6_ptr->u.ic.S_Info[0]);
  844. writeb(0, &dp6_ptr->u.ic.S_Status);
  845. writeb(0xff, &dp6_ptr->io.irqdel);
  846. if (prot_ver != PROTOCOL_VERSION) {
  847. printk("GDT-PCI: Illegal protocol version\n");
  848. iounmap(ha->brd);
  849. return 0;
  850. }
  851. ha->type = GDT_PCI;
  852. ha->ic_all_size = sizeof(dp6_ptr->u);
  853. /* special command to controller BIOS */
  854. writel(0x00, &dp6_ptr->u.ic.S_Info[0]);
  855. writel(0x00, &dp6_ptr->u.ic.S_Info[1]);
  856. writel(0x00, &dp6_ptr->u.ic.S_Info[2]);
  857. writel(0x00, &dp6_ptr->u.ic.S_Info[3]);
  858. writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx);
  859. writeb(0, &dp6_ptr->io.event);
  860. retries = INIT_RETRIES;
  861. gdth_delay(20);
  862. while (readb(&dp6_ptr->u.ic.S_Status) != 0xfe) {
  863. if (--retries == 0) {
  864. printk("GDT-PCI: Initialization error\n");
  865. iounmap(ha->brd);
  866. return 0;
  867. }
  868. gdth_delay(1);
  869. }
  870. writeb(0, &dp6_ptr->u.ic.S_Status);
  871. writeb(0xff, &dp6_ptr->io.irqdel);
  872. ha->dma64_support = 0;
  873. } else if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6555) { /* GDT6110, ... */
  874. ha->plx = (gdt6c_plx_regs *)pcistr->io;
  875. TRACE2(("init_pci_new() dpmem %lx irq %d\n",
  876. pcistr->dpmem,ha->irq));
  877. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6c_dpram_str));
  878. if (ha->brd == NULL) {
  879. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  880. iounmap(ha->brd);
  881. return 0;
  882. }
  883. /* check and reset interface area */
  884. dp6c_ptr = ha->brd;
  885. writel(DPMEM_MAGIC, &dp6c_ptr->u);
  886. if (readl(&dp6c_ptr->u) != DPMEM_MAGIC) {
  887. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  888. pcistr->dpmem);
  889. found = FALSE;
  890. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  891. iounmap(ha->brd);
  892. ha->brd = ioremap(i, sizeof(u16));
  893. if (ha->brd == NULL) {
  894. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  895. return 0;
  896. }
  897. if (readw(ha->brd) != 0xffff) {
  898. TRACE2(("init_pci_plx() address 0x%x busy\n", i));
  899. continue;
  900. }
  901. iounmap(ha->brd);
  902. pci_write_config_dword(pdev, PCI_BASE_ADDRESS_2, i);
  903. ha->brd = ioremap(i, sizeof(gdt6c_dpram_str));
  904. if (ha->brd == NULL) {
  905. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  906. return 0;
  907. }
  908. dp6c_ptr = ha->brd;
  909. writel(DPMEM_MAGIC, &dp6c_ptr->u);
  910. if (readl(&dp6c_ptr->u) == DPMEM_MAGIC) {
  911. printk("GDT-PCI: Use free address at 0x%x\n", i);
  912. found = TRUE;
  913. break;
  914. }
  915. }
  916. if (!found) {
  917. printk("GDT-PCI: No free address found!\n");
  918. iounmap(ha->brd);
  919. return 0;
  920. }
  921. }
  922. memset_io(&dp6c_ptr->u, 0, sizeof(dp6c_ptr->u));
  923. if (readl(&dp6c_ptr->u) != 0) {
  924. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  925. iounmap(ha->brd);
  926. return 0;
  927. }
  928. /* disable board interrupts, deinit services */
  929. outb(0x00,PTR2USHORT(&ha->plx->control1));
  930. outb(0xff,PTR2USHORT(&ha->plx->edoor_reg));
  931. writeb(0x00, &dp6c_ptr->u.ic.S_Status);
  932. writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index);
  933. writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]);
  934. writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx);
  935. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  936. retries = INIT_RETRIES;
  937. gdth_delay(20);
  938. while (readb(&dp6c_ptr->u.ic.S_Status) != 0xff) {
  939. if (--retries == 0) {
  940. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  941. iounmap(ha->brd);
  942. return 0;
  943. }
  944. gdth_delay(1);
  945. }
  946. prot_ver = (u8)readl(&dp6c_ptr->u.ic.S_Info[0]);
  947. writeb(0, &dp6c_ptr->u.ic.Status);
  948. if (prot_ver != PROTOCOL_VERSION) {
  949. printk("GDT-PCI: Illegal protocol version\n");
  950. iounmap(ha->brd);
  951. return 0;
  952. }
  953. ha->type = GDT_PCINEW;
  954. ha->ic_all_size = sizeof(dp6c_ptr->u);
  955. /* special command to controller BIOS */
  956. writel(0x00, &dp6c_ptr->u.ic.S_Info[0]);
  957. writel(0x00, &dp6c_ptr->u.ic.S_Info[1]);
  958. writel(0x00, &dp6c_ptr->u.ic.S_Info[2]);
  959. writel(0x00, &dp6c_ptr->u.ic.S_Info[3]);
  960. writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx);
  961. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  962. retries = INIT_RETRIES;
  963. gdth_delay(20);
  964. while (readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) {
  965. if (--retries == 0) {
  966. printk("GDT-PCI: Initialization error\n");
  967. iounmap(ha->brd);
  968. return 0;
  969. }
  970. gdth_delay(1);
  971. }
  972. writeb(0, &dp6c_ptr->u.ic.S_Status);
  973. ha->dma64_support = 0;
  974. } else { /* MPR */
  975. TRACE2(("init_pci_mpr() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  976. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6m_dpram_str));
  977. if (ha->brd == NULL) {
  978. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  979. return 0;
  980. }
  981. /* manipulate config. space to enable DPMEM, start RP controller */
  982. pci_read_config_word(pdev, PCI_COMMAND, &command);
  983. command |= 6;
  984. pci_write_config_word(pdev, PCI_COMMAND, command);
  985. gdth_delay(1);
  986. dp6m_ptr = ha->brd;
  987. /* Ensure that it is safe to access the non HW portions of DPMEM.
  988. * Aditional check needed for Xscale based RAID controllers */
  989. while( ((int)readb(&dp6m_ptr->i960r.sema0_reg) ) & 3 )
  990. gdth_delay(1);
  991. /* check and reset interface area */
  992. writel(DPMEM_MAGIC, &dp6m_ptr->u);
  993. if (readl(&dp6m_ptr->u) != DPMEM_MAGIC) {
  994. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  995. pcistr->dpmem);
  996. found = FALSE;
  997. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  998. iounmap(ha->brd);
  999. ha->brd = ioremap(i, sizeof(u16));
  1000. if (ha->brd == NULL) {
  1001. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1002. return 0;
  1003. }
  1004. if (readw(ha->brd) != 0xffff) {
  1005. TRACE2(("init_pci_mpr() address 0x%x busy\n", i));
  1006. continue;
  1007. }
  1008. iounmap(ha->brd);
  1009. pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, i);
  1010. ha->brd = ioremap(i, sizeof(gdt6m_dpram_str));
  1011. if (ha->brd == NULL) {
  1012. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1013. return 0;
  1014. }
  1015. dp6m_ptr = ha->brd;
  1016. writel(DPMEM_MAGIC, &dp6m_ptr->u);
  1017. if (readl(&dp6m_ptr->u) == DPMEM_MAGIC) {
  1018. printk("GDT-PCI: Use free address at 0x%x\n", i);
  1019. found = TRUE;
  1020. break;
  1021. }
  1022. }
  1023. if (!found) {
  1024. printk("GDT-PCI: No free address found!\n");
  1025. iounmap(ha->brd);
  1026. return 0;
  1027. }
  1028. }
  1029. memset_io(&dp6m_ptr->u, 0, sizeof(dp6m_ptr->u));
  1030. /* disable board interrupts, deinit services */
  1031. writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) | 4,
  1032. &dp6m_ptr->i960r.edoor_en_reg);
  1033. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1034. writeb(0x00, &dp6m_ptr->u.ic.S_Status);
  1035. writeb(0x00, &dp6m_ptr->u.ic.Cmd_Index);
  1036. writel(pcistr->dpmem, &dp6m_ptr->u.ic.S_Info[0]);
  1037. writeb(0xff, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1038. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1039. retries = INIT_RETRIES;
  1040. gdth_delay(20);
  1041. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xff) {
  1042. if (--retries == 0) {
  1043. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1044. iounmap(ha->brd);
  1045. return 0;
  1046. }
  1047. gdth_delay(1);
  1048. }
  1049. prot_ver = (u8)readl(&dp6m_ptr->u.ic.S_Info[0]);
  1050. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1051. if (prot_ver != PROTOCOL_VERSION) {
  1052. printk("GDT-PCI: Illegal protocol version\n");
  1053. iounmap(ha->brd);
  1054. return 0;
  1055. }
  1056. ha->type = GDT_PCIMPR;
  1057. ha->ic_all_size = sizeof(dp6m_ptr->u);
  1058. /* special command to controller BIOS */
  1059. writel(0x00, &dp6m_ptr->u.ic.S_Info[0]);
  1060. writel(0x00, &dp6m_ptr->u.ic.S_Info[1]);
  1061. writel(0x00, &dp6m_ptr->u.ic.S_Info[2]);
  1062. writel(0x00, &dp6m_ptr->u.ic.S_Info[3]);
  1063. writeb(0xfe, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1064. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1065. retries = INIT_RETRIES;
  1066. gdth_delay(20);
  1067. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfe) {
  1068. if (--retries == 0) {
  1069. printk("GDT-PCI: Initialization error\n");
  1070. iounmap(ha->brd);
  1071. return 0;
  1072. }
  1073. gdth_delay(1);
  1074. }
  1075. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1076. /* read FW version to detect 64-bit DMA support */
  1077. writeb(0xfd, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1078. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1079. retries = INIT_RETRIES;
  1080. gdth_delay(20);
  1081. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfd) {
  1082. if (--retries == 0) {
  1083. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1084. iounmap(ha->brd);
  1085. return 0;
  1086. }
  1087. gdth_delay(1);
  1088. }
  1089. prot_ver = (u8)(readl(&dp6m_ptr->u.ic.S_Info[0]) >> 16);
  1090. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1091. if (prot_ver < 0x2b) /* FW < x.43: no 64-bit DMA support */
  1092. ha->dma64_support = 0;
  1093. else
  1094. ha->dma64_support = 1;
  1095. }
  1096. return 1;
  1097. }
  1098. #endif /* CONFIG_PCI */
  1099. /* controller protocol functions */
  1100. static void gdth_enable_int(gdth_ha_str *ha)
  1101. {
  1102. unsigned long flags;
  1103. gdt2_dpram_str __iomem *dp2_ptr;
  1104. gdt6_dpram_str __iomem *dp6_ptr;
  1105. gdt6m_dpram_str __iomem *dp6m_ptr;
  1106. TRACE(("gdth_enable_int() hanum %d\n",ha->hanum));
  1107. spin_lock_irqsave(&ha->smp_lock, flags);
  1108. if (ha->type == GDT_EISA) {
  1109. outb(0xff, ha->bmic + EDOORREG);
  1110. outb(0xff, ha->bmic + EDENABREG);
  1111. outb(0x01, ha->bmic + EINTENABREG);
  1112. } else if (ha->type == GDT_ISA) {
  1113. dp2_ptr = ha->brd;
  1114. writeb(1, &dp2_ptr->io.irqdel);
  1115. writeb(0, &dp2_ptr->u.ic.Cmd_Index);
  1116. writeb(1, &dp2_ptr->io.irqen);
  1117. } else if (ha->type == GDT_PCI) {
  1118. dp6_ptr = ha->brd;
  1119. writeb(1, &dp6_ptr->io.irqdel);
  1120. writeb(0, &dp6_ptr->u.ic.Cmd_Index);
  1121. writeb(1, &dp6_ptr->io.irqen);
  1122. } else if (ha->type == GDT_PCINEW) {
  1123. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  1124. outb(0x03, PTR2USHORT(&ha->plx->control1));
  1125. } else if (ha->type == GDT_PCIMPR) {
  1126. dp6m_ptr = ha->brd;
  1127. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1128. writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) & ~4,
  1129. &dp6m_ptr->i960r.edoor_en_reg);
  1130. }
  1131. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1132. }
  1133. /* return IStatus if interrupt was from this card else 0 */
  1134. static u8 gdth_get_status(gdth_ha_str *ha)
  1135. {
  1136. u8 IStatus = 0;
  1137. TRACE(("gdth_get_status() irq %d ctr_count %d\n", ha->irq, gdth_ctr_count));
  1138. if (ha->type == GDT_EISA)
  1139. IStatus = inb((u16)ha->bmic + EDOORREG);
  1140. else if (ha->type == GDT_ISA)
  1141. IStatus =
  1142. readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1143. else if (ha->type == GDT_PCI)
  1144. IStatus =
  1145. readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1146. else if (ha->type == GDT_PCINEW)
  1147. IStatus = inb(PTR2USHORT(&ha->plx->edoor_reg));
  1148. else if (ha->type == GDT_PCIMPR)
  1149. IStatus =
  1150. readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.edoor_reg);
  1151. return IStatus;
  1152. }
  1153. static int gdth_test_busy(gdth_ha_str *ha)
  1154. {
  1155. register int gdtsema0 = 0;
  1156. TRACE(("gdth_test_busy() hanum %d\n", ha->hanum));
  1157. if (ha->type == GDT_EISA)
  1158. gdtsema0 = (int)inb(ha->bmic + SEMA0REG);
  1159. else if (ha->type == GDT_ISA)
  1160. gdtsema0 = (int)readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1161. else if (ha->type == GDT_PCI)
  1162. gdtsema0 = (int)readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1163. else if (ha->type == GDT_PCINEW)
  1164. gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg));
  1165. else if (ha->type == GDT_PCIMPR)
  1166. gdtsema0 =
  1167. (int)readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1168. return (gdtsema0 & 1);
  1169. }
  1170. static int gdth_get_cmd_index(gdth_ha_str *ha)
  1171. {
  1172. int i;
  1173. TRACE(("gdth_get_cmd_index() hanum %d\n", ha->hanum));
  1174. for (i=0; i<GDTH_MAXCMDS; ++i) {
  1175. if (ha->cmd_tab[i].cmnd == UNUSED_CMND) {
  1176. ha->cmd_tab[i].cmnd = ha->pccb->RequestBuffer;
  1177. ha->cmd_tab[i].service = ha->pccb->Service;
  1178. ha->pccb->CommandIndex = (u32)i+2;
  1179. return (i+2);
  1180. }
  1181. }
  1182. return 0;
  1183. }
  1184. static void gdth_set_sema0(gdth_ha_str *ha)
  1185. {
  1186. TRACE(("gdth_set_sema0() hanum %d\n", ha->hanum));
  1187. if (ha->type == GDT_EISA) {
  1188. outb(1, ha->bmic + SEMA0REG);
  1189. } else if (ha->type == GDT_ISA) {
  1190. writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1191. } else if (ha->type == GDT_PCI) {
  1192. writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1193. } else if (ha->type == GDT_PCINEW) {
  1194. outb(1, PTR2USHORT(&ha->plx->sema0_reg));
  1195. } else if (ha->type == GDT_PCIMPR) {
  1196. writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1197. }
  1198. }
  1199. static void gdth_copy_command(gdth_ha_str *ha)
  1200. {
  1201. register gdth_cmd_str *cmd_ptr;
  1202. register gdt6m_dpram_str __iomem *dp6m_ptr;
  1203. register gdt6c_dpram_str __iomem *dp6c_ptr;
  1204. gdt6_dpram_str __iomem *dp6_ptr;
  1205. gdt2_dpram_str __iomem *dp2_ptr;
  1206. u16 cp_count,dp_offset,cmd_no;
  1207. TRACE(("gdth_copy_command() hanum %d\n", ha->hanum));
  1208. cp_count = ha->cmd_len;
  1209. dp_offset= ha->cmd_offs_dpmem;
  1210. cmd_no = ha->cmd_cnt;
  1211. cmd_ptr = ha->pccb;
  1212. ++ha->cmd_cnt;
  1213. if (ha->type == GDT_EISA)
  1214. return; /* no DPMEM, no copy */
  1215. /* set cpcount dword aligned */
  1216. if (cp_count & 3)
  1217. cp_count += (4 - (cp_count & 3));
  1218. ha->cmd_offs_dpmem += cp_count;
  1219. /* set offset and service, copy command to DPMEM */
  1220. if (ha->type == GDT_ISA) {
  1221. dp2_ptr = ha->brd;
  1222. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1223. &dp2_ptr->u.ic.comm_queue[cmd_no].offset);
  1224. writew((u16)cmd_ptr->Service,
  1225. &dp2_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1226. memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1227. } else if (ha->type == GDT_PCI) {
  1228. dp6_ptr = ha->brd;
  1229. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1230. &dp6_ptr->u.ic.comm_queue[cmd_no].offset);
  1231. writew((u16)cmd_ptr->Service,
  1232. &dp6_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1233. memcpy_toio(&dp6_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1234. } else if (ha->type == GDT_PCINEW) {
  1235. dp6c_ptr = ha->brd;
  1236. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1237. &dp6c_ptr->u.ic.comm_queue[cmd_no].offset);
  1238. writew((u16)cmd_ptr->Service,
  1239. &dp6c_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1240. memcpy_toio(&dp6c_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1241. } else if (ha->type == GDT_PCIMPR) {
  1242. dp6m_ptr = ha->brd;
  1243. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1244. &dp6m_ptr->u.ic.comm_queue[cmd_no].offset);
  1245. writew((u16)cmd_ptr->Service,
  1246. &dp6m_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1247. memcpy_toio(&dp6m_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1248. }
  1249. }
  1250. static void gdth_release_event(gdth_ha_str *ha)
  1251. {
  1252. TRACE(("gdth_release_event() hanum %d\n", ha->hanum));
  1253. #ifdef GDTH_STATISTICS
  1254. {
  1255. u32 i,j;
  1256. for (i=0,j=0; j<GDTH_MAXCMDS; ++j) {
  1257. if (ha->cmd_tab[j].cmnd != UNUSED_CMND)
  1258. ++i;
  1259. }
  1260. if (max_index < i) {
  1261. max_index = i;
  1262. TRACE3(("GDT: max_index = %d\n",(u16)i));
  1263. }
  1264. }
  1265. #endif
  1266. if (ha->pccb->OpCode == GDT_INIT)
  1267. ha->pccb->Service |= 0x80;
  1268. if (ha->type == GDT_EISA) {
  1269. if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */
  1270. outl(ha->ccb_phys, ha->bmic + MAILBOXREG);
  1271. outb(ha->pccb->Service, ha->bmic + LDOORREG);
  1272. } else if (ha->type == GDT_ISA) {
  1273. writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event);
  1274. } else if (ha->type == GDT_PCI) {
  1275. writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event);
  1276. } else if (ha->type == GDT_PCINEW) {
  1277. outb(1, PTR2USHORT(&ha->plx->ldoor_reg));
  1278. } else if (ha->type == GDT_PCIMPR) {
  1279. writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.ldoor_reg);
  1280. }
  1281. }
  1282. static int gdth_wait(gdth_ha_str *ha, int index, u32 time)
  1283. {
  1284. int answer_found = FALSE;
  1285. int wait_index = 0;
  1286. TRACE(("gdth_wait() hanum %d index %d time %d\n", ha->hanum, index, time));
  1287. if (index == 0)
  1288. return 1; /* no wait required */
  1289. do {
  1290. __gdth_interrupt(ha, true, &wait_index);
  1291. if (wait_index == index) {
  1292. answer_found = TRUE;
  1293. break;
  1294. }
  1295. gdth_delay(1);
  1296. } while (--time);
  1297. while (gdth_test_busy(ha))
  1298. gdth_delay(0);
  1299. return (answer_found);
  1300. }
  1301. static int gdth_internal_cmd(gdth_ha_str *ha, u8 service, u16 opcode,
  1302. u32 p1, u64 p2, u64 p3)
  1303. {
  1304. register gdth_cmd_str *cmd_ptr;
  1305. int retries,index;
  1306. TRACE2(("gdth_internal_cmd() service %d opcode %d\n",service,opcode));
  1307. cmd_ptr = ha->pccb;
  1308. memset((char*)cmd_ptr,0,sizeof(gdth_cmd_str));
  1309. /* make command */
  1310. for (retries = INIT_RETRIES;;) {
  1311. cmd_ptr->Service = service;
  1312. cmd_ptr->RequestBuffer = INTERNAL_CMND;
  1313. if (!(index=gdth_get_cmd_index(ha))) {
  1314. TRACE(("GDT: No free command index found\n"));
  1315. return 0;
  1316. }
  1317. gdth_set_sema0(ha);
  1318. cmd_ptr->OpCode = opcode;
  1319. cmd_ptr->BoardNode = LOCALBOARD;
  1320. if (service == CACHESERVICE) {
  1321. if (opcode == GDT_IOCTL) {
  1322. cmd_ptr->u.ioctl.subfunc = p1;
  1323. cmd_ptr->u.ioctl.channel = (u32)p2;
  1324. cmd_ptr->u.ioctl.param_size = (u16)p3;
  1325. cmd_ptr->u.ioctl.p_param = ha->scratch_phys;
  1326. } else {
  1327. if (ha->cache_feat & GDT_64BIT) {
  1328. cmd_ptr->u.cache64.DeviceNo = (u16)p1;
  1329. cmd_ptr->u.cache64.BlockNo = p2;
  1330. } else {
  1331. cmd_ptr->u.cache.DeviceNo = (u16)p1;
  1332. cmd_ptr->u.cache.BlockNo = (u32)p2;
  1333. }
  1334. }
  1335. } else if (service == SCSIRAWSERVICE) {
  1336. if (ha->raw_feat & GDT_64BIT) {
  1337. cmd_ptr->u.raw64.direction = p1;
  1338. cmd_ptr->u.raw64.bus = (u8)p2;
  1339. cmd_ptr->u.raw64.target = (u8)p3;
  1340. cmd_ptr->u.raw64.lun = (u8)(p3 >> 8);
  1341. } else {
  1342. cmd_ptr->u.raw.direction = p1;
  1343. cmd_ptr->u.raw.bus = (u8)p2;
  1344. cmd_ptr->u.raw.target = (u8)p3;
  1345. cmd_ptr->u.raw.lun = (u8)(p3 >> 8);
  1346. }
  1347. } else if (service == SCREENSERVICE) {
  1348. if (opcode == GDT_REALTIME) {
  1349. *(u32 *)&cmd_ptr->u.screen.su.data[0] = p1;
  1350. *(u32 *)&cmd_ptr->u.screen.su.data[4] = (u32)p2;
  1351. *(u32 *)&cmd_ptr->u.screen.su.data[8] = (u32)p3;
  1352. }
  1353. }
  1354. ha->cmd_len = sizeof(gdth_cmd_str);
  1355. ha->cmd_offs_dpmem = 0;
  1356. ha->cmd_cnt = 0;
  1357. gdth_copy_command(ha);
  1358. gdth_release_event(ha);
  1359. gdth_delay(20);
  1360. if (!gdth_wait(ha, index, INIT_TIMEOUT)) {
  1361. printk("GDT: Initialization error (timeout service %d)\n",service);
  1362. return 0;
  1363. }
  1364. if (ha->status != S_BSY || --retries == 0)
  1365. break;
  1366. gdth_delay(1);
  1367. }
  1368. return (ha->status != S_OK ? 0:1);
  1369. }
  1370. /* search for devices */
  1371. static int gdth_search_drives(gdth_ha_str *ha)
  1372. {
  1373. u16 cdev_cnt, i;
  1374. int ok;
  1375. u32 bus_no, drv_cnt, drv_no, j;
  1376. gdth_getch_str *chn;
  1377. gdth_drlist_str *drl;
  1378. gdth_iochan_str *ioc;
  1379. gdth_raw_iochan_str *iocr;
  1380. gdth_arcdl_str *alst;
  1381. gdth_alist_str *alst2;
  1382. gdth_oem_str_ioctl *oemstr;
  1383. #ifdef INT_COAL
  1384. gdth_perf_modes *pmod;
  1385. #endif
  1386. #ifdef GDTH_RTC
  1387. u8 rtc[12];
  1388. unsigned long flags;
  1389. #endif
  1390. TRACE(("gdth_search_drives() hanum %d\n", ha->hanum));
  1391. ok = 0;
  1392. /* initialize controller services, at first: screen service */
  1393. ha->screen_feat = 0;
  1394. if (!force_dma32) {
  1395. ok = gdth_internal_cmd(ha, SCREENSERVICE, GDT_X_INIT_SCR, 0, 0, 0);
  1396. if (ok)
  1397. ha->screen_feat = GDT_64BIT;
  1398. }
  1399. if (force_dma32 || (!ok && ha->status == (u16)S_NOFUNC))
  1400. ok = gdth_internal_cmd(ha, SCREENSERVICE, GDT_INIT, 0, 0, 0);
  1401. if (!ok) {
  1402. printk("GDT-HA %d: Initialization error screen service (code %d)\n",
  1403. ha->hanum, ha->status);
  1404. return 0;
  1405. }
  1406. TRACE2(("gdth_search_drives(): SCREENSERVICE initialized\n"));
  1407. #ifdef GDTH_RTC
  1408. /* read realtime clock info, send to controller */
  1409. /* 1. wait for the falling edge of update flag */
  1410. spin_lock_irqsave(&rtc_lock, flags);
  1411. for (j = 0; j < 1000000; ++j)
  1412. if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
  1413. break;
  1414. for (j = 0; j < 1000000; ++j)
  1415. if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
  1416. break;
  1417. /* 2. read info */
  1418. do {
  1419. for (j = 0; j < 12; ++j)
  1420. rtc[j] = CMOS_READ(j);
  1421. } while (rtc[0] != CMOS_READ(0));
  1422. spin_unlock_irqrestore(&rtc_lock, flags);
  1423. TRACE2(("gdth_search_drives(): RTC: %x/%x/%x\n",*(u32 *)&rtc[0],
  1424. *(u32 *)&rtc[4], *(u32 *)&rtc[8]));
  1425. /* 3. send to controller firmware */
  1426. gdth_internal_cmd(ha, SCREENSERVICE, GDT_REALTIME, *(u32 *)&rtc[0],
  1427. *(u32 *)&rtc[4], *(u32 *)&rtc[8]);
  1428. #endif
  1429. /* unfreeze all IOs */
  1430. gdth_internal_cmd(ha, CACHESERVICE, GDT_UNFREEZE_IO, 0, 0, 0);
  1431. /* initialize cache service */
  1432. ha->cache_feat = 0;
  1433. if (!force_dma32) {
  1434. ok = gdth_internal_cmd(ha, CACHESERVICE, GDT_X_INIT_HOST, LINUX_OS,
  1435. 0, 0);
  1436. if (ok)
  1437. ha->cache_feat = GDT_64BIT;
  1438. }
  1439. if (force_dma32 || (!ok && ha->status == (u16)S_NOFUNC))
  1440. ok = gdth_internal_cmd(ha, CACHESERVICE, GDT_INIT, LINUX_OS, 0, 0);
  1441. if (!ok) {
  1442. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1443. ha->hanum, ha->status);
  1444. return 0;
  1445. }
  1446. TRACE2(("gdth_search_drives(): CACHESERVICE initialized\n"));
  1447. cdev_cnt = (u16)ha->info;
  1448. ha->fw_vers = ha->service;
  1449. #ifdef INT_COAL
  1450. if (ha->type == GDT_PCIMPR) {
  1451. /* set perf. modes */
  1452. pmod = (gdth_perf_modes *)ha->pscratch;
  1453. pmod->version = 1;
  1454. pmod->st_mode = 1; /* enable one status buffer */
  1455. *((u64 *)&pmod->st_buff_addr1) = ha->coal_stat_phys;
  1456. pmod->st_buff_indx1 = COALINDEX;
  1457. pmod->st_buff_addr2 = 0;
  1458. pmod->st_buff_u_addr2 = 0;
  1459. pmod->st_buff_indx2 = 0;
  1460. pmod->st_buff_size = sizeof(gdth_coal_status) * MAXOFFSETS;
  1461. pmod->cmd_mode = 0; // disable all cmd buffers
  1462. pmod->cmd_buff_addr1 = 0;
  1463. pmod->cmd_buff_u_addr1 = 0;
  1464. pmod->cmd_buff_indx1 = 0;
  1465. pmod->cmd_buff_addr2 = 0;
  1466. pmod->cmd_buff_u_addr2 = 0;
  1467. pmod->cmd_buff_indx2 = 0;
  1468. pmod->cmd_buff_size = 0;
  1469. pmod->reserved1 = 0;
  1470. pmod->reserved2 = 0;
  1471. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, SET_PERF_MODES,
  1472. INVALID_CHANNEL,sizeof(gdth_perf_modes))) {
  1473. printk("GDT-HA %d: Interrupt coalescing activated\n", ha->hanum);
  1474. }
  1475. }
  1476. #endif
  1477. /* detect number of buses - try new IOCTL */
  1478. iocr = (gdth_raw_iochan_str *)ha->pscratch;
  1479. iocr->hdr.version = 0xffffffff;
  1480. iocr->hdr.list_entries = MAXBUS;
  1481. iocr->hdr.first_chan = 0;
  1482. iocr->hdr.last_chan = MAXBUS-1;
  1483. iocr->hdr.list_offset = GDTOFFSOF(gdth_raw_iochan_str, list[0]);
  1484. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, IOCHAN_RAW_DESC,
  1485. INVALID_CHANNEL,sizeof(gdth_raw_iochan_str))) {
  1486. TRACE2(("IOCHAN_RAW_DESC supported!\n"));
  1487. ha->bus_cnt = iocr->hdr.chan_count;
  1488. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1489. if (iocr->list[bus_no].proc_id < MAXID)
  1490. ha->bus_id[bus_no] = iocr->list[bus_no].proc_id;
  1491. else
  1492. ha->bus_id[bus_no] = 0xff;
  1493. }
  1494. } else {
  1495. /* old method */
  1496. chn = (gdth_getch_str *)ha->pscratch;
  1497. for (bus_no = 0; bus_no < MAXBUS; ++bus_no) {
  1498. chn->channel_no = bus_no;
  1499. if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1500. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1501. IO_CHANNEL | INVALID_CHANNEL,
  1502. sizeof(gdth_getch_str))) {
  1503. if (bus_no == 0) {
  1504. printk("GDT-HA %d: Error detecting channel count (0x%x)\n",
  1505. ha->hanum, ha->status);
  1506. return 0;
  1507. }
  1508. break;
  1509. }
  1510. if (chn->siop_id < MAXID)
  1511. ha->bus_id[bus_no] = chn->siop_id;
  1512. else
  1513. ha->bus_id[bus_no] = 0xff;
  1514. }
  1515. ha->bus_cnt = (u8)bus_no;
  1516. }
  1517. TRACE2(("gdth_search_drives() %d channels\n",ha->bus_cnt));
  1518. /* read cache configuration */
  1519. if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_INFO,
  1520. INVALID_CHANNEL,sizeof(gdth_cinfo_str))) {
  1521. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1522. ha->hanum, ha->status);
  1523. return 0;
  1524. }
  1525. ha->cpar = ((gdth_cinfo_str *)ha->pscratch)->cpar;
  1526. TRACE2(("gdth_search_drives() cinfo: vs %x sta %d str %d dw %d b %d\n",
  1527. ha->cpar.version,ha->cpar.state,ha->cpar.strategy,
  1528. ha->cpar.write_back,ha->cpar.block_size));
  1529. /* read board info and features */
  1530. ha->more_proc = FALSE;
  1531. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, BOARD_INFO,
  1532. INVALID_CHANNEL,sizeof(gdth_binfo_str))) {
  1533. memcpy(&ha->binfo, (gdth_binfo_str *)ha->pscratch,
  1534. sizeof(gdth_binfo_str));
  1535. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, BOARD_FEATURES,
  1536. INVALID_CHANNEL,sizeof(gdth_bfeat_str))) {
  1537. TRACE2(("BOARD_INFO/BOARD_FEATURES supported\n"));
  1538. ha->bfeat = *(gdth_bfeat_str *)ha->pscratch;
  1539. ha->more_proc = TRUE;
  1540. }
  1541. } else {
  1542. TRACE2(("BOARD_INFO requires firmware >= 1.10/2.08\n"));
  1543. strcpy(ha->binfo.type_string, gdth_ctr_name(ha));
  1544. }
  1545. TRACE2(("Controller name: %s\n",ha->binfo.type_string));
  1546. /* read more informations */
  1547. if (ha->more_proc) {
  1548. /* physical drives, channel addresses */
  1549. ioc = (gdth_iochan_str *)ha->pscratch;
  1550. ioc->hdr.version = 0xffffffff;
  1551. ioc->hdr.list_entries = MAXBUS;
  1552. ioc->hdr.first_chan = 0;
  1553. ioc->hdr.last_chan = MAXBUS-1;
  1554. ioc->hdr.list_offset = GDTOFFSOF(gdth_iochan_str, list[0]);
  1555. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, IOCHAN_DESC,
  1556. INVALID_CHANNEL,sizeof(gdth_iochan_str))) {
  1557. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1558. ha->raw[bus_no].address = ioc->list[bus_no].address;
  1559. ha->raw[bus_no].local_no = ioc->list[bus_no].local_no;
  1560. }
  1561. } else {
  1562. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1563. ha->raw[bus_no].address = IO_CHANNEL;
  1564. ha->raw[bus_no].local_no = bus_no;
  1565. }
  1566. }
  1567. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1568. chn = (gdth_getch_str *)ha->pscratch;
  1569. chn->channel_no = ha->raw[bus_no].local_no;
  1570. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1571. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1572. ha->raw[bus_no].address | INVALID_CHANNEL,
  1573. sizeof(gdth_getch_str))) {
  1574. ha->raw[bus_no].pdev_cnt = chn->drive_cnt;
  1575. TRACE2(("Channel %d: %d phys. drives\n",
  1576. bus_no,chn->drive_cnt));
  1577. }
  1578. if (ha->raw[bus_no].pdev_cnt > 0) {
  1579. drl = (gdth_drlist_str *)ha->pscratch;
  1580. drl->sc_no = ha->raw[bus_no].local_no;
  1581. drl->sc_cnt = ha->raw[bus_no].pdev_cnt;
  1582. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1583. SCSI_DR_LIST | L_CTRL_PATTERN,
  1584. ha->raw[bus_no].address | INVALID_CHANNEL,
  1585. sizeof(gdth_drlist_str))) {
  1586. for (j = 0; j < ha->raw[bus_no].pdev_cnt; ++j)
  1587. ha->raw[bus_no].id_list[j] = drl->sc_list[j];
  1588. } else {
  1589. ha->raw[bus_no].pdev_cnt = 0;
  1590. }
  1591. }
  1592. }
  1593. /* logical drives */
  1594. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_DRV_CNT,
  1595. INVALID_CHANNEL,sizeof(u32))) {
  1596. drv_cnt = *(u32 *)ha->pscratch;
  1597. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_DRV_LIST,
  1598. INVALID_CHANNEL,drv_cnt * sizeof(u32))) {
  1599. for (j = 0; j < drv_cnt; ++j) {
  1600. drv_no = ((u32 *)ha->pscratch)[j];
  1601. if (drv_no < MAX_LDRIVES) {
  1602. ha->hdr[drv_no].is_logdrv = TRUE;
  1603. TRACE2(("Drive %d is log. drive\n",drv_no));
  1604. }
  1605. }
  1606. }
  1607. alst = (gdth_arcdl_str *)ha->pscratch;
  1608. alst->entries_avail = MAX_LDRIVES;
  1609. alst->first_entry = 0;
  1610. alst->list_offset = GDTOFFSOF(gdth_arcdl_str, list[0]);
  1611. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1612. ARRAY_DRV_LIST2 | LA_CTRL_PATTERN,
  1613. INVALID_CHANNEL, sizeof(gdth_arcdl_str) +
  1614. (alst->entries_avail-1) * sizeof(gdth_alist_str))) {
  1615. for (j = 0; j < alst->entries_init; ++j) {
  1616. ha->hdr[j].is_arraydrv = alst->list[j].is_arrayd;
  1617. ha->hdr[j].is_master = alst->list[j].is_master;
  1618. ha->hdr[j].is_parity = alst->list[j].is_parity;
  1619. ha->hdr[j].is_hotfix = alst->list[j].is_hotfix;
  1620. ha->hdr[j].master_no = alst->list[j].cd_handle;
  1621. }
  1622. } else if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1623. ARRAY_DRV_LIST | LA_CTRL_PATTERN,
  1624. 0, 35 * sizeof(gdth_alist_str))) {
  1625. for (j = 0; j < 35; ++j) {
  1626. alst2 = &((gdth_alist_str *)ha->pscratch)[j];
  1627. ha->hdr[j].is_arraydrv = alst2->is_arrayd;
  1628. ha->hdr[j].is_master = alst2->is_master;
  1629. ha->hdr[j].is_parity = alst2->is_parity;
  1630. ha->hdr[j].is_hotfix = alst2->is_hotfix;
  1631. ha->hdr[j].master_no = alst2->cd_handle;
  1632. }
  1633. }
  1634. }
  1635. }
  1636. /* initialize raw service */
  1637. ha->raw_feat = 0;
  1638. if (!force_dma32) {
  1639. ok = gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_X_INIT_RAW, 0, 0, 0);
  1640. if (ok)
  1641. ha->raw_feat = GDT_64BIT;
  1642. }
  1643. if (force_dma32 || (!ok && ha->status == (u16)S_NOFUNC))
  1644. ok = gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_INIT, 0, 0, 0);
  1645. if (!ok) {
  1646. printk("GDT-HA %d: Initialization error raw service (code %d)\n",
  1647. ha->hanum, ha->status);
  1648. return 0;
  1649. }
  1650. TRACE2(("gdth_search_drives(): RAWSERVICE initialized\n"));
  1651. /* set/get features raw service (scatter/gather) */
  1652. if (gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_SET_FEAT, SCATTER_GATHER,
  1653. 0, 0)) {
  1654. TRACE2(("gdth_search_drives(): set features RAWSERVICE OK\n"));
  1655. if (gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_GET_FEAT, 0, 0, 0)) {
  1656. TRACE2(("gdth_search_dr(): get feat RAWSERVICE %d\n",
  1657. ha->info));
  1658. ha->raw_feat |= (u16)ha->info;
  1659. }
  1660. }
  1661. /* set/get features cache service (equal to raw service) */
  1662. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_SET_FEAT, 0,
  1663. SCATTER_GATHER,0)) {
  1664. TRACE2(("gdth_search_drives(): set features CACHESERVICE OK\n"));
  1665. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_GET_FEAT, 0, 0, 0)) {
  1666. TRACE2(("gdth_search_dr(): get feat CACHESERV. %d\n",
  1667. ha->info));
  1668. ha->cache_feat |= (u16)ha->info;
  1669. }
  1670. }
  1671. /* reserve drives for raw service */
  1672. if (reserve_mode != 0) {
  1673. gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESERVE_ALL,
  1674. reserve_mode == 1 ? 1 : 3, 0, 0);
  1675. TRACE2(("gdth_search_drives(): RESERVE_ALL code %d\n",
  1676. ha->status));
  1677. }
  1678. for (i = 0; i < MAX_RES_ARGS; i += 4) {
  1679. if (reserve_list[i] == ha->hanum && reserve_list[i+1] < ha->bus_cnt &&
  1680. reserve_list[i+2] < ha->tid_cnt && reserve_list[i+3] < MAXLUN) {
  1681. TRACE2(("gdth_search_drives(): reserve ha %d bus %d id %d lun %d\n",
  1682. reserve_list[i], reserve_list[i+1],
  1683. reserve_list[i+2], reserve_list[i+3]));
  1684. if (!gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESERVE, 0,
  1685. reserve_list[i+1], reserve_list[i+2] |
  1686. (reserve_list[i+3] << 8))) {
  1687. printk("GDT-HA %d: Error raw service (RESERVE, code %d)\n",
  1688. ha->hanum, ha->status);
  1689. }
  1690. }
  1691. }
  1692. /* Determine OEM string using IOCTL */
  1693. oemstr = (gdth_oem_str_ioctl *)ha->pscratch;
  1694. oemstr->params.ctl_version = 0x01;
  1695. oemstr->params.buffer_size = sizeof(oemstr->text);
  1696. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1697. CACHE_READ_OEM_STRING_RECORD,INVALID_CHANNEL,
  1698. sizeof(gdth_oem_str_ioctl))) {
  1699. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD OK\n"));
  1700. printk("GDT-HA %d: Vendor: %s Name: %s\n",
  1701. ha->hanum, oemstr->text.oem_company_name, ha->binfo.type_string);
  1702. /* Save the Host Drive inquiry data */
  1703. strlcpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,
  1704. sizeof(ha->oem_name));
  1705. } else {
  1706. /* Old method, based on PCI ID */
  1707. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD failed\n"));
  1708. printk("GDT-HA %d: Name: %s\n",
  1709. ha->hanum, ha->binfo.type_string);
  1710. if (ha->oem_id == OEM_ID_INTEL)
  1711. strlcpy(ha->oem_name,"Intel ", sizeof(ha->oem_name));
  1712. else
  1713. strlcpy(ha->oem_name,"ICP ", sizeof(ha->oem_name));
  1714. }
  1715. /* scanning for host drives */
  1716. for (i = 0; i < cdev_cnt; ++i)
  1717. gdth_analyse_hdrive(ha, i);
  1718. TRACE(("gdth_search_drives() OK\n"));
  1719. return 1;
  1720. }
  1721. static int gdth_analyse_hdrive(gdth_ha_str *ha, u16 hdrive)
  1722. {
  1723. u32 drv_cyls;
  1724. int drv_hds, drv_secs;
  1725. TRACE(("gdth_analyse_hdrive() hanum %d drive %d\n", ha->hanum, hdrive));
  1726. if (hdrive >= MAX_HDRIVES)
  1727. return 0;
  1728. if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_INFO, hdrive, 0, 0))
  1729. return 0;
  1730. ha->hdr[hdrive].present = TRUE;
  1731. ha->hdr[hdrive].size = ha->info;
  1732. /* evaluate mapping (sectors per head, heads per cylinder) */
  1733. ha->hdr[hdrive].size &= ~SECS32;
  1734. if (ha->info2 == 0) {
  1735. gdth_eval_mapping(ha->hdr[hdrive].size,&drv_cyls,&drv_hds,&drv_secs);
  1736. } else {
  1737. drv_hds = ha->info2 & 0xff;
  1738. drv_secs = (ha->info2 >> 8) & 0xff;
  1739. drv_cyls = (u32)ha->hdr[hdrive].size / drv_hds / drv_secs;
  1740. }
  1741. ha->hdr[hdrive].heads = (u8)drv_hds;
  1742. ha->hdr[hdrive].secs = (u8)drv_secs;
  1743. /* round size */
  1744. ha->hdr[hdrive].size = drv_cyls * drv_hds * drv_secs;
  1745. if (ha->cache_feat & GDT_64BIT) {
  1746. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_X_INFO, hdrive, 0, 0)
  1747. && ha->info2 != 0) {
  1748. ha->hdr[hdrive].size = ((u64)ha->info2 << 32) | ha->info;
  1749. }
  1750. }
  1751. TRACE2(("gdth_search_dr() cdr. %d size %d hds %d scs %d\n",
  1752. hdrive,ha->hdr[hdrive].size,drv_hds,drv_secs));
  1753. /* get informations about device */
  1754. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_DEVTYPE, hdrive, 0, 0)) {
  1755. TRACE2(("gdth_search_dr() cache drive %d devtype %d\n",
  1756. hdrive,ha->info));
  1757. ha->hdr[hdrive].devtype = (u16)ha->info;
  1758. }
  1759. /* cluster info */
  1760. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_CLUST_INFO, hdrive, 0, 0)) {
  1761. TRACE2(("gdth_search_dr() cache drive %d cluster info %d\n",
  1762. hdrive,ha->info));
  1763. if (!shared_access)
  1764. ha->hdr[hdrive].cluster_type = (u8)ha->info;
  1765. }
  1766. /* R/W attributes */
  1767. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_RW_ATTRIBS, hdrive, 0, 0)) {
  1768. TRACE2(("gdth_search_dr() cache drive %d r/w attrib. %d\n",
  1769. hdrive,ha->info));
  1770. ha->hdr[hdrive].rw_attribs = (u8)ha->info;
  1771. }
  1772. return 1;
  1773. }
  1774. /* command queueing/sending functions */
  1775. static void gdth_putq(gdth_ha_str *ha, struct scsi_cmnd *scp, u8 priority)
  1776. {
  1777. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  1778. register struct scsi_cmnd *pscp;
  1779. register struct scsi_cmnd *nscp;
  1780. unsigned long flags;
  1781. TRACE(("gdth_putq() priority %d\n",priority));
  1782. spin_lock_irqsave(&ha->smp_lock, flags);
  1783. if (!cmndinfo->internal_command)
  1784. cmndinfo->priority = priority;
  1785. if (ha->req_first==NULL) {
  1786. ha->req_first = scp; /* queue was empty */
  1787. scp->SCp.ptr = NULL;
  1788. } else { /* queue not empty */
  1789. pscp = ha->req_first;
  1790. nscp = (struct scsi_cmnd *)pscp->SCp.ptr;
  1791. /* priority: 0-highest,..,0xff-lowest */
  1792. while (nscp && gdth_cmnd_priv(nscp)->priority <= priority) {
  1793. pscp = nscp;
  1794. nscp = (struct scsi_cmnd *)pscp->SCp.ptr;
  1795. }
  1796. pscp->SCp.ptr = (char *)scp;
  1797. scp->SCp.ptr = (char *)nscp;
  1798. }
  1799. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1800. #ifdef GDTH_STATISTICS
  1801. flags = 0;
  1802. for (nscp=ha->req_first; nscp; nscp=(struct scsi_cmnd*)nscp->SCp.ptr)
  1803. ++flags;
  1804. if (max_rq < flags) {
  1805. max_rq = flags;
  1806. TRACE3(("GDT: max_rq = %d\n",(u16)max_rq));
  1807. }
  1808. #endif
  1809. }
  1810. static void gdth_next(gdth_ha_str *ha)
  1811. {
  1812. register struct scsi_cmnd *pscp;
  1813. register struct scsi_cmnd *nscp;
  1814. u8 b, t, l, firsttime;
  1815. u8 this_cmd, next_cmd;
  1816. unsigned long flags = 0;
  1817. int cmd_index;
  1818. TRACE(("gdth_next() hanum %d\n", ha->hanum));
  1819. if (!gdth_polling)
  1820. spin_lock_irqsave(&ha->smp_lock, flags);
  1821. ha->cmd_cnt = ha->cmd_offs_dpmem = 0;
  1822. this_cmd = firsttime = TRUE;
  1823. next_cmd = gdth_polling ? FALSE:TRUE;
  1824. cmd_index = 0;
  1825. for (nscp = pscp = ha->req_first; nscp; nscp = (struct scsi_cmnd *)nscp->SCp.ptr) {
  1826. struct gdth_cmndinfo *nscp_cmndinfo = gdth_cmnd_priv(nscp);
  1827. if (nscp != pscp && nscp != (struct scsi_cmnd *)pscp->SCp.ptr)
  1828. pscp = (struct scsi_cmnd *)pscp->SCp.ptr;
  1829. if (!nscp_cmndinfo->internal_command) {
  1830. b = nscp->device->channel;
  1831. t = nscp->device->id;
  1832. l = nscp->device->lun;
  1833. if (nscp_cmndinfo->priority >= DEFAULT_PRI) {
  1834. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  1835. (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock))
  1836. continue;
  1837. }
  1838. } else
  1839. b = t = l = 0;
  1840. if (firsttime) {
  1841. if (gdth_test_busy(ha)) { /* controller busy ? */
  1842. TRACE(("gdth_next() controller %d busy !\n", ha->hanum));
  1843. if (!gdth_polling) {
  1844. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1845. return;
  1846. }
  1847. while (gdth_test_busy(ha))
  1848. gdth_delay(1);
  1849. }
  1850. firsttime = FALSE;
  1851. }
  1852. if (!nscp_cmndinfo->internal_command) {
  1853. if (nscp_cmndinfo->phase == -1) {
  1854. nscp_cmndinfo->phase = CACHESERVICE; /* default: cache svc. */
  1855. if (nscp->cmnd[0] == TEST_UNIT_READY) {
  1856. TRACE2(("TEST_UNIT_READY Bus %d Id %d LUN %d\n",
  1857. b, t, l));
  1858. /* TEST_UNIT_READY -> set scan mode */
  1859. if ((ha->scan_mode & 0x0f) == 0) {
  1860. if (b == 0 && t == 0 && l == 0) {
  1861. ha->scan_mode |= 1;
  1862. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  1863. }
  1864. } else if ((ha->scan_mode & 0x0f) == 1) {
  1865. if (b == 0 && ((t == 0 && l == 1) ||
  1866. (t == 1 && l == 0))) {
  1867. nscp_cmndinfo->OpCode = GDT_SCAN_START;
  1868. nscp_cmndinfo->phase = ((ha->scan_mode & 0x10 ? 1:0) << 8)
  1869. | SCSIRAWSERVICE;
  1870. ha->scan_mode = 0x12;
  1871. TRACE2(("Scan mode: 0x%x (SCAN_START)\n",
  1872. ha->scan_mode));
  1873. } else {
  1874. ha->scan_mode &= 0x10;
  1875. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  1876. }
  1877. } else if (ha->scan_mode == 0x12) {
  1878. if (b == ha->bus_cnt && t == ha->tid_cnt-1) {
  1879. nscp_cmndinfo->phase = SCSIRAWSERVICE;
  1880. nscp_cmndinfo->OpCode = GDT_SCAN_END;
  1881. ha->scan_mode &= 0x10;
  1882. TRACE2(("Scan mode: 0x%x (SCAN_END)\n",
  1883. ha->scan_mode));
  1884. }
  1885. }
  1886. }
  1887. if (b == ha->virt_bus && nscp->cmnd[0] != INQUIRY &&
  1888. nscp->cmnd[0] != READ_CAPACITY && nscp->cmnd[0] != MODE_SENSE &&
  1889. (ha->hdr[t].cluster_type & CLUSTER_DRIVE)) {
  1890. /* always GDT_CLUST_INFO! */
  1891. nscp_cmndinfo->OpCode = GDT_CLUST_INFO;
  1892. }
  1893. }
  1894. }
  1895. if (nscp_cmndinfo->OpCode != -1) {
  1896. if ((nscp_cmndinfo->phase & 0xff) == CACHESERVICE) {
  1897. if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  1898. this_cmd = FALSE;
  1899. next_cmd = FALSE;
  1900. } else if ((nscp_cmndinfo->phase & 0xff) == SCSIRAWSERVICE) {
  1901. if (!(cmd_index=gdth_fill_raw_cmd(ha, nscp, BUS_L2P(ha, b))))
  1902. this_cmd = FALSE;
  1903. next_cmd = FALSE;
  1904. } else {
  1905. memset((char*)nscp->sense_buffer,0,16);
  1906. nscp->sense_buffer[0] = 0x70;
  1907. nscp->sense_buffer[2] = NOT_READY;
  1908. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  1909. if (!nscp_cmndinfo->wait_for_completion)
  1910. nscp_cmndinfo->wait_for_completion++;
  1911. else
  1912. gdth_scsi_done(nscp);
  1913. }
  1914. } else if (gdth_cmnd_priv(nscp)->internal_command) {
  1915. if (!(cmd_index=gdth_special_cmd(ha, nscp)))
  1916. this_cmd = FALSE;
  1917. next_cmd = FALSE;
  1918. } else if (b != ha->virt_bus) {
  1919. if (ha->raw[BUS_L2P(ha,b)].io_cnt[t] >= GDTH_MAX_RAW ||
  1920. !(cmd_index=gdth_fill_raw_cmd(ha, nscp, BUS_L2P(ha, b))))
  1921. this_cmd = FALSE;
  1922. else
  1923. ha->raw[BUS_L2P(ha,b)].io_cnt[t]++;
  1924. } else if (t >= MAX_HDRIVES || !ha->hdr[t].present || l != 0) {
  1925. TRACE2(("Command 0x%x to bus %d id %d lun %d -> IGNORE\n",
  1926. nscp->cmnd[0], b, t, l));
  1927. nscp->result = DID_BAD_TARGET << 16;
  1928. if (!nscp_cmndinfo->wait_for_completion)
  1929. nscp_cmndinfo->wait_for_completion++;
  1930. else
  1931. gdth_scsi_done(nscp);
  1932. } else {
  1933. switch (nscp->cmnd[0]) {
  1934. case TEST_UNIT_READY:
  1935. case INQUIRY:
  1936. case REQUEST_SENSE:
  1937. case READ_CAPACITY:
  1938. case VERIFY:
  1939. case START_STOP:
  1940. case MODE_SENSE:
  1941. case SERVICE_ACTION_IN_16:
  1942. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  1943. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  1944. nscp->cmnd[4],nscp->cmnd[5]));
  1945. if (ha->hdr[t].media_changed && nscp->cmnd[0] != INQUIRY) {
  1946. /* return UNIT_ATTENTION */
  1947. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  1948. nscp->cmnd[0], t));
  1949. ha->hdr[t].media_changed = FALSE;
  1950. memset((char*)nscp->sense_buffer,0,16);
  1951. nscp->sense_buffer[0] = 0x70;
  1952. nscp->sense_buffer[2] = UNIT_ATTENTION;
  1953. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  1954. if (!nscp_cmndinfo->wait_for_completion)
  1955. nscp_cmndinfo->wait_for_completion++;
  1956. else
  1957. gdth_scsi_done(nscp);
  1958. } else if (gdth_internal_cache_cmd(ha, nscp))
  1959. gdth_scsi_done(nscp);
  1960. break;
  1961. case ALLOW_MEDIUM_REMOVAL:
  1962. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  1963. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  1964. nscp->cmnd[4],nscp->cmnd[5]));
  1965. if ( (nscp->cmnd[4]&1) && !(ha->hdr[t].devtype&1) ) {
  1966. TRACE(("Prevent r. nonremov. drive->do nothing\n"));
  1967. nscp->result = DID_OK << 16;
  1968. nscp->sense_buffer[0] = 0;
  1969. if (!nscp_cmndinfo->wait_for_completion)
  1970. nscp_cmndinfo->wait_for_completion++;
  1971. else
  1972. gdth_scsi_done(nscp);
  1973. } else {
  1974. nscp->cmnd[3] = (ha->hdr[t].devtype&1) ? 1:0;
  1975. TRACE(("Prevent/allow r. %d rem. drive %d\n",
  1976. nscp->cmnd[4],nscp->cmnd[3]));
  1977. if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  1978. this_cmd = FALSE;
  1979. }
  1980. break;
  1981. case RESERVE:
  1982. case RELEASE:
  1983. TRACE2(("cache cmd %s\n",nscp->cmnd[0] == RESERVE ?
  1984. "RESERVE" : "RELEASE"));
  1985. if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  1986. this_cmd = FALSE;
  1987. break;
  1988. case READ_6:
  1989. case WRITE_6:
  1990. case READ_10:
  1991. case WRITE_10:
  1992. case READ_16:
  1993. case WRITE_16:
  1994. if (ha->hdr[t].media_changed) {
  1995. /* return UNIT_ATTENTION */
  1996. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  1997. nscp->cmnd[0], t));
  1998. ha->hdr[t].media_changed = FALSE;
  1999. memset((char*)nscp->sense_buffer,0,16);
  2000. nscp->sense_buffer[0] = 0x70;
  2001. nscp->sense_buffer[2] = UNIT_ATTENTION;
  2002. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2003. if (!nscp_cmndinfo->wait_for_completion)
  2004. nscp_cmndinfo->wait_for_completion++;
  2005. else
  2006. gdth_scsi_done(nscp);
  2007. } else if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  2008. this_cmd = FALSE;
  2009. break;
  2010. default:
  2011. TRACE2(("cache cmd %x/%x/%x/%x/%x/%x unknown\n",nscp->cmnd[0],
  2012. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2013. nscp->cmnd[4],nscp->cmnd[5]));
  2014. printk("GDT-HA %d: Unknown SCSI command 0x%x to cache service !\n",
  2015. ha->hanum, nscp->cmnd[0]);
  2016. nscp->result = DID_ABORT << 16;
  2017. if (!nscp_cmndinfo->wait_for_completion)
  2018. nscp_cmndinfo->wait_for_completion++;
  2019. else
  2020. gdth_scsi_done(nscp);
  2021. break;
  2022. }
  2023. }
  2024. if (!this_cmd)
  2025. break;
  2026. if (nscp == ha->req_first)
  2027. ha->req_first = pscp = (struct scsi_cmnd *)nscp->SCp.ptr;
  2028. else
  2029. pscp->SCp.ptr = nscp->SCp.ptr;
  2030. if (!next_cmd)
  2031. break;
  2032. }
  2033. if (ha->cmd_cnt > 0) {
  2034. gdth_release_event(ha);
  2035. }
  2036. if (!gdth_polling)
  2037. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2038. if (gdth_polling && ha->cmd_cnt > 0) {
  2039. if (!gdth_wait(ha, cmd_index, POLL_TIMEOUT))
  2040. printk("GDT-HA %d: Command %d timed out !\n",
  2041. ha->hanum, cmd_index);
  2042. }
  2043. }
  2044. /*
  2045. * gdth_copy_internal_data() - copy to/from a buffer onto a scsi_cmnd's
  2046. * buffers, kmap_atomic() as needed.
  2047. */
  2048. static void gdth_copy_internal_data(gdth_ha_str *ha, struct scsi_cmnd *scp,
  2049. char *buffer, u16 count)
  2050. {
  2051. u16 cpcount,i, max_sg = scsi_sg_count(scp);
  2052. u16 cpsum,cpnow;
  2053. struct scatterlist *sl;
  2054. char *address;
  2055. cpcount = min_t(u16, count, scsi_bufflen(scp));
  2056. if (cpcount) {
  2057. cpsum=0;
  2058. scsi_for_each_sg(scp, sl, max_sg, i) {
  2059. unsigned long flags;
  2060. cpnow = (u16)sl->length;
  2061. TRACE(("copy_internal() now %d sum %d count %d %d\n",
  2062. cpnow, cpsum, cpcount, scsi_bufflen(scp)));
  2063. if (cpsum+cpnow > cpcount)
  2064. cpnow = cpcount - cpsum;
  2065. cpsum += cpnow;
  2066. if (!sg_page(sl)) {
  2067. printk("GDT-HA %d: invalid sc/gt element in gdth_copy_internal_data()\n",
  2068. ha->hanum);
  2069. return;
  2070. }
  2071. local_irq_save(flags);
  2072. address = kmap_atomic(sg_page(sl)) + sl->offset;
  2073. memcpy(address, buffer, cpnow);
  2074. flush_dcache_page(sg_page(sl));
  2075. kunmap_atomic(address);
  2076. local_irq_restore(flags);
  2077. if (cpsum == cpcount)
  2078. break;
  2079. buffer += cpnow;
  2080. }
  2081. } else if (count) {
  2082. printk("GDT-HA %d: SCSI command with no buffers but data transfer expected!\n",
  2083. ha->hanum);
  2084. WARN_ON(1);
  2085. }
  2086. }
  2087. static int gdth_internal_cache_cmd(gdth_ha_str *ha, struct scsi_cmnd *scp)
  2088. {
  2089. u8 t;
  2090. gdth_inq_data inq;
  2091. gdth_rdcap_data rdc;
  2092. gdth_sense_data sd;
  2093. gdth_modep_data mpd;
  2094. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  2095. t = scp->device->id;
  2096. TRACE(("gdth_internal_cache_cmd() cmd 0x%x hdrive %d\n",
  2097. scp->cmnd[0],t));
  2098. scp->result = DID_OK << 16;
  2099. scp->sense_buffer[0] = 0;
  2100. switch (scp->cmnd[0]) {
  2101. case TEST_UNIT_READY:
  2102. case VERIFY:
  2103. case START_STOP:
  2104. TRACE2(("Test/Verify/Start hdrive %d\n",t));
  2105. break;
  2106. case INQUIRY:
  2107. TRACE2(("Inquiry hdrive %d devtype %d\n",
  2108. t,ha->hdr[t].devtype));
  2109. inq.type_qual = (ha->hdr[t].devtype&4) ? TYPE_ROM:TYPE_DISK;
  2110. /* you can here set all disks to removable, if you want to do
  2111. a flush using the ALLOW_MEDIUM_REMOVAL command */
  2112. inq.modif_rmb = 0x00;
  2113. if ((ha->hdr[t].devtype & 1) ||
  2114. (ha->hdr[t].cluster_type & CLUSTER_DRIVE))
  2115. inq.modif_rmb = 0x80;
  2116. inq.version = 2;
  2117. inq.resp_aenc = 2;
  2118. inq.add_length= 32;
  2119. strcpy(inq.vendor,ha->oem_name);
  2120. snprintf(inq.product, sizeof(inq.product), "Host Drive #%02d",t);
  2121. strcpy(inq.revision," ");
  2122. gdth_copy_internal_data(ha, scp, (char*)&inq, sizeof(gdth_inq_data));
  2123. break;
  2124. case REQUEST_SENSE:
  2125. TRACE2(("Request sense hdrive %d\n",t));
  2126. sd.errorcode = 0x70;
  2127. sd.segno = 0x00;
  2128. sd.key = NO_SENSE;
  2129. sd.info = 0;
  2130. sd.add_length= 0;
  2131. gdth_copy_internal_data(ha, scp, (char*)&sd, sizeof(gdth_sense_data));
  2132. break;
  2133. case MODE_SENSE:
  2134. TRACE2(("Mode sense hdrive %d\n",t));
  2135. memset((char*)&mpd,0,sizeof(gdth_modep_data));
  2136. mpd.hd.data_length = sizeof(gdth_modep_data);
  2137. mpd.hd.dev_par = (ha->hdr[t].devtype&2) ? 0x80:0;
  2138. mpd.hd.bd_length = sizeof(mpd.bd);
  2139. mpd.bd.block_length[0] = (SECTOR_SIZE & 0x00ff0000) >> 16;
  2140. mpd.bd.block_length[1] = (SECTOR_SIZE & 0x0000ff00) >> 8;
  2141. mpd.bd.block_length[2] = (SECTOR_SIZE & 0x000000ff);
  2142. gdth_copy_internal_data(ha, scp, (char*)&mpd, sizeof(gdth_modep_data));
  2143. break;
  2144. case READ_CAPACITY:
  2145. TRACE2(("Read capacity hdrive %d\n",t));
  2146. if (ha->hdr[t].size > (u64)0xffffffff)
  2147. rdc.last_block_no = 0xffffffff;
  2148. else
  2149. rdc.last_block_no = cpu_to_be32(ha->hdr[t].size-1);
  2150. rdc.block_length = cpu_to_be32(SECTOR_SIZE);
  2151. gdth_copy_internal_data(ha, scp, (char*)&rdc, sizeof(gdth_rdcap_data));
  2152. break;
  2153. case SERVICE_ACTION_IN_16:
  2154. if ((scp->cmnd[1] & 0x1f) == SAI_READ_CAPACITY_16 &&
  2155. (ha->cache_feat & GDT_64BIT)) {
  2156. gdth_rdcap16_data rdc16;
  2157. TRACE2(("Read capacity (16) hdrive %d\n",t));
  2158. rdc16.last_block_no = cpu_to_be64(ha->hdr[t].size-1);
  2159. rdc16.block_length = cpu_to_be32(SECTOR_SIZE);
  2160. gdth_copy_internal_data(ha, scp, (char*)&rdc16,
  2161. sizeof(gdth_rdcap16_data));
  2162. } else {
  2163. scp->result = DID_ABORT << 16;
  2164. }
  2165. break;
  2166. default:
  2167. TRACE2(("Internal cache cmd 0x%x unknown\n",scp->cmnd[0]));
  2168. break;
  2169. }
  2170. if (!cmndinfo->wait_for_completion)
  2171. cmndinfo->wait_for_completion++;
  2172. else
  2173. return 1;
  2174. return 0;
  2175. }
  2176. static int gdth_fill_cache_cmd(gdth_ha_str *ha, struct scsi_cmnd *scp,
  2177. u16 hdrive)
  2178. {
  2179. register gdth_cmd_str *cmdp;
  2180. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  2181. u32 cnt, blockcnt;
  2182. u64 no, blockno;
  2183. int i, cmd_index, read_write, sgcnt, mode64;
  2184. cmdp = ha->pccb;
  2185. TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n",
  2186. scp->cmnd[0],scp->cmd_len,hdrive));
  2187. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2188. return 0;
  2189. mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE;
  2190. /* test for READ_16, WRITE_16 if !mode64 ? ---
  2191. not required, should not occur due to error return on
  2192. READ_CAPACITY_16 */
  2193. cmdp->Service = CACHESERVICE;
  2194. cmdp->RequestBuffer = scp;
  2195. /* search free command index */
  2196. if (!(cmd_index=gdth_get_cmd_index(ha))) {
  2197. TRACE(("GDT: No free command index found\n"));
  2198. return 0;
  2199. }
  2200. /* if it's the first command, set command semaphore */
  2201. if (ha->cmd_cnt == 0)
  2202. gdth_set_sema0(ha);
  2203. /* fill command */
  2204. read_write = 0;
  2205. if (cmndinfo->OpCode != -1)
  2206. cmdp->OpCode = cmndinfo->OpCode; /* special cache cmd. */
  2207. else if (scp->cmnd[0] == RESERVE)
  2208. cmdp->OpCode = GDT_RESERVE_DRV;
  2209. else if (scp->cmnd[0] == RELEASE)
  2210. cmdp->OpCode = GDT_RELEASE_DRV;
  2211. else if (scp->cmnd[0] == ALLOW_MEDIUM_REMOVAL) {
  2212. if (scp->cmnd[4] & 1) /* prevent ? */
  2213. cmdp->OpCode = GDT_MOUNT;
  2214. else if (scp->cmnd[3] & 1) /* removable drive ? */
  2215. cmdp->OpCode = GDT_UNMOUNT;
  2216. else
  2217. cmdp->OpCode = GDT_FLUSH;
  2218. } else if (scp->cmnd[0] == WRITE_6 || scp->cmnd[0] == WRITE_10 ||
  2219. scp->cmnd[0] == WRITE_12 || scp->cmnd[0] == WRITE_16
  2220. ) {
  2221. read_write = 1;
  2222. if (gdth_write_through || ((ha->hdr[hdrive].rw_attribs & 1) &&
  2223. (ha->cache_feat & GDT_WR_THROUGH)))
  2224. cmdp->OpCode = GDT_WRITE_THR;
  2225. else
  2226. cmdp->OpCode = GDT_WRITE;
  2227. } else {
  2228. read_write = 2;
  2229. cmdp->OpCode = GDT_READ;
  2230. }
  2231. cmdp->BoardNode = LOCALBOARD;
  2232. if (mode64) {
  2233. cmdp->u.cache64.DeviceNo = hdrive;
  2234. cmdp->u.cache64.BlockNo = 1;
  2235. cmdp->u.cache64.sg_canz = 0;
  2236. } else {
  2237. cmdp->u.cache.DeviceNo = hdrive;
  2238. cmdp->u.cache.BlockNo = 1;
  2239. cmdp->u.cache.sg_canz = 0;
  2240. }
  2241. if (read_write) {
  2242. if (scp->cmd_len == 16) {
  2243. memcpy(&no, &scp->cmnd[2], sizeof(u64));
  2244. blockno = be64_to_cpu(no);
  2245. memcpy(&cnt, &scp->cmnd[10], sizeof(u32));
  2246. blockcnt = be32_to_cpu(cnt);
  2247. } else if (scp->cmd_len == 10) {
  2248. memcpy(&no, &scp->cmnd[2], sizeof(u32));
  2249. blockno = be32_to_cpu(no);
  2250. memcpy(&cnt, &scp->cmnd[7], sizeof(u16));
  2251. blockcnt = be16_to_cpu(cnt);
  2252. } else {
  2253. memcpy(&no, &scp->cmnd[0], sizeof(u32));
  2254. blockno = be32_to_cpu(no) & 0x001fffffUL;
  2255. blockcnt= scp->cmnd[4]==0 ? 0x100 : scp->cmnd[4];
  2256. }
  2257. if (mode64) {
  2258. cmdp->u.cache64.BlockNo = blockno;
  2259. cmdp->u.cache64.BlockCnt = blockcnt;
  2260. } else {
  2261. cmdp->u.cache.BlockNo = (u32)blockno;
  2262. cmdp->u.cache.BlockCnt = blockcnt;
  2263. }
  2264. if (scsi_bufflen(scp)) {
  2265. cmndinfo->dma_dir = (read_write == 1 ?
  2266. PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  2267. sgcnt = pci_map_sg(ha->pdev, scsi_sglist(scp), scsi_sg_count(scp),
  2268. cmndinfo->dma_dir);
  2269. if (mode64) {
  2270. struct scatterlist *sl;
  2271. cmdp->u.cache64.DestAddr= (u64)-1;
  2272. cmdp->u.cache64.sg_canz = sgcnt;
  2273. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2274. cmdp->u.cache64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2275. #ifdef GDTH_DMA_STATISTICS
  2276. if (cmdp->u.cache64.sg_lst[i].sg_ptr > (u64)0xffffffff)
  2277. ha->dma64_cnt++;
  2278. else
  2279. ha->dma32_cnt++;
  2280. #endif
  2281. cmdp->u.cache64.sg_lst[i].sg_len = sg_dma_len(sl);
  2282. }
  2283. } else {
  2284. struct scatterlist *sl;
  2285. cmdp->u.cache.DestAddr= 0xffffffff;
  2286. cmdp->u.cache.sg_canz = sgcnt;
  2287. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2288. cmdp->u.cache.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2289. #ifdef GDTH_DMA_STATISTICS
  2290. ha->dma32_cnt++;
  2291. #endif
  2292. cmdp->u.cache.sg_lst[i].sg_len = sg_dma_len(sl);
  2293. }
  2294. }
  2295. #ifdef GDTH_STATISTICS
  2296. if (max_sg < (u32)sgcnt) {
  2297. max_sg = (u32)sgcnt;
  2298. TRACE3(("GDT: max_sg = %d\n",max_sg));
  2299. }
  2300. #endif
  2301. }
  2302. }
  2303. /* evaluate command size, check space */
  2304. if (mode64) {
  2305. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2306. cmdp->u.cache64.DestAddr,cmdp->u.cache64.sg_canz,
  2307. cmdp->u.cache64.sg_lst[0].sg_ptr,
  2308. cmdp->u.cache64.sg_lst[0].sg_len));
  2309. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2310. cmdp->OpCode,cmdp->u.cache64.BlockNo,cmdp->u.cache64.BlockCnt));
  2311. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) +
  2312. (u16)cmdp->u.cache64.sg_canz * sizeof(gdth_sg64_str);
  2313. } else {
  2314. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2315. cmdp->u.cache.DestAddr,cmdp->u.cache.sg_canz,
  2316. cmdp->u.cache.sg_lst[0].sg_ptr,
  2317. cmdp->u.cache.sg_lst[0].sg_len));
  2318. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2319. cmdp->OpCode,cmdp->u.cache.BlockNo,cmdp->u.cache.BlockCnt));
  2320. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) +
  2321. (u16)cmdp->u.cache.sg_canz * sizeof(gdth_sg_str);
  2322. }
  2323. if (ha->cmd_len & 3)
  2324. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2325. if (ha->cmd_cnt > 0) {
  2326. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2327. ha->ic_all_size) {
  2328. TRACE2(("gdth_fill_cache() DPMEM overflow\n"));
  2329. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2330. return 0;
  2331. }
  2332. }
  2333. /* copy command */
  2334. gdth_copy_command(ha);
  2335. return cmd_index;
  2336. }
  2337. static int gdth_fill_raw_cmd(gdth_ha_str *ha, struct scsi_cmnd *scp, u8 b)
  2338. {
  2339. register gdth_cmd_str *cmdp;
  2340. u16 i;
  2341. dma_addr_t sense_paddr;
  2342. int cmd_index, sgcnt, mode64;
  2343. u8 t,l;
  2344. struct page *page;
  2345. unsigned long offset;
  2346. struct gdth_cmndinfo *cmndinfo;
  2347. t = scp->device->id;
  2348. l = scp->device->lun;
  2349. cmdp = ha->pccb;
  2350. TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n",
  2351. scp->cmnd[0],b,t,l));
  2352. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2353. return 0;
  2354. mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE;
  2355. cmdp->Service = SCSIRAWSERVICE;
  2356. cmdp->RequestBuffer = scp;
  2357. /* search free command index */
  2358. if (!(cmd_index=gdth_get_cmd_index(ha))) {
  2359. TRACE(("GDT: No free command index found\n"));
  2360. return 0;
  2361. }
  2362. /* if it's the first command, set command semaphore */
  2363. if (ha->cmd_cnt == 0)
  2364. gdth_set_sema0(ha);
  2365. cmndinfo = gdth_cmnd_priv(scp);
  2366. /* fill command */
  2367. if (cmndinfo->OpCode != -1) {
  2368. cmdp->OpCode = cmndinfo->OpCode; /* special raw cmd. */
  2369. cmdp->BoardNode = LOCALBOARD;
  2370. if (mode64) {
  2371. cmdp->u.raw64.direction = (cmndinfo->phase >> 8);
  2372. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2373. cmdp->OpCode, cmdp->u.raw64.direction));
  2374. /* evaluate command size */
  2375. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst);
  2376. } else {
  2377. cmdp->u.raw.direction = (cmndinfo->phase >> 8);
  2378. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2379. cmdp->OpCode, cmdp->u.raw.direction));
  2380. /* evaluate command size */
  2381. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst);
  2382. }
  2383. } else {
  2384. page = virt_to_page(scp->sense_buffer);
  2385. offset = (unsigned long)scp->sense_buffer & ~PAGE_MASK;
  2386. sense_paddr = pci_map_page(ha->pdev,page,offset,
  2387. 16,PCI_DMA_FROMDEVICE);
  2388. cmndinfo->sense_paddr = sense_paddr;
  2389. cmdp->OpCode = GDT_WRITE; /* always */
  2390. cmdp->BoardNode = LOCALBOARD;
  2391. if (mode64) {
  2392. cmdp->u.raw64.reserved = 0;
  2393. cmdp->u.raw64.mdisc_time = 0;
  2394. cmdp->u.raw64.mcon_time = 0;
  2395. cmdp->u.raw64.clen = scp->cmd_len;
  2396. cmdp->u.raw64.target = t;
  2397. cmdp->u.raw64.lun = l;
  2398. cmdp->u.raw64.bus = b;
  2399. cmdp->u.raw64.priority = 0;
  2400. cmdp->u.raw64.sdlen = scsi_bufflen(scp);
  2401. cmdp->u.raw64.sense_len = 16;
  2402. cmdp->u.raw64.sense_data = sense_paddr;
  2403. cmdp->u.raw64.direction =
  2404. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2405. memcpy(cmdp->u.raw64.cmd,scp->cmnd,16);
  2406. cmdp->u.raw64.sg_ranz = 0;
  2407. } else {
  2408. cmdp->u.raw.reserved = 0;
  2409. cmdp->u.raw.mdisc_time = 0;
  2410. cmdp->u.raw.mcon_time = 0;
  2411. cmdp->u.raw.clen = scp->cmd_len;
  2412. cmdp->u.raw.target = t;
  2413. cmdp->u.raw.lun = l;
  2414. cmdp->u.raw.bus = b;
  2415. cmdp->u.raw.priority = 0;
  2416. cmdp->u.raw.link_p = 0;
  2417. cmdp->u.raw.sdlen = scsi_bufflen(scp);
  2418. cmdp->u.raw.sense_len = 16;
  2419. cmdp->u.raw.sense_data = sense_paddr;
  2420. cmdp->u.raw.direction =
  2421. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2422. memcpy(cmdp->u.raw.cmd,scp->cmnd,12);
  2423. cmdp->u.raw.sg_ranz = 0;
  2424. }
  2425. if (scsi_bufflen(scp)) {
  2426. cmndinfo->dma_dir = PCI_DMA_BIDIRECTIONAL;
  2427. sgcnt = pci_map_sg(ha->pdev, scsi_sglist(scp), scsi_sg_count(scp),
  2428. cmndinfo->dma_dir);
  2429. if (mode64) {
  2430. struct scatterlist *sl;
  2431. cmdp->u.raw64.sdata = (u64)-1;
  2432. cmdp->u.raw64.sg_ranz = sgcnt;
  2433. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2434. cmdp->u.raw64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2435. #ifdef GDTH_DMA_STATISTICS
  2436. if (cmdp->u.raw64.sg_lst[i].sg_ptr > (u64)0xffffffff)
  2437. ha->dma64_cnt++;
  2438. else
  2439. ha->dma32_cnt++;
  2440. #endif
  2441. cmdp->u.raw64.sg_lst[i].sg_len = sg_dma_len(sl);
  2442. }
  2443. } else {
  2444. struct scatterlist *sl;
  2445. cmdp->u.raw.sdata = 0xffffffff;
  2446. cmdp->u.raw.sg_ranz = sgcnt;
  2447. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2448. cmdp->u.raw.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2449. #ifdef GDTH_DMA_STATISTICS
  2450. ha->dma32_cnt++;
  2451. #endif
  2452. cmdp->u.raw.sg_lst[i].sg_len = sg_dma_len(sl);
  2453. }
  2454. }
  2455. #ifdef GDTH_STATISTICS
  2456. if (max_sg < sgcnt) {
  2457. max_sg = sgcnt;
  2458. TRACE3(("GDT: max_sg = %d\n",sgcnt));
  2459. }
  2460. #endif
  2461. }
  2462. if (mode64) {
  2463. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2464. cmdp->u.raw64.sdata,cmdp->u.raw64.sg_ranz,
  2465. cmdp->u.raw64.sg_lst[0].sg_ptr,
  2466. cmdp->u.raw64.sg_lst[0].sg_len));
  2467. /* evaluate command size */
  2468. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) +
  2469. (u16)cmdp->u.raw64.sg_ranz * sizeof(gdth_sg64_str);
  2470. } else {
  2471. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2472. cmdp->u.raw.sdata,cmdp->u.raw.sg_ranz,
  2473. cmdp->u.raw.sg_lst[0].sg_ptr,
  2474. cmdp->u.raw.sg_lst[0].sg_len));
  2475. /* evaluate command size */
  2476. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) +
  2477. (u16)cmdp->u.raw.sg_ranz * sizeof(gdth_sg_str);
  2478. }
  2479. }
  2480. /* check space */
  2481. if (ha->cmd_len & 3)
  2482. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2483. if (ha->cmd_cnt > 0) {
  2484. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2485. ha->ic_all_size) {
  2486. TRACE2(("gdth_fill_raw() DPMEM overflow\n"));
  2487. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2488. return 0;
  2489. }
  2490. }
  2491. /* copy command */
  2492. gdth_copy_command(ha);
  2493. return cmd_index;
  2494. }
  2495. static int gdth_special_cmd(gdth_ha_str *ha, struct scsi_cmnd *scp)
  2496. {
  2497. register gdth_cmd_str *cmdp;
  2498. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  2499. int cmd_index;
  2500. cmdp= ha->pccb;
  2501. TRACE2(("gdth_special_cmd(): "));
  2502. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2503. return 0;
  2504. *cmdp = *cmndinfo->internal_cmd_str;
  2505. cmdp->RequestBuffer = scp;
  2506. /* search free command index */
  2507. if (!(cmd_index=gdth_get_cmd_index(ha))) {
  2508. TRACE(("GDT: No free command index found\n"));
  2509. return 0;
  2510. }
  2511. /* if it's the first command, set command semaphore */
  2512. if (ha->cmd_cnt == 0)
  2513. gdth_set_sema0(ha);
  2514. /* evaluate command size, check space */
  2515. if (cmdp->OpCode == GDT_IOCTL) {
  2516. TRACE2(("IOCTL\n"));
  2517. ha->cmd_len =
  2518. GDTOFFSOF(gdth_cmd_str,u.ioctl.p_param) + sizeof(u64);
  2519. } else if (cmdp->Service == CACHESERVICE) {
  2520. TRACE2(("cache command %d\n",cmdp->OpCode));
  2521. if (ha->cache_feat & GDT_64BIT)
  2522. ha->cmd_len =
  2523. GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) + sizeof(gdth_sg64_str);
  2524. else
  2525. ha->cmd_len =
  2526. GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) + sizeof(gdth_sg_str);
  2527. } else if (cmdp->Service == SCSIRAWSERVICE) {
  2528. TRACE2(("raw command %d\n",cmdp->OpCode));
  2529. if (ha->raw_feat & GDT_64BIT)
  2530. ha->cmd_len =
  2531. GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) + sizeof(gdth_sg64_str);
  2532. else
  2533. ha->cmd_len =
  2534. GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) + sizeof(gdth_sg_str);
  2535. }
  2536. if (ha->cmd_len & 3)
  2537. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2538. if (ha->cmd_cnt > 0) {
  2539. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2540. ha->ic_all_size) {
  2541. TRACE2(("gdth_special_cmd() DPMEM overflow\n"));
  2542. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2543. return 0;
  2544. }
  2545. }
  2546. /* copy command */
  2547. gdth_copy_command(ha);
  2548. return cmd_index;
  2549. }
  2550. /* Controller event handling functions */
  2551. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, u16 source,
  2552. u16 idx, gdth_evt_data *evt)
  2553. {
  2554. gdth_evt_str *e;
  2555. /* no GDTH_LOCK_HA() ! */
  2556. TRACE2(("gdth_store_event() source %d idx %d\n", source, idx));
  2557. if (source == 0) /* no source -> no event */
  2558. return NULL;
  2559. if (ebuffer[elastidx].event_source == source &&
  2560. ebuffer[elastidx].event_idx == idx &&
  2561. ((evt->size != 0 && ebuffer[elastidx].event_data.size != 0 &&
  2562. !memcmp((char *)&ebuffer[elastidx].event_data.eu,
  2563. (char *)&evt->eu, evt->size)) ||
  2564. (evt->size == 0 && ebuffer[elastidx].event_data.size == 0 &&
  2565. !strcmp((char *)&ebuffer[elastidx].event_data.event_string,
  2566. (char *)&evt->event_string)))) {
  2567. e = &ebuffer[elastidx];
  2568. e->last_stamp = (u32)ktime_get_real_seconds();
  2569. ++e->same_count;
  2570. } else {
  2571. if (ebuffer[elastidx].event_source != 0) { /* entry not free ? */
  2572. ++elastidx;
  2573. if (elastidx == MAX_EVENTS)
  2574. elastidx = 0;
  2575. if (elastidx == eoldidx) { /* reached mark ? */
  2576. ++eoldidx;
  2577. if (eoldidx == MAX_EVENTS)
  2578. eoldidx = 0;
  2579. }
  2580. }
  2581. e = &ebuffer[elastidx];
  2582. e->event_source = source;
  2583. e->event_idx = idx;
  2584. e->first_stamp = e->last_stamp = (u32)ktime_get_real_seconds();
  2585. e->same_count = 1;
  2586. e->event_data = *evt;
  2587. e->application = 0;
  2588. }
  2589. return e;
  2590. }
  2591. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr)
  2592. {
  2593. gdth_evt_str *e;
  2594. int eindex;
  2595. unsigned long flags;
  2596. TRACE2(("gdth_read_event() handle %d\n", handle));
  2597. spin_lock_irqsave(&ha->smp_lock, flags);
  2598. if (handle == -1)
  2599. eindex = eoldidx;
  2600. else
  2601. eindex = handle;
  2602. estr->event_source = 0;
  2603. if (eindex < 0 || eindex >= MAX_EVENTS) {
  2604. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2605. return eindex;
  2606. }
  2607. e = &ebuffer[eindex];
  2608. if (e->event_source != 0) {
  2609. if (eindex != elastidx) {
  2610. if (++eindex == MAX_EVENTS)
  2611. eindex = 0;
  2612. } else {
  2613. eindex = -1;
  2614. }
  2615. memcpy(estr, e, sizeof(gdth_evt_str));
  2616. }
  2617. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2618. return eindex;
  2619. }
  2620. static void gdth_readapp_event(gdth_ha_str *ha,
  2621. u8 application, gdth_evt_str *estr)
  2622. {
  2623. gdth_evt_str *e;
  2624. int eindex;
  2625. unsigned long flags;
  2626. u8 found = FALSE;
  2627. TRACE2(("gdth_readapp_event() app. %d\n", application));
  2628. spin_lock_irqsave(&ha->smp_lock, flags);
  2629. eindex = eoldidx;
  2630. for (;;) {
  2631. e = &ebuffer[eindex];
  2632. if (e->event_source == 0)
  2633. break;
  2634. if ((e->application & application) == 0) {
  2635. e->application |= application;
  2636. found = TRUE;
  2637. break;
  2638. }
  2639. if (eindex == elastidx)
  2640. break;
  2641. if (++eindex == MAX_EVENTS)
  2642. eindex = 0;
  2643. }
  2644. if (found)
  2645. memcpy(estr, e, sizeof(gdth_evt_str));
  2646. else
  2647. estr->event_source = 0;
  2648. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2649. }
  2650. static void gdth_clear_events(void)
  2651. {
  2652. TRACE(("gdth_clear_events()"));
  2653. eoldidx = elastidx = 0;
  2654. ebuffer[0].event_source = 0;
  2655. }
  2656. /* SCSI interface functions */
  2657. static irqreturn_t __gdth_interrupt(gdth_ha_str *ha,
  2658. int gdth_from_wait, int* pIndex)
  2659. {
  2660. gdt6m_dpram_str __iomem *dp6m_ptr = NULL;
  2661. gdt6_dpram_str __iomem *dp6_ptr;
  2662. gdt2_dpram_str __iomem *dp2_ptr;
  2663. struct scsi_cmnd *scp;
  2664. int rval, i;
  2665. u8 IStatus;
  2666. u16 Service;
  2667. unsigned long flags = 0;
  2668. #ifdef INT_COAL
  2669. int coalesced = FALSE;
  2670. int next = FALSE;
  2671. gdth_coal_status *pcs = NULL;
  2672. int act_int_coal = 0;
  2673. #endif
  2674. TRACE(("gdth_interrupt() IRQ %d\n", ha->irq));
  2675. /* if polling and not from gdth_wait() -> return */
  2676. if (gdth_polling) {
  2677. if (!gdth_from_wait) {
  2678. return IRQ_HANDLED;
  2679. }
  2680. }
  2681. if (!gdth_polling)
  2682. spin_lock_irqsave(&ha->smp_lock, flags);
  2683. /* search controller */
  2684. IStatus = gdth_get_status(ha);
  2685. if (IStatus == 0) {
  2686. /* spurious interrupt */
  2687. if (!gdth_polling)
  2688. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2689. return IRQ_HANDLED;
  2690. }
  2691. #ifdef GDTH_STATISTICS
  2692. ++act_ints;
  2693. #endif
  2694. #ifdef INT_COAL
  2695. /* See if the fw is returning coalesced status */
  2696. if (IStatus == COALINDEX) {
  2697. /* Coalesced status. Setup the initial status
  2698. buffer pointer and flags */
  2699. pcs = ha->coal_stat;
  2700. coalesced = TRUE;
  2701. next = TRUE;
  2702. }
  2703. do {
  2704. if (coalesced) {
  2705. /* For coalesced requests all status
  2706. information is found in the status buffer */
  2707. IStatus = (u8)(pcs->status & 0xff);
  2708. }
  2709. #endif
  2710. if (ha->type == GDT_EISA) {
  2711. if (IStatus & 0x80) { /* error flag */
  2712. IStatus &= ~0x80;
  2713. ha->status = inw(ha->bmic + MAILBOXREG+8);
  2714. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2715. } else /* no error */
  2716. ha->status = S_OK;
  2717. ha->info = inl(ha->bmic + MAILBOXREG+12);
  2718. ha->service = inw(ha->bmic + MAILBOXREG+10);
  2719. ha->info2 = inl(ha->bmic + MAILBOXREG+4);
  2720. outb(0xff, ha->bmic + EDOORREG); /* acknowledge interrupt */
  2721. outb(0x00, ha->bmic + SEMA1REG); /* reset status semaphore */
  2722. } else if (ha->type == GDT_ISA) {
  2723. dp2_ptr = ha->brd;
  2724. if (IStatus & 0x80) { /* error flag */
  2725. IStatus &= ~0x80;
  2726. ha->status = readw(&dp2_ptr->u.ic.Status);
  2727. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2728. } else /* no error */
  2729. ha->status = S_OK;
  2730. ha->info = readl(&dp2_ptr->u.ic.Info[0]);
  2731. ha->service = readw(&dp2_ptr->u.ic.Service);
  2732. ha->info2 = readl(&dp2_ptr->u.ic.Info[1]);
  2733. writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */
  2734. writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */
  2735. writeb(0, &dp2_ptr->io.Sema1); /* reset status semaphore */
  2736. } else if (ha->type == GDT_PCI) {
  2737. dp6_ptr = ha->brd;
  2738. if (IStatus & 0x80) { /* error flag */
  2739. IStatus &= ~0x80;
  2740. ha->status = readw(&dp6_ptr->u.ic.Status);
  2741. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2742. } else /* no error */
  2743. ha->status = S_OK;
  2744. ha->info = readl(&dp6_ptr->u.ic.Info[0]);
  2745. ha->service = readw(&dp6_ptr->u.ic.Service);
  2746. ha->info2 = readl(&dp6_ptr->u.ic.Info[1]);
  2747. writeb(0xff, &dp6_ptr->io.irqdel); /* acknowledge interrupt */
  2748. writeb(0, &dp6_ptr->u.ic.Cmd_Index);/* reset command index */
  2749. writeb(0, &dp6_ptr->io.Sema1); /* reset status semaphore */
  2750. } else if (ha->type == GDT_PCINEW) {
  2751. if (IStatus & 0x80) { /* error flag */
  2752. IStatus &= ~0x80;
  2753. ha->status = inw(PTR2USHORT(&ha->plx->status));
  2754. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2755. } else
  2756. ha->status = S_OK;
  2757. ha->info = inl(PTR2USHORT(&ha->plx->info[0]));
  2758. ha->service = inw(PTR2USHORT(&ha->plx->service));
  2759. ha->info2 = inl(PTR2USHORT(&ha->plx->info[1]));
  2760. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  2761. outb(0x00, PTR2USHORT(&ha->plx->sema1_reg));
  2762. } else if (ha->type == GDT_PCIMPR) {
  2763. dp6m_ptr = ha->brd;
  2764. if (IStatus & 0x80) { /* error flag */
  2765. IStatus &= ~0x80;
  2766. #ifdef INT_COAL
  2767. if (coalesced)
  2768. ha->status = pcs->ext_status & 0xffff;
  2769. else
  2770. #endif
  2771. ha->status = readw(&dp6m_ptr->i960r.status);
  2772. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2773. } else /* no error */
  2774. ha->status = S_OK;
  2775. #ifdef INT_COAL
  2776. /* get information */
  2777. if (coalesced) {
  2778. ha->info = pcs->info0;
  2779. ha->info2 = pcs->info1;
  2780. ha->service = (pcs->ext_status >> 16) & 0xffff;
  2781. } else
  2782. #endif
  2783. {
  2784. ha->info = readl(&dp6m_ptr->i960r.info[0]);
  2785. ha->service = readw(&dp6m_ptr->i960r.service);
  2786. ha->info2 = readl(&dp6m_ptr->i960r.info[1]);
  2787. }
  2788. /* event string */
  2789. if (IStatus == ASYNCINDEX) {
  2790. if (ha->service != SCREENSERVICE &&
  2791. (ha->fw_vers & 0xff) >= 0x1a) {
  2792. ha->dvr.severity = readb
  2793. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.severity);
  2794. for (i = 0; i < 256; ++i) {
  2795. ha->dvr.event_string[i] = readb
  2796. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.evt_str[i]);
  2797. if (ha->dvr.event_string[i] == 0)
  2798. break;
  2799. }
  2800. }
  2801. }
  2802. #ifdef INT_COAL
  2803. /* Make sure that non coalesced interrupts get cleared
  2804. before being handled by gdth_async_event/gdth_sync_event */
  2805. if (!coalesced)
  2806. #endif
  2807. {
  2808. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  2809. writeb(0, &dp6m_ptr->i960r.sema1_reg);
  2810. }
  2811. } else {
  2812. TRACE2(("gdth_interrupt() unknown controller type\n"));
  2813. if (!gdth_polling)
  2814. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2815. return IRQ_HANDLED;
  2816. }
  2817. TRACE(("gdth_interrupt() index %d stat %d info %d\n",
  2818. IStatus,ha->status,ha->info));
  2819. if (gdth_from_wait) {
  2820. *pIndex = (int)IStatus;
  2821. }
  2822. if (IStatus == ASYNCINDEX) {
  2823. TRACE2(("gdth_interrupt() async. event\n"));
  2824. gdth_async_event(ha);
  2825. if (!gdth_polling)
  2826. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2827. gdth_next(ha);
  2828. return IRQ_HANDLED;
  2829. }
  2830. if (IStatus == SPEZINDEX) {
  2831. TRACE2(("Service unknown or not initialized !\n"));
  2832. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  2833. ha->dvr.eu.driver.ionode = ha->hanum;
  2834. gdth_store_event(ha, ES_DRIVER, 4, &ha->dvr);
  2835. if (!gdth_polling)
  2836. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2837. return IRQ_HANDLED;
  2838. }
  2839. scp = ha->cmd_tab[IStatus-2].cmnd;
  2840. Service = ha->cmd_tab[IStatus-2].service;
  2841. ha->cmd_tab[IStatus-2].cmnd = UNUSED_CMND;
  2842. if (scp == UNUSED_CMND) {
  2843. TRACE2(("gdth_interrupt() index to unused command (%d)\n",IStatus));
  2844. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  2845. ha->dvr.eu.driver.ionode = ha->hanum;
  2846. ha->dvr.eu.driver.index = IStatus;
  2847. gdth_store_event(ha, ES_DRIVER, 1, &ha->dvr);
  2848. if (!gdth_polling)
  2849. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2850. return IRQ_HANDLED;
  2851. }
  2852. if (scp == INTERNAL_CMND) {
  2853. TRACE(("gdth_interrupt() answer to internal command\n"));
  2854. if (!gdth_polling)
  2855. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2856. return IRQ_HANDLED;
  2857. }
  2858. TRACE(("gdth_interrupt() sync. status\n"));
  2859. rval = gdth_sync_event(ha,Service,IStatus,scp);
  2860. if (!gdth_polling)
  2861. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2862. if (rval == 2) {
  2863. gdth_putq(ha, scp, gdth_cmnd_priv(scp)->priority);
  2864. } else if (rval == 1) {
  2865. gdth_scsi_done(scp);
  2866. }
  2867. #ifdef INT_COAL
  2868. if (coalesced) {
  2869. /* go to the next status in the status buffer */
  2870. ++pcs;
  2871. #ifdef GDTH_STATISTICS
  2872. ++act_int_coal;
  2873. if (act_int_coal > max_int_coal) {
  2874. max_int_coal = act_int_coal;
  2875. printk("GDT: max_int_coal = %d\n",(u16)max_int_coal);
  2876. }
  2877. #endif
  2878. /* see if there is another status */
  2879. if (pcs->status == 0)
  2880. /* Stop the coalesce loop */
  2881. next = FALSE;
  2882. }
  2883. } while (next);
  2884. /* coalescing only for new GDT_PCIMPR controllers available */
  2885. if (ha->type == GDT_PCIMPR && coalesced) {
  2886. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  2887. writeb(0, &dp6m_ptr->i960r.sema1_reg);
  2888. }
  2889. #endif
  2890. gdth_next(ha);
  2891. return IRQ_HANDLED;
  2892. }
  2893. static irqreturn_t gdth_interrupt(int irq, void *dev_id)
  2894. {
  2895. gdth_ha_str *ha = dev_id;
  2896. return __gdth_interrupt(ha, false, NULL);
  2897. }
  2898. static int gdth_sync_event(gdth_ha_str *ha, int service, u8 index,
  2899. struct scsi_cmnd *scp)
  2900. {
  2901. gdth_msg_str *msg;
  2902. gdth_cmd_str *cmdp;
  2903. u8 b, t;
  2904. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  2905. cmdp = ha->pccb;
  2906. TRACE(("gdth_sync_event() serv %d status %d\n",
  2907. service,ha->status));
  2908. if (service == SCREENSERVICE) {
  2909. msg = ha->pmsg;
  2910. TRACE(("len: %d, answer: %d, ext: %d, alen: %d\n",
  2911. msg->msg_len,msg->msg_answer,msg->msg_ext,msg->msg_alen));
  2912. if (msg->msg_len > MSGLEN+1)
  2913. msg->msg_len = MSGLEN+1;
  2914. if (msg->msg_len)
  2915. if (!(msg->msg_answer && msg->msg_ext)) {
  2916. msg->msg_text[msg->msg_len] = '\0';
  2917. printk("%s",msg->msg_text);
  2918. }
  2919. if (msg->msg_ext && !msg->msg_answer) {
  2920. while (gdth_test_busy(ha))
  2921. gdth_delay(0);
  2922. cmdp->Service = SCREENSERVICE;
  2923. cmdp->RequestBuffer = SCREEN_CMND;
  2924. gdth_get_cmd_index(ha);
  2925. gdth_set_sema0(ha);
  2926. cmdp->OpCode = GDT_READ;
  2927. cmdp->BoardNode = LOCALBOARD;
  2928. cmdp->u.screen.reserved = 0;
  2929. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  2930. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  2931. ha->cmd_offs_dpmem = 0;
  2932. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  2933. + sizeof(u64);
  2934. ha->cmd_cnt = 0;
  2935. gdth_copy_command(ha);
  2936. gdth_release_event(ha);
  2937. return 0;
  2938. }
  2939. if (msg->msg_answer && msg->msg_alen) {
  2940. /* default answers (getchar() not possible) */
  2941. if (msg->msg_alen == 1) {
  2942. msg->msg_alen = 0;
  2943. msg->msg_len = 1;
  2944. msg->msg_text[0] = 0;
  2945. } else {
  2946. msg->msg_alen -= 2;
  2947. msg->msg_len = 2;
  2948. msg->msg_text[0] = 1;
  2949. msg->msg_text[1] = 0;
  2950. }
  2951. msg->msg_ext = 0;
  2952. msg->msg_answer = 0;
  2953. while (gdth_test_busy(ha))
  2954. gdth_delay(0);
  2955. cmdp->Service = SCREENSERVICE;
  2956. cmdp->RequestBuffer = SCREEN_CMND;
  2957. gdth_get_cmd_index(ha);
  2958. gdth_set_sema0(ha);
  2959. cmdp->OpCode = GDT_WRITE;
  2960. cmdp->BoardNode = LOCALBOARD;
  2961. cmdp->u.screen.reserved = 0;
  2962. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  2963. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  2964. ha->cmd_offs_dpmem = 0;
  2965. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  2966. + sizeof(u64);
  2967. ha->cmd_cnt = 0;
  2968. gdth_copy_command(ha);
  2969. gdth_release_event(ha);
  2970. return 0;
  2971. }
  2972. printk("\n");
  2973. } else {
  2974. b = scp->device->channel;
  2975. t = scp->device->id;
  2976. if (cmndinfo->OpCode == -1 && b != ha->virt_bus) {
  2977. ha->raw[BUS_L2P(ha,b)].io_cnt[t]--;
  2978. }
  2979. /* cache or raw service */
  2980. if (ha->status == S_BSY) {
  2981. TRACE2(("Controller busy -> retry !\n"));
  2982. if (cmndinfo->OpCode == GDT_MOUNT)
  2983. cmndinfo->OpCode = GDT_CLUST_INFO;
  2984. /* retry */
  2985. return 2;
  2986. }
  2987. if (scsi_bufflen(scp))
  2988. pci_unmap_sg(ha->pdev, scsi_sglist(scp), scsi_sg_count(scp),
  2989. cmndinfo->dma_dir);
  2990. if (cmndinfo->sense_paddr)
  2991. pci_unmap_page(ha->pdev, cmndinfo->sense_paddr, 16,
  2992. PCI_DMA_FROMDEVICE);
  2993. if (ha->status == S_OK) {
  2994. cmndinfo->status = S_OK;
  2995. cmndinfo->info = ha->info;
  2996. if (cmndinfo->OpCode != -1) {
  2997. TRACE2(("gdth_sync_event(): special cmd 0x%x OK\n",
  2998. cmndinfo->OpCode));
  2999. /* special commands GDT_CLUST_INFO/GDT_MOUNT ? */
  3000. if (cmndinfo->OpCode == GDT_CLUST_INFO) {
  3001. ha->hdr[t].cluster_type = (u8)ha->info;
  3002. if (!(ha->hdr[t].cluster_type &
  3003. CLUSTER_MOUNTED)) {
  3004. /* NOT MOUNTED -> MOUNT */
  3005. cmndinfo->OpCode = GDT_MOUNT;
  3006. if (ha->hdr[t].cluster_type &
  3007. CLUSTER_RESERVED) {
  3008. /* cluster drive RESERVED (on the other node) */
  3009. cmndinfo->phase = -2; /* reservation conflict */
  3010. }
  3011. } else {
  3012. cmndinfo->OpCode = -1;
  3013. }
  3014. } else {
  3015. if (cmndinfo->OpCode == GDT_MOUNT) {
  3016. ha->hdr[t].cluster_type |= CLUSTER_MOUNTED;
  3017. ha->hdr[t].media_changed = TRUE;
  3018. } else if (cmndinfo->OpCode == GDT_UNMOUNT) {
  3019. ha->hdr[t].cluster_type &= ~CLUSTER_MOUNTED;
  3020. ha->hdr[t].media_changed = TRUE;
  3021. }
  3022. cmndinfo->OpCode = -1;
  3023. }
  3024. /* retry */
  3025. cmndinfo->priority = HIGH_PRI;
  3026. return 2;
  3027. } else {
  3028. /* RESERVE/RELEASE ? */
  3029. if (scp->cmnd[0] == RESERVE) {
  3030. ha->hdr[t].cluster_type |= CLUSTER_RESERVED;
  3031. } else if (scp->cmnd[0] == RELEASE) {
  3032. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3033. }
  3034. scp->result = DID_OK << 16;
  3035. scp->sense_buffer[0] = 0;
  3036. }
  3037. } else {
  3038. cmndinfo->status = ha->status;
  3039. cmndinfo->info = ha->info;
  3040. if (cmndinfo->OpCode != -1) {
  3041. TRACE2(("gdth_sync_event(): special cmd 0x%x error 0x%x\n",
  3042. cmndinfo->OpCode, ha->status));
  3043. if (cmndinfo->OpCode == GDT_SCAN_START ||
  3044. cmndinfo->OpCode == GDT_SCAN_END) {
  3045. cmndinfo->OpCode = -1;
  3046. /* retry */
  3047. cmndinfo->priority = HIGH_PRI;
  3048. return 2;
  3049. }
  3050. memset((char*)scp->sense_buffer,0,16);
  3051. scp->sense_buffer[0] = 0x70;
  3052. scp->sense_buffer[2] = NOT_READY;
  3053. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3054. } else if (service == CACHESERVICE) {
  3055. if (ha->status == S_CACHE_UNKNOWN &&
  3056. (ha->hdr[t].cluster_type &
  3057. CLUSTER_RESERVE_STATE) == CLUSTER_RESERVE_STATE) {
  3058. /* bus reset -> force GDT_CLUST_INFO */
  3059. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3060. }
  3061. memset((char*)scp->sense_buffer,0,16);
  3062. if (ha->status == (u16)S_CACHE_RESERV) {
  3063. scp->result = (DID_OK << 16) | (RESERVATION_CONFLICT << 1);
  3064. } else {
  3065. scp->sense_buffer[0] = 0x70;
  3066. scp->sense_buffer[2] = NOT_READY;
  3067. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3068. }
  3069. if (!cmndinfo->internal_command) {
  3070. ha->dvr.size = sizeof(ha->dvr.eu.sync);
  3071. ha->dvr.eu.sync.ionode = ha->hanum;
  3072. ha->dvr.eu.sync.service = service;
  3073. ha->dvr.eu.sync.status = ha->status;
  3074. ha->dvr.eu.sync.info = ha->info;
  3075. ha->dvr.eu.sync.hostdrive = t;
  3076. if (ha->status >= 0x8000)
  3077. gdth_store_event(ha, ES_SYNC, 0, &ha->dvr);
  3078. else
  3079. gdth_store_event(ha, ES_SYNC, service, &ha->dvr);
  3080. }
  3081. } else {
  3082. /* sense buffer filled from controller firmware (DMA) */
  3083. if (ha->status != S_RAW_SCSI || ha->info >= 0x100) {
  3084. scp->result = DID_BAD_TARGET << 16;
  3085. } else {
  3086. scp->result = (DID_OK << 16) | ha->info;
  3087. }
  3088. }
  3089. }
  3090. if (!cmndinfo->wait_for_completion)
  3091. cmndinfo->wait_for_completion++;
  3092. else
  3093. return 1;
  3094. }
  3095. return 0;
  3096. }
  3097. static char *async_cache_tab[] = {
  3098. /* 0*/ "\011\000\002\002\002\004\002\006\004"
  3099. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3100. /* 1*/ "\011\000\002\002\002\004\002\006\004"
  3101. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3102. /* 2*/ "\005\000\002\006\004"
  3103. "GDT HA %u, Host Drive %lu not ready",
  3104. /* 3*/ "\005\000\002\006\004"
  3105. "GDT HA %u, Host Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3106. /* 4*/ "\005\000\002\006\004"
  3107. "GDT HA %u, mirror update on Host Drive %lu failed",
  3108. /* 5*/ "\005\000\002\006\004"
  3109. "GDT HA %u, Mirror Drive %lu failed",
  3110. /* 6*/ "\005\000\002\006\004"
  3111. "GDT HA %u, Mirror Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3112. /* 7*/ "\005\000\002\006\004"
  3113. "GDT HA %u, Host Drive %lu write protected",
  3114. /* 8*/ "\005\000\002\006\004"
  3115. "GDT HA %u, media changed in Host Drive %lu",
  3116. /* 9*/ "\005\000\002\006\004"
  3117. "GDT HA %u, Host Drive %lu is offline",
  3118. /*10*/ "\005\000\002\006\004"
  3119. "GDT HA %u, media change of Mirror Drive %lu",
  3120. /*11*/ "\005\000\002\006\004"
  3121. "GDT HA %u, Mirror Drive %lu is write protected",
  3122. /*12*/ "\005\000\002\006\004"
  3123. "GDT HA %u, general error on Host Drive %lu. Please check the devices of this drive!",
  3124. /*13*/ "\007\000\002\006\002\010\002"
  3125. "GDT HA %u, Array Drive %u: Cache Drive %u failed",
  3126. /*14*/ "\005\000\002\006\002"
  3127. "GDT HA %u, Array Drive %u: FAIL state entered",
  3128. /*15*/ "\005\000\002\006\002"
  3129. "GDT HA %u, Array Drive %u: error",
  3130. /*16*/ "\007\000\002\006\002\010\002"
  3131. "GDT HA %u, Array Drive %u: failed drive replaced by Cache Drive %u",
  3132. /*17*/ "\005\000\002\006\002"
  3133. "GDT HA %u, Array Drive %u: parity build failed",
  3134. /*18*/ "\005\000\002\006\002"
  3135. "GDT HA %u, Array Drive %u: drive rebuild failed",
  3136. /*19*/ "\005\000\002\010\002"
  3137. "GDT HA %u, Test of Hot Fix %u failed",
  3138. /*20*/ "\005\000\002\006\002"
  3139. "GDT HA %u, Array Drive %u: drive build finished successfully",
  3140. /*21*/ "\005\000\002\006\002"
  3141. "GDT HA %u, Array Drive %u: drive rebuild finished successfully",
  3142. /*22*/ "\007\000\002\006\002\010\002"
  3143. "GDT HA %u, Array Drive %u: Hot Fix %u activated",
  3144. /*23*/ "\005\000\002\006\002"
  3145. "GDT HA %u, Host Drive %u: processing of i/o aborted due to serious drive error",
  3146. /*24*/ "\005\000\002\010\002"
  3147. "GDT HA %u, mirror update on Cache Drive %u completed",
  3148. /*25*/ "\005\000\002\010\002"
  3149. "GDT HA %u, mirror update on Cache Drive %lu failed",
  3150. /*26*/ "\005\000\002\006\002"
  3151. "GDT HA %u, Array Drive %u: drive rebuild started",
  3152. /*27*/ "\005\000\002\012\001"
  3153. "GDT HA %u, Fault bus %u: SHELF OK detected",
  3154. /*28*/ "\005\000\002\012\001"
  3155. "GDT HA %u, Fault bus %u: SHELF not OK detected",
  3156. /*29*/ "\007\000\002\012\001\013\001"
  3157. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug started",
  3158. /*30*/ "\007\000\002\012\001\013\001"
  3159. "GDT HA %u, Fault bus %u, ID %u: new disk detected",
  3160. /*31*/ "\007\000\002\012\001\013\001"
  3161. "GDT HA %u, Fault bus %u, ID %u: old disk detected",
  3162. /*32*/ "\007\000\002\012\001\013\001"
  3163. "GDT HA %u, Fault bus %u, ID %u: plugging an active disk is invalid",
  3164. /*33*/ "\007\000\002\012\001\013\001"
  3165. "GDT HA %u, Fault bus %u, ID %u: invalid device detected",
  3166. /*34*/ "\011\000\002\012\001\013\001\006\004"
  3167. "GDT HA %u, Fault bus %u, ID %u: insufficient disk capacity (%lu MB required)",
  3168. /*35*/ "\007\000\002\012\001\013\001"
  3169. "GDT HA %u, Fault bus %u, ID %u: disk write protected",
  3170. /*36*/ "\007\000\002\012\001\013\001"
  3171. "GDT HA %u, Fault bus %u, ID %u: disk not available",
  3172. /*37*/ "\007\000\002\012\001\006\004"
  3173. "GDT HA %u, Fault bus %u: swap detected (%lu)",
  3174. /*38*/ "\007\000\002\012\001\013\001"
  3175. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug finished successfully",
  3176. /*39*/ "\007\000\002\012\001\013\001"
  3177. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted due to user Hot Plug",
  3178. /*40*/ "\007\000\002\012\001\013\001"
  3179. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted",
  3180. /*41*/ "\007\000\002\012\001\013\001"
  3181. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug for Hot Fix started",
  3182. /*42*/ "\005\000\002\006\002"
  3183. "GDT HA %u, Array Drive %u: drive build started",
  3184. /*43*/ "\003\000\002"
  3185. "GDT HA %u, DRAM parity error detected",
  3186. /*44*/ "\005\000\002\006\002"
  3187. "GDT HA %u, Mirror Drive %u: update started",
  3188. /*45*/ "\007\000\002\006\002\010\002"
  3189. "GDT HA %u, Mirror Drive %u: Hot Fix %u activated",
  3190. /*46*/ "\005\000\002\006\002"
  3191. "GDT HA %u, Array Drive %u: no matching Pool Hot Fix Drive available",
  3192. /*47*/ "\005\000\002\006\002"
  3193. "GDT HA %u, Array Drive %u: Pool Hot Fix Drive available",
  3194. /*48*/ "\005\000\002\006\002"
  3195. "GDT HA %u, Mirror Drive %u: no matching Pool Hot Fix Drive available",
  3196. /*49*/ "\005\000\002\006\002"
  3197. "GDT HA %u, Mirror Drive %u: Pool Hot Fix Drive available",
  3198. /*50*/ "\007\000\002\012\001\013\001"
  3199. "GDT HA %u, SCSI bus %u, ID %u: IGNORE_WIDE_RESIDUE message received",
  3200. /*51*/ "\005\000\002\006\002"
  3201. "GDT HA %u, Array Drive %u: expand started",
  3202. /*52*/ "\005\000\002\006\002"
  3203. "GDT HA %u, Array Drive %u: expand finished successfully",
  3204. /*53*/ "\005\000\002\006\002"
  3205. "GDT HA %u, Array Drive %u: expand failed",
  3206. /*54*/ "\003\000\002"
  3207. "GDT HA %u, CPU temperature critical",
  3208. /*55*/ "\003\000\002"
  3209. "GDT HA %u, CPU temperature OK",
  3210. /*56*/ "\005\000\002\006\004"
  3211. "GDT HA %u, Host drive %lu created",
  3212. /*57*/ "\005\000\002\006\002"
  3213. "GDT HA %u, Array Drive %u: expand restarted",
  3214. /*58*/ "\005\000\002\006\002"
  3215. "GDT HA %u, Array Drive %u: expand stopped",
  3216. /*59*/ "\005\000\002\010\002"
  3217. "GDT HA %u, Mirror Drive %u: drive build quited",
  3218. /*60*/ "\005\000\002\006\002"
  3219. "GDT HA %u, Array Drive %u: parity build quited",
  3220. /*61*/ "\005\000\002\006\002"
  3221. "GDT HA %u, Array Drive %u: drive rebuild quited",
  3222. /*62*/ "\005\000\002\006\002"
  3223. "GDT HA %u, Array Drive %u: parity verify started",
  3224. /*63*/ "\005\000\002\006\002"
  3225. "GDT HA %u, Array Drive %u: parity verify done",
  3226. /*64*/ "\005\000\002\006\002"
  3227. "GDT HA %u, Array Drive %u: parity verify failed",
  3228. /*65*/ "\005\000\002\006\002"
  3229. "GDT HA %u, Array Drive %u: parity error detected",
  3230. /*66*/ "\005\000\002\006\002"
  3231. "GDT HA %u, Array Drive %u: parity verify quited",
  3232. /*67*/ "\005\000\002\006\002"
  3233. "GDT HA %u, Host Drive %u reserved",
  3234. /*68*/ "\005\000\002\006\002"
  3235. "GDT HA %u, Host Drive %u mounted and released",
  3236. /*69*/ "\005\000\002\006\002"
  3237. "GDT HA %u, Host Drive %u released",
  3238. /*70*/ "\003\000\002"
  3239. "GDT HA %u, DRAM error detected and corrected with ECC",
  3240. /*71*/ "\003\000\002"
  3241. "GDT HA %u, Uncorrectable DRAM error detected with ECC",
  3242. /*72*/ "\011\000\002\012\001\013\001\014\001"
  3243. "GDT HA %u, SCSI bus %u, ID %u, LUN %u: reassigning block",
  3244. /*73*/ "\005\000\002\006\002"
  3245. "GDT HA %u, Host drive %u resetted locally",
  3246. /*74*/ "\005\000\002\006\002"
  3247. "GDT HA %u, Host drive %u resetted remotely",
  3248. /*75*/ "\003\000\002"
  3249. "GDT HA %u, async. status 75 unknown",
  3250. };
  3251. static int gdth_async_event(gdth_ha_str *ha)
  3252. {
  3253. gdth_cmd_str *cmdp;
  3254. int cmd_index;
  3255. cmdp= ha->pccb;
  3256. TRACE2(("gdth_async_event() ha %d serv %d\n",
  3257. ha->hanum, ha->service));
  3258. if (ha->service == SCREENSERVICE) {
  3259. if (ha->status == MSG_REQUEST) {
  3260. while (gdth_test_busy(ha))
  3261. gdth_delay(0);
  3262. cmdp->Service = SCREENSERVICE;
  3263. cmdp->RequestBuffer = SCREEN_CMND;
  3264. cmd_index = gdth_get_cmd_index(ha);
  3265. gdth_set_sema0(ha);
  3266. cmdp->OpCode = GDT_READ;
  3267. cmdp->BoardNode = LOCALBOARD;
  3268. cmdp->u.screen.reserved = 0;
  3269. cmdp->u.screen.su.msg.msg_handle= MSG_INV_HANDLE;
  3270. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3271. ha->cmd_offs_dpmem = 0;
  3272. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3273. + sizeof(u64);
  3274. ha->cmd_cnt = 0;
  3275. gdth_copy_command(ha);
  3276. if (ha->type == GDT_EISA)
  3277. printk("[EISA slot %d] ",(u16)ha->brd_phys);
  3278. else if (ha->type == GDT_ISA)
  3279. printk("[DPMEM 0x%4X] ",(u16)ha->brd_phys);
  3280. else
  3281. printk("[PCI %d/%d] ",(u16)(ha->brd_phys>>8),
  3282. (u16)((ha->brd_phys>>3)&0x1f));
  3283. gdth_release_event(ha);
  3284. }
  3285. } else {
  3286. if (ha->type == GDT_PCIMPR &&
  3287. (ha->fw_vers & 0xff) >= 0x1a) {
  3288. ha->dvr.size = 0;
  3289. ha->dvr.eu.async.ionode = ha->hanum;
  3290. ha->dvr.eu.async.status = ha->status;
  3291. /* severity and event_string already set! */
  3292. } else {
  3293. ha->dvr.size = sizeof(ha->dvr.eu.async);
  3294. ha->dvr.eu.async.ionode = ha->hanum;
  3295. ha->dvr.eu.async.service = ha->service;
  3296. ha->dvr.eu.async.status = ha->status;
  3297. ha->dvr.eu.async.info = ha->info;
  3298. *(u32 *)ha->dvr.eu.async.scsi_coord = ha->info2;
  3299. }
  3300. gdth_store_event( ha, ES_ASYNC, ha->service, &ha->dvr );
  3301. gdth_log_event( &ha->dvr, NULL );
  3302. /* new host drive from expand? */
  3303. if (ha->service == CACHESERVICE && ha->status == 56) {
  3304. TRACE2(("gdth_async_event(): new host drive %d created\n",
  3305. (u16)ha->info));
  3306. /* gdth_analyse_hdrive(hanum, (u16)ha->info); */
  3307. }
  3308. }
  3309. return 1;
  3310. }
  3311. static void gdth_log_event(gdth_evt_data *dvr, char *buffer)
  3312. {
  3313. gdth_stackframe stack;
  3314. char *f = NULL;
  3315. int i,j;
  3316. TRACE2(("gdth_log_event()\n"));
  3317. if (dvr->size == 0) {
  3318. if (buffer == NULL) {
  3319. printk("Adapter %d: %s\n",dvr->eu.async.ionode,dvr->event_string);
  3320. } else {
  3321. sprintf(buffer,"Adapter %d: %s\n",
  3322. dvr->eu.async.ionode,dvr->event_string);
  3323. }
  3324. } else if (dvr->eu.async.service == CACHESERVICE &&
  3325. INDEX_OK(dvr->eu.async.status, async_cache_tab)) {
  3326. TRACE2(("GDT: Async. event cache service, event no.: %d\n",
  3327. dvr->eu.async.status));
  3328. f = async_cache_tab[dvr->eu.async.status];
  3329. /* i: parameter to push, j: stack element to fill */
  3330. for (j=0,i=1; i < f[0]; i+=2) {
  3331. switch (f[i+1]) {
  3332. case 4:
  3333. stack.b[j++] = *(u32*)&dvr->eu.stream[(int)f[i]];
  3334. break;
  3335. case 2:
  3336. stack.b[j++] = *(u16*)&dvr->eu.stream[(int)f[i]];
  3337. break;
  3338. case 1:
  3339. stack.b[j++] = *(u8*)&dvr->eu.stream[(int)f[i]];
  3340. break;
  3341. default:
  3342. break;
  3343. }
  3344. }
  3345. if (buffer == NULL) {
  3346. printk(&f[(int)f[0]],stack);
  3347. printk("\n");
  3348. } else {
  3349. sprintf(buffer,&f[(int)f[0]],stack);
  3350. }
  3351. } else {
  3352. if (buffer == NULL) {
  3353. printk("GDT HA %u, Unknown async. event service %d event no. %d\n",
  3354. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3355. } else {
  3356. sprintf(buffer,"GDT HA %u, Unknown async. event service %d event no. %d",
  3357. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3358. }
  3359. }
  3360. }
  3361. #ifdef GDTH_STATISTICS
  3362. static u8 gdth_timer_running;
  3363. static void gdth_timeout(struct timer_list *unused)
  3364. {
  3365. u32 i;
  3366. struct scsi_cmnd *nscp;
  3367. gdth_ha_str *ha;
  3368. unsigned long flags;
  3369. if(unlikely(list_empty(&gdth_instances))) {
  3370. gdth_timer_running = 0;
  3371. return;
  3372. }
  3373. ha = list_first_entry(&gdth_instances, gdth_ha_str, list);
  3374. spin_lock_irqsave(&ha->smp_lock, flags);
  3375. for (act_stats=0,i=0; i<GDTH_MAXCMDS; ++i)
  3376. if (ha->cmd_tab[i].cmnd != UNUSED_CMND)
  3377. ++act_stats;
  3378. for (act_rq=0,
  3379. nscp=ha->req_first; nscp; nscp=(struct scsi_cmnd*)nscp->SCp.ptr)
  3380. ++act_rq;
  3381. TRACE2(("gdth_to(): ints %d, ios %d, act_stats %d, act_rq %d\n",
  3382. act_ints, act_ios, act_stats, act_rq));
  3383. act_ints = act_ios = 0;
  3384. gdth_timer.expires = jiffies + 30 * HZ;
  3385. add_timer(&gdth_timer);
  3386. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3387. }
  3388. static void gdth_timer_init(void)
  3389. {
  3390. if (gdth_timer_running)
  3391. return;
  3392. gdth_timer_running = 1;
  3393. TRACE2(("gdth_detect(): Initializing timer !\n"));
  3394. gdth_timer.expires = jiffies + HZ;
  3395. add_timer(&gdth_timer);
  3396. }
  3397. #else
  3398. static inline void gdth_timer_init(void)
  3399. {
  3400. }
  3401. #endif
  3402. static void __init internal_setup(char *str,int *ints)
  3403. {
  3404. int i, argc;
  3405. char *cur_str, *argv;
  3406. TRACE2(("internal_setup() str %s ints[0] %d\n",
  3407. str ? str:"NULL", ints ? ints[0]:0));
  3408. /* read irq[] from ints[] */
  3409. if (ints) {
  3410. argc = ints[0];
  3411. if (argc > 0) {
  3412. if (argc > MAXHA)
  3413. argc = MAXHA;
  3414. for (i = 0; i < argc; ++i)
  3415. irq[i] = ints[i+1];
  3416. }
  3417. }
  3418. /* analyse string */
  3419. argv = str;
  3420. while (argv && (cur_str = strchr(argv, ':'))) {
  3421. int val = 0, c = *++cur_str;
  3422. if (c == 'n' || c == 'N')
  3423. val = 0;
  3424. else if (c == 'y' || c == 'Y')
  3425. val = 1;
  3426. else
  3427. val = (int)simple_strtoul(cur_str, NULL, 0);
  3428. if (!strncmp(argv, "disable:", 8))
  3429. disable = val;
  3430. else if (!strncmp(argv, "reserve_mode:", 13))
  3431. reserve_mode = val;
  3432. else if (!strncmp(argv, "reverse_scan:", 13))
  3433. reverse_scan = val;
  3434. else if (!strncmp(argv, "hdr_channel:", 12))
  3435. hdr_channel = val;
  3436. else if (!strncmp(argv, "max_ids:", 8))
  3437. max_ids = val;
  3438. else if (!strncmp(argv, "rescan:", 7))
  3439. rescan = val;
  3440. else if (!strncmp(argv, "shared_access:", 14))
  3441. shared_access = val;
  3442. else if (!strncmp(argv, "probe_eisa_isa:", 15))
  3443. probe_eisa_isa = val;
  3444. else if (!strncmp(argv, "reserve_list:", 13)) {
  3445. reserve_list[0] = val;
  3446. for (i = 1; i < MAX_RES_ARGS; i++) {
  3447. cur_str = strchr(cur_str, ',');
  3448. if (!cur_str)
  3449. break;
  3450. if (!isdigit((int)*++cur_str)) {
  3451. --cur_str;
  3452. break;
  3453. }
  3454. reserve_list[i] =
  3455. (int)simple_strtoul(cur_str, NULL, 0);
  3456. }
  3457. if (!cur_str)
  3458. break;
  3459. argv = ++cur_str;
  3460. continue;
  3461. }
  3462. if ((argv = strchr(argv, ',')))
  3463. ++argv;
  3464. }
  3465. }
  3466. int __init option_setup(char *str)
  3467. {
  3468. int ints[MAXHA];
  3469. char *cur = str;
  3470. int i = 1;
  3471. TRACE2(("option_setup() str %s\n", str ? str:"NULL"));
  3472. while (cur && isdigit(*cur) && i < MAXHA) {
  3473. ints[i++] = simple_strtoul(cur, NULL, 0);
  3474. if ((cur = strchr(cur, ',')) != NULL) cur++;
  3475. }
  3476. ints[0] = i - 1;
  3477. internal_setup(cur, ints);
  3478. return 1;
  3479. }
  3480. static const char *gdth_ctr_name(gdth_ha_str *ha)
  3481. {
  3482. TRACE2(("gdth_ctr_name()\n"));
  3483. if (ha->type == GDT_EISA) {
  3484. switch (ha->stype) {
  3485. case GDT3_ID:
  3486. return("GDT3000/3020");
  3487. case GDT3A_ID:
  3488. return("GDT3000A/3020A/3050A");
  3489. case GDT3B_ID:
  3490. return("GDT3000B/3010A");
  3491. }
  3492. } else if (ha->type == GDT_ISA) {
  3493. return("GDT2000/2020");
  3494. } else if (ha->type == GDT_PCI) {
  3495. switch (ha->pdev->device) {
  3496. case PCI_DEVICE_ID_VORTEX_GDT60x0:
  3497. return("GDT6000/6020/6050");
  3498. case PCI_DEVICE_ID_VORTEX_GDT6000B:
  3499. return("GDT6000B/6010");
  3500. }
  3501. }
  3502. /* new controllers (GDT_PCINEW, GDT_PCIMPR, ..) use board_info IOCTL! */
  3503. return("");
  3504. }
  3505. static const char *gdth_info(struct Scsi_Host *shp)
  3506. {
  3507. gdth_ha_str *ha = shost_priv(shp);
  3508. TRACE2(("gdth_info()\n"));
  3509. return ((const char *)ha->binfo.type_string);
  3510. }
  3511. static enum blk_eh_timer_return gdth_timed_out(struct scsi_cmnd *scp)
  3512. {
  3513. gdth_ha_str *ha = shost_priv(scp->device->host);
  3514. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  3515. u8 b, t;
  3516. unsigned long flags;
  3517. enum blk_eh_timer_return retval = BLK_EH_DONE;
  3518. TRACE(("%s() cmd 0x%x\n", scp->cmnd[0], __func__));
  3519. b = scp->device->channel;
  3520. t = scp->device->id;
  3521. /*
  3522. * We don't really honor the command timeout, but we try to
  3523. * honor 6 times of the actual command timeout! So reset the
  3524. * timer if this is less than 6th timeout on this command!
  3525. */
  3526. if (++cmndinfo->timeout_count < 6)
  3527. retval = BLK_EH_RESET_TIMER;
  3528. /* Reset the timeout if it is locked IO */
  3529. spin_lock_irqsave(&ha->smp_lock, flags);
  3530. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha, b)].lock) ||
  3531. (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock)) {
  3532. TRACE2(("%s(): locked IO, reset timeout\n", __func__));
  3533. retval = BLK_EH_RESET_TIMER;
  3534. }
  3535. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3536. return retval;
  3537. }
  3538. static int gdth_eh_bus_reset(struct scsi_cmnd *scp)
  3539. {
  3540. gdth_ha_str *ha = shost_priv(scp->device->host);
  3541. int i;
  3542. unsigned long flags;
  3543. struct scsi_cmnd *cmnd;
  3544. u8 b;
  3545. TRACE2(("gdth_eh_bus_reset()\n"));
  3546. b = scp->device->channel;
  3547. /* clear command tab */
  3548. spin_lock_irqsave(&ha->smp_lock, flags);
  3549. for (i = 0; i < GDTH_MAXCMDS; ++i) {
  3550. cmnd = ha->cmd_tab[i].cmnd;
  3551. if (!SPECIAL_SCP(cmnd) && cmnd->device->channel == b)
  3552. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  3553. }
  3554. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3555. if (b == ha->virt_bus) {
  3556. /* host drives */
  3557. for (i = 0; i < MAX_HDRIVES; ++i) {
  3558. if (ha->hdr[i].present) {
  3559. spin_lock_irqsave(&ha->smp_lock, flags);
  3560. gdth_polling = TRUE;
  3561. while (gdth_test_busy(ha))
  3562. gdth_delay(0);
  3563. if (gdth_internal_cmd(ha, CACHESERVICE,
  3564. GDT_CLUST_RESET, i, 0, 0))
  3565. ha->hdr[i].cluster_type &= ~CLUSTER_RESERVED;
  3566. gdth_polling = FALSE;
  3567. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3568. }
  3569. }
  3570. } else {
  3571. /* raw devices */
  3572. spin_lock_irqsave(&ha->smp_lock, flags);
  3573. for (i = 0; i < MAXID; ++i)
  3574. ha->raw[BUS_L2P(ha,b)].io_cnt[i] = 0;
  3575. gdth_polling = TRUE;
  3576. while (gdth_test_busy(ha))
  3577. gdth_delay(0);
  3578. gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESET_BUS,
  3579. BUS_L2P(ha,b), 0, 0);
  3580. gdth_polling = FALSE;
  3581. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3582. }
  3583. return SUCCESS;
  3584. }
  3585. static int gdth_bios_param(struct scsi_device *sdev,struct block_device *bdev,sector_t cap,int *ip)
  3586. {
  3587. u8 b, t;
  3588. gdth_ha_str *ha = shost_priv(sdev->host);
  3589. struct scsi_device *sd;
  3590. unsigned capacity;
  3591. sd = sdev;
  3592. capacity = cap;
  3593. b = sd->channel;
  3594. t = sd->id;
  3595. TRACE2(("gdth_bios_param() ha %d bus %d target %d\n", ha->hanum, b, t));
  3596. if (b != ha->virt_bus || ha->hdr[t].heads == 0) {
  3597. /* raw device or host drive without mapping information */
  3598. TRACE2(("Evaluate mapping\n"));
  3599. gdth_eval_mapping(capacity,&ip[2],&ip[0],&ip[1]);
  3600. } else {
  3601. ip[0] = ha->hdr[t].heads;
  3602. ip[1] = ha->hdr[t].secs;
  3603. ip[2] = capacity / ip[0] / ip[1];
  3604. }
  3605. TRACE2(("gdth_bios_param(): %d heads, %d secs, %d cyls\n",
  3606. ip[0],ip[1],ip[2]));
  3607. return 0;
  3608. }
  3609. static int gdth_queuecommand_lck(struct scsi_cmnd *scp,
  3610. void (*done)(struct scsi_cmnd *))
  3611. {
  3612. gdth_ha_str *ha = shost_priv(scp->device->host);
  3613. struct gdth_cmndinfo *cmndinfo;
  3614. TRACE(("gdth_queuecommand() cmd 0x%x\n", scp->cmnd[0]));
  3615. cmndinfo = gdth_get_cmndinfo(ha);
  3616. BUG_ON(!cmndinfo);
  3617. scp->scsi_done = done;
  3618. cmndinfo->timeout_count = 0;
  3619. cmndinfo->priority = DEFAULT_PRI;
  3620. return __gdth_queuecommand(ha, scp, cmndinfo);
  3621. }
  3622. static DEF_SCSI_QCMD(gdth_queuecommand)
  3623. static int __gdth_queuecommand(gdth_ha_str *ha, struct scsi_cmnd *scp,
  3624. struct gdth_cmndinfo *cmndinfo)
  3625. {
  3626. scp->host_scribble = (unsigned char *)cmndinfo;
  3627. cmndinfo->wait_for_completion = 1;
  3628. cmndinfo->phase = -1;
  3629. cmndinfo->OpCode = -1;
  3630. #ifdef GDTH_STATISTICS
  3631. ++act_ios;
  3632. #endif
  3633. gdth_putq(ha, scp, cmndinfo->priority);
  3634. gdth_next(ha);
  3635. return 0;
  3636. }
  3637. static int gdth_open(struct inode *inode, struct file *filep)
  3638. {
  3639. gdth_ha_str *ha;
  3640. mutex_lock(&gdth_mutex);
  3641. list_for_each_entry(ha, &gdth_instances, list) {
  3642. if (!ha->sdev)
  3643. ha->sdev = scsi_get_host_dev(ha->shost);
  3644. }
  3645. mutex_unlock(&gdth_mutex);
  3646. TRACE(("gdth_open()\n"));
  3647. return 0;
  3648. }
  3649. static int gdth_close(struct inode *inode, struct file *filep)
  3650. {
  3651. TRACE(("gdth_close()\n"));
  3652. return 0;
  3653. }
  3654. static int ioc_event(void __user *arg)
  3655. {
  3656. gdth_ioctl_event evt;
  3657. gdth_ha_str *ha;
  3658. unsigned long flags;
  3659. if (copy_from_user(&evt, arg, sizeof(gdth_ioctl_event)))
  3660. return -EFAULT;
  3661. ha = gdth_find_ha(evt.ionode);
  3662. if (!ha)
  3663. return -EFAULT;
  3664. if (evt.erase == 0xff) {
  3665. if (evt.event.event_source == ES_TEST)
  3666. evt.event.event_data.size=sizeof(evt.event.event_data.eu.test);
  3667. else if (evt.event.event_source == ES_DRIVER)
  3668. evt.event.event_data.size=sizeof(evt.event.event_data.eu.driver);
  3669. else if (evt.event.event_source == ES_SYNC)
  3670. evt.event.event_data.size=sizeof(evt.event.event_data.eu.sync);
  3671. else
  3672. evt.event.event_data.size=sizeof(evt.event.event_data.eu.async);
  3673. spin_lock_irqsave(&ha->smp_lock, flags);
  3674. gdth_store_event(ha, evt.event.event_source, evt.event.event_idx,
  3675. &evt.event.event_data);
  3676. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3677. } else if (evt.erase == 0xfe) {
  3678. gdth_clear_events();
  3679. } else if (evt.erase == 0) {
  3680. evt.handle = gdth_read_event(ha, evt.handle, &evt.event);
  3681. } else {
  3682. gdth_readapp_event(ha, evt.erase, &evt.event);
  3683. }
  3684. if (copy_to_user(arg, &evt, sizeof(gdth_ioctl_event)))
  3685. return -EFAULT;
  3686. return 0;
  3687. }
  3688. static int ioc_lockdrv(void __user *arg)
  3689. {
  3690. gdth_ioctl_lockdrv ldrv;
  3691. u8 i, j;
  3692. unsigned long flags;
  3693. gdth_ha_str *ha;
  3694. if (copy_from_user(&ldrv, arg, sizeof(gdth_ioctl_lockdrv)))
  3695. return -EFAULT;
  3696. ha = gdth_find_ha(ldrv.ionode);
  3697. if (!ha)
  3698. return -EFAULT;
  3699. for (i = 0; i < ldrv.drive_cnt && i < MAX_HDRIVES; ++i) {
  3700. j = ldrv.drives[i];
  3701. if (j >= MAX_HDRIVES || !ha->hdr[j].present)
  3702. continue;
  3703. if (ldrv.lock) {
  3704. spin_lock_irqsave(&ha->smp_lock, flags);
  3705. ha->hdr[j].lock = 1;
  3706. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3707. gdth_wait_completion(ha, ha->bus_cnt, j);
  3708. } else {
  3709. spin_lock_irqsave(&ha->smp_lock, flags);
  3710. ha->hdr[j].lock = 0;
  3711. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3712. gdth_next(ha);
  3713. }
  3714. }
  3715. return 0;
  3716. }
  3717. static int ioc_resetdrv(void __user *arg, char *cmnd)
  3718. {
  3719. gdth_ioctl_reset res;
  3720. gdth_cmd_str cmd;
  3721. gdth_ha_str *ha;
  3722. int rval;
  3723. if (copy_from_user(&res, arg, sizeof(gdth_ioctl_reset)) ||
  3724. res.number >= MAX_HDRIVES)
  3725. return -EFAULT;
  3726. ha = gdth_find_ha(res.ionode);
  3727. if (!ha)
  3728. return -EFAULT;
  3729. if (!ha->hdr[res.number].present)
  3730. return 0;
  3731. memset(&cmd, 0, sizeof(gdth_cmd_str));
  3732. cmd.Service = CACHESERVICE;
  3733. cmd.OpCode = GDT_CLUST_RESET;
  3734. if (ha->cache_feat & GDT_64BIT)
  3735. cmd.u.cache64.DeviceNo = res.number;
  3736. else
  3737. cmd.u.cache.DeviceNo = res.number;
  3738. rval = __gdth_execute(ha->sdev, &cmd, cmnd, 30, NULL);
  3739. if (rval < 0)
  3740. return rval;
  3741. res.status = rval;
  3742. if (copy_to_user(arg, &res, sizeof(gdth_ioctl_reset)))
  3743. return -EFAULT;
  3744. return 0;
  3745. }
  3746. static int ioc_general(void __user *arg, char *cmnd)
  3747. {
  3748. gdth_ioctl_general gen;
  3749. char *buf = NULL;
  3750. u64 paddr;
  3751. gdth_ha_str *ha;
  3752. int rval;
  3753. if (copy_from_user(&gen, arg, sizeof(gdth_ioctl_general)))
  3754. return -EFAULT;
  3755. ha = gdth_find_ha(gen.ionode);
  3756. if (!ha)
  3757. return -EFAULT;
  3758. if (gen.data_len > INT_MAX)
  3759. return -EINVAL;
  3760. if (gen.sense_len > INT_MAX)
  3761. return -EINVAL;
  3762. if (gen.data_len + gen.sense_len > INT_MAX)
  3763. return -EINVAL;
  3764. if (gen.data_len + gen.sense_len != 0) {
  3765. if (!(buf = gdth_ioctl_alloc(ha, gen.data_len + gen.sense_len,
  3766. FALSE, &paddr)))
  3767. return -EFAULT;
  3768. if (copy_from_user(buf, arg + sizeof(gdth_ioctl_general),
  3769. gen.data_len + gen.sense_len)) {
  3770. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3771. return -EFAULT;
  3772. }
  3773. if (gen.command.OpCode == GDT_IOCTL) {
  3774. gen.command.u.ioctl.p_param = paddr;
  3775. } else if (gen.command.Service == CACHESERVICE) {
  3776. if (ha->cache_feat & GDT_64BIT) {
  3777. /* copy elements from 32-bit IOCTL structure */
  3778. gen.command.u.cache64.BlockCnt = gen.command.u.cache.BlockCnt;
  3779. gen.command.u.cache64.BlockNo = gen.command.u.cache.BlockNo;
  3780. gen.command.u.cache64.DeviceNo = gen.command.u.cache.DeviceNo;
  3781. /* addresses */
  3782. if (ha->cache_feat & SCATTER_GATHER) {
  3783. gen.command.u.cache64.DestAddr = (u64)-1;
  3784. gen.command.u.cache64.sg_canz = 1;
  3785. gen.command.u.cache64.sg_lst[0].sg_ptr = paddr;
  3786. gen.command.u.cache64.sg_lst[0].sg_len = gen.data_len;
  3787. gen.command.u.cache64.sg_lst[1].sg_len = 0;
  3788. } else {
  3789. gen.command.u.cache64.DestAddr = paddr;
  3790. gen.command.u.cache64.sg_canz = 0;
  3791. }
  3792. } else {
  3793. if (ha->cache_feat & SCATTER_GATHER) {
  3794. gen.command.u.cache.DestAddr = 0xffffffff;
  3795. gen.command.u.cache.sg_canz = 1;
  3796. gen.command.u.cache.sg_lst[0].sg_ptr = (u32)paddr;
  3797. gen.command.u.cache.sg_lst[0].sg_len = gen.data_len;
  3798. gen.command.u.cache.sg_lst[1].sg_len = 0;
  3799. } else {
  3800. gen.command.u.cache.DestAddr = paddr;
  3801. gen.command.u.cache.sg_canz = 0;
  3802. }
  3803. }
  3804. } else if (gen.command.Service == SCSIRAWSERVICE) {
  3805. if (ha->raw_feat & GDT_64BIT) {
  3806. /* copy elements from 32-bit IOCTL structure */
  3807. char cmd[16];
  3808. gen.command.u.raw64.sense_len = gen.command.u.raw.sense_len;
  3809. gen.command.u.raw64.bus = gen.command.u.raw.bus;
  3810. gen.command.u.raw64.lun = gen.command.u.raw.lun;
  3811. gen.command.u.raw64.target = gen.command.u.raw.target;
  3812. memcpy(cmd, gen.command.u.raw.cmd, 16);
  3813. memcpy(gen.command.u.raw64.cmd, cmd, 16);
  3814. gen.command.u.raw64.clen = gen.command.u.raw.clen;
  3815. gen.command.u.raw64.sdlen = gen.command.u.raw.sdlen;
  3816. gen.command.u.raw64.direction = gen.command.u.raw.direction;
  3817. /* addresses */
  3818. if (ha->raw_feat & SCATTER_GATHER) {
  3819. gen.command.u.raw64.sdata = (u64)-1;
  3820. gen.command.u.raw64.sg_ranz = 1;
  3821. gen.command.u.raw64.sg_lst[0].sg_ptr = paddr;
  3822. gen.command.u.raw64.sg_lst[0].sg_len = gen.data_len;
  3823. gen.command.u.raw64.sg_lst[1].sg_len = 0;
  3824. } else {
  3825. gen.command.u.raw64.sdata = paddr;
  3826. gen.command.u.raw64.sg_ranz = 0;
  3827. }
  3828. gen.command.u.raw64.sense_data = paddr + gen.data_len;
  3829. } else {
  3830. if (ha->raw_feat & SCATTER_GATHER) {
  3831. gen.command.u.raw.sdata = 0xffffffff;
  3832. gen.command.u.raw.sg_ranz = 1;
  3833. gen.command.u.raw.sg_lst[0].sg_ptr = (u32)paddr;
  3834. gen.command.u.raw.sg_lst[0].sg_len = gen.data_len;
  3835. gen.command.u.raw.sg_lst[1].sg_len = 0;
  3836. } else {
  3837. gen.command.u.raw.sdata = paddr;
  3838. gen.command.u.raw.sg_ranz = 0;
  3839. }
  3840. gen.command.u.raw.sense_data = (u32)paddr + gen.data_len;
  3841. }
  3842. } else {
  3843. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3844. return -EFAULT;
  3845. }
  3846. }
  3847. rval = __gdth_execute(ha->sdev, &gen.command, cmnd, gen.timeout, &gen.info);
  3848. if (rval < 0) {
  3849. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3850. return rval;
  3851. }
  3852. gen.status = rval;
  3853. if (copy_to_user(arg + sizeof(gdth_ioctl_general), buf,
  3854. gen.data_len + gen.sense_len)) {
  3855. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3856. return -EFAULT;
  3857. }
  3858. if (copy_to_user(arg, &gen,
  3859. sizeof(gdth_ioctl_general) - sizeof(gdth_cmd_str))) {
  3860. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3861. return -EFAULT;
  3862. }
  3863. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3864. return 0;
  3865. }
  3866. static int ioc_hdrlist(void __user *arg, char *cmnd)
  3867. {
  3868. gdth_ioctl_rescan *rsc;
  3869. gdth_cmd_str *cmd;
  3870. gdth_ha_str *ha;
  3871. u8 i;
  3872. int rc = -ENOMEM;
  3873. u32 cluster_type = 0;
  3874. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  3875. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  3876. if (!rsc || !cmd)
  3877. goto free_fail;
  3878. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  3879. (NULL == (ha = gdth_find_ha(rsc->ionode)))) {
  3880. rc = -EFAULT;
  3881. goto free_fail;
  3882. }
  3883. memset(cmd, 0, sizeof(gdth_cmd_str));
  3884. for (i = 0; i < MAX_HDRIVES; ++i) {
  3885. if (!ha->hdr[i].present) {
  3886. rsc->hdr_list[i].bus = 0xff;
  3887. continue;
  3888. }
  3889. rsc->hdr_list[i].bus = ha->virt_bus;
  3890. rsc->hdr_list[i].target = i;
  3891. rsc->hdr_list[i].lun = 0;
  3892. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  3893. if (ha->hdr[i].cluster_type & CLUSTER_DRIVE) {
  3894. cmd->Service = CACHESERVICE;
  3895. cmd->OpCode = GDT_CLUST_INFO;
  3896. if (ha->cache_feat & GDT_64BIT)
  3897. cmd->u.cache64.DeviceNo = i;
  3898. else
  3899. cmd->u.cache.DeviceNo = i;
  3900. if (__gdth_execute(ha->sdev, cmd, cmnd, 30, &cluster_type) == S_OK)
  3901. rsc->hdr_list[i].cluster_type = cluster_type;
  3902. }
  3903. }
  3904. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  3905. rc = -EFAULT;
  3906. else
  3907. rc = 0;
  3908. free_fail:
  3909. kfree(rsc);
  3910. kfree(cmd);
  3911. return rc;
  3912. }
  3913. static int ioc_rescan(void __user *arg, char *cmnd)
  3914. {
  3915. gdth_ioctl_rescan *rsc;
  3916. gdth_cmd_str *cmd;
  3917. u16 i, status, hdr_cnt;
  3918. u32 info;
  3919. int cyls, hds, secs;
  3920. int rc = -ENOMEM;
  3921. unsigned long flags;
  3922. gdth_ha_str *ha;
  3923. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  3924. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  3925. if (!cmd || !rsc)
  3926. goto free_fail;
  3927. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  3928. (NULL == (ha = gdth_find_ha(rsc->ionode)))) {
  3929. rc = -EFAULT;
  3930. goto free_fail;
  3931. }
  3932. memset(cmd, 0, sizeof(gdth_cmd_str));
  3933. if (rsc->flag == 0) {
  3934. /* old method: re-init. cache service */
  3935. cmd->Service = CACHESERVICE;
  3936. if (ha->cache_feat & GDT_64BIT) {
  3937. cmd->OpCode = GDT_X_INIT_HOST;
  3938. cmd->u.cache64.DeviceNo = LINUX_OS;
  3939. } else {
  3940. cmd->OpCode = GDT_INIT;
  3941. cmd->u.cache.DeviceNo = LINUX_OS;
  3942. }
  3943. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  3944. i = 0;
  3945. hdr_cnt = (status == S_OK ? (u16)info : 0);
  3946. } else {
  3947. i = rsc->hdr_no;
  3948. hdr_cnt = i + 1;
  3949. }
  3950. for (; i < hdr_cnt && i < MAX_HDRIVES; ++i) {
  3951. cmd->Service = CACHESERVICE;
  3952. cmd->OpCode = GDT_INFO;
  3953. if (ha->cache_feat & GDT_64BIT)
  3954. cmd->u.cache64.DeviceNo = i;
  3955. else
  3956. cmd->u.cache.DeviceNo = i;
  3957. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  3958. spin_lock_irqsave(&ha->smp_lock, flags);
  3959. rsc->hdr_list[i].bus = ha->virt_bus;
  3960. rsc->hdr_list[i].target = i;
  3961. rsc->hdr_list[i].lun = 0;
  3962. if (status != S_OK) {
  3963. ha->hdr[i].present = FALSE;
  3964. } else {
  3965. ha->hdr[i].present = TRUE;
  3966. ha->hdr[i].size = info;
  3967. /* evaluate mapping */
  3968. ha->hdr[i].size &= ~SECS32;
  3969. gdth_eval_mapping(ha->hdr[i].size,&cyls,&hds,&secs);
  3970. ha->hdr[i].heads = hds;
  3971. ha->hdr[i].secs = secs;
  3972. /* round size */
  3973. ha->hdr[i].size = cyls * hds * secs;
  3974. }
  3975. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3976. if (status != S_OK)
  3977. continue;
  3978. /* extended info, if GDT_64BIT, for drives > 2 TB */
  3979. /* but we need ha->info2, not yet stored in scp->SCp */
  3980. /* devtype, cluster info, R/W attribs */
  3981. cmd->Service = CACHESERVICE;
  3982. cmd->OpCode = GDT_DEVTYPE;
  3983. if (ha->cache_feat & GDT_64BIT)
  3984. cmd->u.cache64.DeviceNo = i;
  3985. else
  3986. cmd->u.cache.DeviceNo = i;
  3987. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  3988. spin_lock_irqsave(&ha->smp_lock, flags);
  3989. ha->hdr[i].devtype = (status == S_OK ? (u16)info : 0);
  3990. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3991. cmd->Service = CACHESERVICE;
  3992. cmd->OpCode = GDT_CLUST_INFO;
  3993. if (ha->cache_feat & GDT_64BIT)
  3994. cmd->u.cache64.DeviceNo = i;
  3995. else
  3996. cmd->u.cache.DeviceNo = i;
  3997. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  3998. spin_lock_irqsave(&ha->smp_lock, flags);
  3999. ha->hdr[i].cluster_type =
  4000. ((status == S_OK && !shared_access) ? (u16)info : 0);
  4001. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4002. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  4003. cmd->Service = CACHESERVICE;
  4004. cmd->OpCode = GDT_RW_ATTRIBS;
  4005. if (ha->cache_feat & GDT_64BIT)
  4006. cmd->u.cache64.DeviceNo = i;
  4007. else
  4008. cmd->u.cache.DeviceNo = i;
  4009. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4010. spin_lock_irqsave(&ha->smp_lock, flags);
  4011. ha->hdr[i].rw_attribs = (status == S_OK ? (u16)info : 0);
  4012. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4013. }
  4014. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  4015. rc = -EFAULT;
  4016. else
  4017. rc = 0;
  4018. free_fail:
  4019. kfree(rsc);
  4020. kfree(cmd);
  4021. return rc;
  4022. }
  4023. static int gdth_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
  4024. {
  4025. gdth_ha_str *ha;
  4026. struct scsi_cmnd *scp;
  4027. unsigned long flags;
  4028. char cmnd[MAX_COMMAND_SIZE];
  4029. void __user *argp = (void __user *)arg;
  4030. memset(cmnd, 0xff, 12);
  4031. TRACE(("gdth_ioctl() cmd 0x%x\n", cmd));
  4032. switch (cmd) {
  4033. case GDTIOCTL_CTRCNT:
  4034. {
  4035. int cnt = gdth_ctr_count;
  4036. if (put_user(cnt, (int __user *)argp))
  4037. return -EFAULT;
  4038. break;
  4039. }
  4040. case GDTIOCTL_DRVERS:
  4041. {
  4042. int ver = (GDTH_VERSION<<8) | GDTH_SUBVERSION;
  4043. if (put_user(ver, (int __user *)argp))
  4044. return -EFAULT;
  4045. break;
  4046. }
  4047. case GDTIOCTL_OSVERS:
  4048. {
  4049. gdth_ioctl_osvers osv;
  4050. osv.version = (u8)(LINUX_VERSION_CODE >> 16);
  4051. osv.subversion = (u8)(LINUX_VERSION_CODE >> 8);
  4052. osv.revision = (u16)(LINUX_VERSION_CODE & 0xff);
  4053. if (copy_to_user(argp, &osv, sizeof(gdth_ioctl_osvers)))
  4054. return -EFAULT;
  4055. break;
  4056. }
  4057. case GDTIOCTL_CTRTYPE:
  4058. {
  4059. gdth_ioctl_ctrtype ctrt;
  4060. if (copy_from_user(&ctrt, argp, sizeof(gdth_ioctl_ctrtype)) ||
  4061. (NULL == (ha = gdth_find_ha(ctrt.ionode))))
  4062. return -EFAULT;
  4063. if (ha->type == GDT_ISA || ha->type == GDT_EISA) {
  4064. ctrt.type = (u8)((ha->stype>>20) - 0x10);
  4065. } else {
  4066. if (ha->type != GDT_PCIMPR) {
  4067. ctrt.type = (u8)((ha->stype<<4) + 6);
  4068. } else {
  4069. ctrt.type =
  4070. (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe);
  4071. if (ha->stype >= 0x300)
  4072. ctrt.ext_type = 0x6000 | ha->pdev->subsystem_device;
  4073. else
  4074. ctrt.ext_type = 0x6000 | ha->stype;
  4075. }
  4076. ctrt.device_id = ha->pdev->device;
  4077. ctrt.sub_device_id = ha->pdev->subsystem_device;
  4078. }
  4079. ctrt.info = ha->brd_phys;
  4080. ctrt.oem_id = ha->oem_id;
  4081. if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype)))
  4082. return -EFAULT;
  4083. break;
  4084. }
  4085. case GDTIOCTL_GENERAL:
  4086. return ioc_general(argp, cmnd);
  4087. case GDTIOCTL_EVENT:
  4088. return ioc_event(argp);
  4089. case GDTIOCTL_LOCKDRV:
  4090. return ioc_lockdrv(argp);
  4091. case GDTIOCTL_LOCKCHN:
  4092. {
  4093. gdth_ioctl_lockchn lchn;
  4094. u8 i, j;
  4095. if (copy_from_user(&lchn, argp, sizeof(gdth_ioctl_lockchn)) ||
  4096. (NULL == (ha = gdth_find_ha(lchn.ionode))))
  4097. return -EFAULT;
  4098. i = lchn.channel;
  4099. if (i < ha->bus_cnt) {
  4100. if (lchn.lock) {
  4101. spin_lock_irqsave(&ha->smp_lock, flags);
  4102. ha->raw[i].lock = 1;
  4103. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4104. for (j = 0; j < ha->tid_cnt; ++j)
  4105. gdth_wait_completion(ha, i, j);
  4106. } else {
  4107. spin_lock_irqsave(&ha->smp_lock, flags);
  4108. ha->raw[i].lock = 0;
  4109. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4110. for (j = 0; j < ha->tid_cnt; ++j)
  4111. gdth_next(ha);
  4112. }
  4113. }
  4114. break;
  4115. }
  4116. case GDTIOCTL_RESCAN:
  4117. return ioc_rescan(argp, cmnd);
  4118. case GDTIOCTL_HDRLIST:
  4119. return ioc_hdrlist(argp, cmnd);
  4120. case GDTIOCTL_RESET_BUS:
  4121. {
  4122. gdth_ioctl_reset res;
  4123. int rval;
  4124. if (copy_from_user(&res, argp, sizeof(gdth_ioctl_reset)) ||
  4125. (NULL == (ha = gdth_find_ha(res.ionode))))
  4126. return -EFAULT;
  4127. scp = kzalloc(sizeof(*scp), GFP_KERNEL);
  4128. if (!scp)
  4129. return -ENOMEM;
  4130. scp->device = ha->sdev;
  4131. scp->cmd_len = 12;
  4132. scp->device->channel = res.number;
  4133. rval = gdth_eh_bus_reset(scp);
  4134. res.status = (rval == SUCCESS ? S_OK : S_GENERR);
  4135. kfree(scp);
  4136. if (copy_to_user(argp, &res, sizeof(gdth_ioctl_reset)))
  4137. return -EFAULT;
  4138. break;
  4139. }
  4140. case GDTIOCTL_RESET_DRV:
  4141. return ioc_resetdrv(argp, cmnd);
  4142. default:
  4143. break;
  4144. }
  4145. return 0;
  4146. }
  4147. static long gdth_unlocked_ioctl(struct file *file, unsigned int cmd,
  4148. unsigned long arg)
  4149. {
  4150. int ret;
  4151. mutex_lock(&gdth_mutex);
  4152. ret = gdth_ioctl(file, cmd, arg);
  4153. mutex_unlock(&gdth_mutex);
  4154. return ret;
  4155. }
  4156. /* flush routine */
  4157. static void gdth_flush(gdth_ha_str *ha)
  4158. {
  4159. int i;
  4160. gdth_cmd_str gdtcmd;
  4161. char cmnd[MAX_COMMAND_SIZE];
  4162. memset(cmnd, 0xff, MAX_COMMAND_SIZE);
  4163. TRACE2(("gdth_flush() hanum %d\n", ha->hanum));
  4164. for (i = 0; i < MAX_HDRIVES; ++i) {
  4165. if (ha->hdr[i].present) {
  4166. gdtcmd.BoardNode = LOCALBOARD;
  4167. gdtcmd.Service = CACHESERVICE;
  4168. gdtcmd.OpCode = GDT_FLUSH;
  4169. if (ha->cache_feat & GDT_64BIT) {
  4170. gdtcmd.u.cache64.DeviceNo = i;
  4171. gdtcmd.u.cache64.BlockNo = 1;
  4172. gdtcmd.u.cache64.sg_canz = 0;
  4173. } else {
  4174. gdtcmd.u.cache.DeviceNo = i;
  4175. gdtcmd.u.cache.BlockNo = 1;
  4176. gdtcmd.u.cache.sg_canz = 0;
  4177. }
  4178. TRACE2(("gdth_flush(): flush ha %d drive %d\n", ha->hanum, i));
  4179. gdth_execute(ha->shost, &gdtcmd, cmnd, 30, NULL);
  4180. }
  4181. }
  4182. }
  4183. /* configure lun */
  4184. static int gdth_slave_configure(struct scsi_device *sdev)
  4185. {
  4186. sdev->skip_ms_page_3f = 1;
  4187. sdev->skip_ms_page_8 = 1;
  4188. return 0;
  4189. }
  4190. static struct scsi_host_template gdth_template = {
  4191. .name = "GDT SCSI Disk Array Controller",
  4192. .info = gdth_info,
  4193. .queuecommand = gdth_queuecommand,
  4194. .eh_bus_reset_handler = gdth_eh_bus_reset,
  4195. .slave_configure = gdth_slave_configure,
  4196. .bios_param = gdth_bios_param,
  4197. .show_info = gdth_show_info,
  4198. .write_info = gdth_set_info,
  4199. .eh_timed_out = gdth_timed_out,
  4200. .proc_name = "gdth",
  4201. .can_queue = GDTH_MAXCMDS,
  4202. .this_id = -1,
  4203. .sg_tablesize = GDTH_MAXSG,
  4204. .cmd_per_lun = GDTH_MAXC_P_L,
  4205. .unchecked_isa_dma = 1,
  4206. .use_clustering = ENABLE_CLUSTERING,
  4207. .no_write_same = 1,
  4208. };
  4209. #ifdef CONFIG_ISA
  4210. static int __init gdth_isa_probe_one(u32 isa_bios)
  4211. {
  4212. struct Scsi_Host *shp;
  4213. gdth_ha_str *ha;
  4214. dma_addr_t scratch_dma_handle = 0;
  4215. int error, i;
  4216. if (!gdth_search_isa(isa_bios))
  4217. return -ENXIO;
  4218. shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
  4219. if (!shp)
  4220. return -ENOMEM;
  4221. ha = shost_priv(shp);
  4222. error = -ENODEV;
  4223. if (!gdth_init_isa(isa_bios,ha))
  4224. goto out_host_put;
  4225. /* controller found and initialized */
  4226. printk("Configuring GDT-ISA HA at BIOS 0x%05X IRQ %u DRQ %u\n",
  4227. isa_bios, ha->irq, ha->drq);
  4228. error = request_irq(ha->irq, gdth_interrupt, 0, "gdth", ha);
  4229. if (error) {
  4230. printk("GDT-ISA: Unable to allocate IRQ\n");
  4231. goto out_host_put;
  4232. }
  4233. error = request_dma(ha->drq, "gdth");
  4234. if (error) {
  4235. printk("GDT-ISA: Unable to allocate DMA channel\n");
  4236. goto out_free_irq;
  4237. }
  4238. set_dma_mode(ha->drq,DMA_MODE_CASCADE);
  4239. enable_dma(ha->drq);
  4240. shp->unchecked_isa_dma = 1;
  4241. shp->irq = ha->irq;
  4242. shp->dma_channel = ha->drq;
  4243. ha->hanum = gdth_ctr_count++;
  4244. ha->shost = shp;
  4245. ha->pccb = &ha->cmdext;
  4246. ha->ccb_phys = 0L;
  4247. ha->pdev = NULL;
  4248. error = -ENOMEM;
  4249. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4250. &scratch_dma_handle);
  4251. if (!ha->pscratch)
  4252. goto out_dec_counters;
  4253. ha->scratch_phys = scratch_dma_handle;
  4254. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4255. &scratch_dma_handle);
  4256. if (!ha->pmsg)
  4257. goto out_free_pscratch;
  4258. ha->msg_phys = scratch_dma_handle;
  4259. #ifdef INT_COAL
  4260. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4261. sizeof(gdth_coal_status) * MAXOFFSETS,
  4262. &scratch_dma_handle);
  4263. if (!ha->coal_stat)
  4264. goto out_free_pmsg;
  4265. ha->coal_stat_phys = scratch_dma_handle;
  4266. #endif
  4267. ha->scratch_busy = FALSE;
  4268. ha->req_first = NULL;
  4269. ha->tid_cnt = MAX_HDRIVES;
  4270. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4271. ha->tid_cnt = max_ids;
  4272. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4273. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4274. ha->scan_mode = rescan ? 0x10 : 0;
  4275. error = -ENODEV;
  4276. if (!gdth_search_drives(ha)) {
  4277. printk("GDT-ISA: Error during device scan\n");
  4278. goto out_free_coal_stat;
  4279. }
  4280. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4281. hdr_channel = ha->bus_cnt;
  4282. ha->virt_bus = hdr_channel;
  4283. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  4284. shp->max_cmd_len = 16;
  4285. shp->max_id = ha->tid_cnt;
  4286. shp->max_lun = MAXLUN;
  4287. shp->max_channel = ha->bus_cnt;
  4288. spin_lock_init(&ha->smp_lock);
  4289. gdth_enable_int(ha);
  4290. error = scsi_add_host(shp, NULL);
  4291. if (error)
  4292. goto out_free_coal_stat;
  4293. list_add_tail(&ha->list, &gdth_instances);
  4294. gdth_timer_init();
  4295. scsi_scan_host(shp);
  4296. return 0;
  4297. out_free_coal_stat:
  4298. #ifdef INT_COAL
  4299. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4300. ha->coal_stat, ha->coal_stat_phys);
  4301. out_free_pmsg:
  4302. #endif
  4303. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4304. ha->pmsg, ha->msg_phys);
  4305. out_free_pscratch:
  4306. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4307. ha->pscratch, ha->scratch_phys);
  4308. out_dec_counters:
  4309. gdth_ctr_count--;
  4310. out_free_irq:
  4311. free_irq(ha->irq, ha);
  4312. out_host_put:
  4313. scsi_host_put(shp);
  4314. return error;
  4315. }
  4316. #endif /* CONFIG_ISA */
  4317. #ifdef CONFIG_EISA
  4318. static int __init gdth_eisa_probe_one(u16 eisa_slot)
  4319. {
  4320. struct Scsi_Host *shp;
  4321. gdth_ha_str *ha;
  4322. dma_addr_t scratch_dma_handle = 0;
  4323. int error, i;
  4324. if (!gdth_search_eisa(eisa_slot))
  4325. return -ENXIO;
  4326. shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
  4327. if (!shp)
  4328. return -ENOMEM;
  4329. ha = shost_priv(shp);
  4330. error = -ENODEV;
  4331. if (!gdth_init_eisa(eisa_slot,ha))
  4332. goto out_host_put;
  4333. /* controller found and initialized */
  4334. printk("Configuring GDT-EISA HA at Slot %d IRQ %u\n",
  4335. eisa_slot >> 12, ha->irq);
  4336. error = request_irq(ha->irq, gdth_interrupt, 0, "gdth", ha);
  4337. if (error) {
  4338. printk("GDT-EISA: Unable to allocate IRQ\n");
  4339. goto out_host_put;
  4340. }
  4341. shp->unchecked_isa_dma = 0;
  4342. shp->irq = ha->irq;
  4343. shp->dma_channel = 0xff;
  4344. ha->hanum = gdth_ctr_count++;
  4345. ha->shost = shp;
  4346. TRACE2(("EISA detect Bus 0: hanum %d\n", ha->hanum));
  4347. ha->pccb = &ha->cmdext;
  4348. ha->ccb_phys = 0L;
  4349. error = -ENOMEM;
  4350. ha->pdev = NULL;
  4351. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4352. &scratch_dma_handle);
  4353. if (!ha->pscratch)
  4354. goto out_free_irq;
  4355. ha->scratch_phys = scratch_dma_handle;
  4356. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4357. &scratch_dma_handle);
  4358. if (!ha->pmsg)
  4359. goto out_free_pscratch;
  4360. ha->msg_phys = scratch_dma_handle;
  4361. #ifdef INT_COAL
  4362. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4363. sizeof(gdth_coal_status) * MAXOFFSETS,
  4364. &scratch_dma_handle);
  4365. if (!ha->coal_stat)
  4366. goto out_free_pmsg;
  4367. ha->coal_stat_phys = scratch_dma_handle;
  4368. #endif
  4369. ha->ccb_phys = pci_map_single(ha->pdev,ha->pccb,
  4370. sizeof(gdth_cmd_str), PCI_DMA_BIDIRECTIONAL);
  4371. if (!ha->ccb_phys)
  4372. goto out_free_coal_stat;
  4373. ha->scratch_busy = FALSE;
  4374. ha->req_first = NULL;
  4375. ha->tid_cnt = MAX_HDRIVES;
  4376. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4377. ha->tid_cnt = max_ids;
  4378. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4379. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4380. ha->scan_mode = rescan ? 0x10 : 0;
  4381. if (!gdth_search_drives(ha)) {
  4382. printk("GDT-EISA: Error during device scan\n");
  4383. error = -ENODEV;
  4384. goto out_free_ccb_phys;
  4385. }
  4386. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4387. hdr_channel = ha->bus_cnt;
  4388. ha->virt_bus = hdr_channel;
  4389. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  4390. shp->max_cmd_len = 16;
  4391. shp->max_id = ha->tid_cnt;
  4392. shp->max_lun = MAXLUN;
  4393. shp->max_channel = ha->bus_cnt;
  4394. spin_lock_init(&ha->smp_lock);
  4395. gdth_enable_int(ha);
  4396. error = scsi_add_host(shp, NULL);
  4397. if (error)
  4398. goto out_free_ccb_phys;
  4399. list_add_tail(&ha->list, &gdth_instances);
  4400. gdth_timer_init();
  4401. scsi_scan_host(shp);
  4402. return 0;
  4403. out_free_ccb_phys:
  4404. pci_unmap_single(ha->pdev,ha->ccb_phys, sizeof(gdth_cmd_str),
  4405. PCI_DMA_BIDIRECTIONAL);
  4406. out_free_coal_stat:
  4407. #ifdef INT_COAL
  4408. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4409. ha->coal_stat, ha->coal_stat_phys);
  4410. out_free_pmsg:
  4411. #endif
  4412. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4413. ha->pmsg, ha->msg_phys);
  4414. out_free_pscratch:
  4415. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4416. ha->pscratch, ha->scratch_phys);
  4417. out_free_irq:
  4418. free_irq(ha->irq, ha);
  4419. gdth_ctr_count--;
  4420. out_host_put:
  4421. scsi_host_put(shp);
  4422. return error;
  4423. }
  4424. #endif /* CONFIG_EISA */
  4425. #ifdef CONFIG_PCI
  4426. static int gdth_pci_probe_one(gdth_pci_str *pcistr, gdth_ha_str **ha_out)
  4427. {
  4428. struct Scsi_Host *shp;
  4429. gdth_ha_str *ha;
  4430. dma_addr_t scratch_dma_handle = 0;
  4431. int error, i;
  4432. struct pci_dev *pdev = pcistr->pdev;
  4433. *ha_out = NULL;
  4434. shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
  4435. if (!shp)
  4436. return -ENOMEM;
  4437. ha = shost_priv(shp);
  4438. error = -ENODEV;
  4439. if (!gdth_init_pci(pdev, pcistr, ha))
  4440. goto out_host_put;
  4441. /* controller found and initialized */
  4442. printk("Configuring GDT-PCI HA at %d/%d IRQ %u\n",
  4443. pdev->bus->number,
  4444. PCI_SLOT(pdev->devfn),
  4445. ha->irq);
  4446. error = request_irq(ha->irq, gdth_interrupt,
  4447. IRQF_SHARED, "gdth", ha);
  4448. if (error) {
  4449. printk("GDT-PCI: Unable to allocate IRQ\n");
  4450. goto out_host_put;
  4451. }
  4452. shp->unchecked_isa_dma = 0;
  4453. shp->irq = ha->irq;
  4454. shp->dma_channel = 0xff;
  4455. ha->hanum = gdth_ctr_count++;
  4456. ha->shost = shp;
  4457. ha->pccb = &ha->cmdext;
  4458. ha->ccb_phys = 0L;
  4459. error = -ENOMEM;
  4460. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4461. &scratch_dma_handle);
  4462. if (!ha->pscratch)
  4463. goto out_free_irq;
  4464. ha->scratch_phys = scratch_dma_handle;
  4465. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4466. &scratch_dma_handle);
  4467. if (!ha->pmsg)
  4468. goto out_free_pscratch;
  4469. ha->msg_phys = scratch_dma_handle;
  4470. #ifdef INT_COAL
  4471. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4472. sizeof(gdth_coal_status) * MAXOFFSETS,
  4473. &scratch_dma_handle);
  4474. if (!ha->coal_stat)
  4475. goto out_free_pmsg;
  4476. ha->coal_stat_phys = scratch_dma_handle;
  4477. #endif
  4478. ha->scratch_busy = FALSE;
  4479. ha->req_first = NULL;
  4480. ha->tid_cnt = pdev->device >= 0x200 ? MAXID : MAX_HDRIVES;
  4481. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4482. ha->tid_cnt = max_ids;
  4483. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4484. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4485. ha->scan_mode = rescan ? 0x10 : 0;
  4486. error = -ENODEV;
  4487. if (!gdth_search_drives(ha)) {
  4488. printk("GDT-PCI %d: Error during device scan\n", ha->hanum);
  4489. goto out_free_coal_stat;
  4490. }
  4491. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4492. hdr_channel = ha->bus_cnt;
  4493. ha->virt_bus = hdr_channel;
  4494. /* 64-bit DMA only supported from FW >= x.43 */
  4495. if (!(ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT) ||
  4496. !ha->dma64_support) {
  4497. if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
  4498. printk(KERN_WARNING "GDT-PCI %d: "
  4499. "Unable to set 32-bit DMA\n", ha->hanum);
  4500. goto out_free_coal_stat;
  4501. }
  4502. } else {
  4503. shp->max_cmd_len = 16;
  4504. if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
  4505. printk("GDT-PCI %d: 64-bit DMA enabled\n", ha->hanum);
  4506. } else if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
  4507. printk(KERN_WARNING "GDT-PCI %d: "
  4508. "Unable to set 64/32-bit DMA\n", ha->hanum);
  4509. goto out_free_coal_stat;
  4510. }
  4511. }
  4512. shp->max_id = ha->tid_cnt;
  4513. shp->max_lun = MAXLUN;
  4514. shp->max_channel = ha->bus_cnt;
  4515. spin_lock_init(&ha->smp_lock);
  4516. gdth_enable_int(ha);
  4517. error = scsi_add_host(shp, &pdev->dev);
  4518. if (error)
  4519. goto out_free_coal_stat;
  4520. list_add_tail(&ha->list, &gdth_instances);
  4521. pci_set_drvdata(ha->pdev, ha);
  4522. gdth_timer_init();
  4523. scsi_scan_host(shp);
  4524. *ha_out = ha;
  4525. return 0;
  4526. out_free_coal_stat:
  4527. #ifdef INT_COAL
  4528. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4529. ha->coal_stat, ha->coal_stat_phys);
  4530. out_free_pmsg:
  4531. #endif
  4532. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4533. ha->pmsg, ha->msg_phys);
  4534. out_free_pscratch:
  4535. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4536. ha->pscratch, ha->scratch_phys);
  4537. out_free_irq:
  4538. free_irq(ha->irq, ha);
  4539. gdth_ctr_count--;
  4540. out_host_put:
  4541. scsi_host_put(shp);
  4542. return error;
  4543. }
  4544. #endif /* CONFIG_PCI */
  4545. static void gdth_remove_one(gdth_ha_str *ha)
  4546. {
  4547. struct Scsi_Host *shp = ha->shost;
  4548. TRACE2(("gdth_remove_one()\n"));
  4549. scsi_remove_host(shp);
  4550. gdth_flush(ha);
  4551. if (ha->sdev) {
  4552. scsi_free_host_dev(ha->sdev);
  4553. ha->sdev = NULL;
  4554. }
  4555. if (shp->irq)
  4556. free_irq(shp->irq,ha);
  4557. #ifdef CONFIG_ISA
  4558. if (shp->dma_channel != 0xff)
  4559. free_dma(shp->dma_channel);
  4560. #endif
  4561. #ifdef INT_COAL
  4562. if (ha->coal_stat)
  4563. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4564. MAXOFFSETS, ha->coal_stat, ha->coal_stat_phys);
  4565. #endif
  4566. if (ha->pscratch)
  4567. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4568. ha->pscratch, ha->scratch_phys);
  4569. if (ha->pmsg)
  4570. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4571. ha->pmsg, ha->msg_phys);
  4572. if (ha->ccb_phys)
  4573. pci_unmap_single(ha->pdev,ha->ccb_phys,
  4574. sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
  4575. scsi_host_put(shp);
  4576. }
  4577. static int gdth_halt(struct notifier_block *nb, unsigned long event, void *buf)
  4578. {
  4579. gdth_ha_str *ha;
  4580. TRACE2(("gdth_halt() event %d\n", (int)event));
  4581. if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
  4582. return NOTIFY_DONE;
  4583. list_for_each_entry(ha, &gdth_instances, list)
  4584. gdth_flush(ha);
  4585. return NOTIFY_OK;
  4586. }
  4587. static struct notifier_block gdth_notifier = {
  4588. gdth_halt, NULL, 0
  4589. };
  4590. static int __init gdth_init(void)
  4591. {
  4592. if (disable) {
  4593. printk("GDT-HA: Controller driver disabled from"
  4594. " command line !\n");
  4595. return 0;
  4596. }
  4597. printk("GDT-HA: Storage RAID Controller Driver. Version: %s\n",
  4598. GDTH_VERSION_STR);
  4599. /* initializations */
  4600. gdth_polling = TRUE;
  4601. gdth_clear_events();
  4602. timer_setup(&gdth_timer, gdth_timeout, 0);
  4603. /* As default we do not probe for EISA or ISA controllers */
  4604. if (probe_eisa_isa) {
  4605. /* scanning for controllers, at first: ISA controller */
  4606. #ifdef CONFIG_ISA
  4607. u32 isa_bios;
  4608. for (isa_bios = 0xc8000UL; isa_bios <= 0xd8000UL;
  4609. isa_bios += 0x8000UL)
  4610. gdth_isa_probe_one(isa_bios);
  4611. #endif
  4612. #ifdef CONFIG_EISA
  4613. {
  4614. u16 eisa_slot;
  4615. for (eisa_slot = 0x1000; eisa_slot <= 0x8000;
  4616. eisa_slot += 0x1000)
  4617. gdth_eisa_probe_one(eisa_slot);
  4618. }
  4619. #endif
  4620. }
  4621. #ifdef CONFIG_PCI
  4622. /* scanning for PCI controllers */
  4623. if (pci_register_driver(&gdth_pci_driver)) {
  4624. gdth_ha_str *ha;
  4625. list_for_each_entry(ha, &gdth_instances, list)
  4626. gdth_remove_one(ha);
  4627. return -ENODEV;
  4628. }
  4629. #endif /* CONFIG_PCI */
  4630. TRACE2(("gdth_detect() %d controller detected\n", gdth_ctr_count));
  4631. major = register_chrdev(0,"gdth", &gdth_fops);
  4632. register_reboot_notifier(&gdth_notifier);
  4633. gdth_polling = FALSE;
  4634. return 0;
  4635. }
  4636. static void __exit gdth_exit(void)
  4637. {
  4638. gdth_ha_str *ha;
  4639. unregister_chrdev(major, "gdth");
  4640. unregister_reboot_notifier(&gdth_notifier);
  4641. #ifdef GDTH_STATISTICS
  4642. del_timer_sync(&gdth_timer);
  4643. #endif
  4644. #ifdef CONFIG_PCI
  4645. pci_unregister_driver(&gdth_pci_driver);
  4646. #endif
  4647. list_for_each_entry(ha, &gdth_instances, list)
  4648. gdth_remove_one(ha);
  4649. }
  4650. module_init(gdth_init);
  4651. module_exit(gdth_exit);
  4652. #ifndef MODULE
  4653. __setup("gdth=", option_setup);
  4654. #endif