rtc-xgene.c 7.4 KB

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  1. /*
  2. * APM X-Gene SoC Real Time Clock Driver
  3. *
  4. * Copyright (c) 2014, Applied Micro Circuits Corporation
  5. * Author: Rameshwar Prasad Sahu <rsahu@apm.com>
  6. * Loc Ho <lho@apm.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  20. *
  21. */
  22. #include <linux/init.h>
  23. #include <linux/module.h>
  24. #include <linux/of.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/io.h>
  27. #include <linux/slab.h>
  28. #include <linux/clk.h>
  29. #include <linux/delay.h>
  30. #include <linux/rtc.h>
  31. /* RTC CSR Registers */
  32. #define RTC_CCVR 0x00
  33. #define RTC_CMR 0x04
  34. #define RTC_CLR 0x08
  35. #define RTC_CCR 0x0C
  36. #define RTC_CCR_IE BIT(0)
  37. #define RTC_CCR_MASK BIT(1)
  38. #define RTC_CCR_EN BIT(2)
  39. #define RTC_CCR_WEN BIT(3)
  40. #define RTC_STAT 0x10
  41. #define RTC_STAT_BIT BIT(0)
  42. #define RTC_RSTAT 0x14
  43. #define RTC_EOI 0x18
  44. #define RTC_VER 0x1C
  45. struct xgene_rtc_dev {
  46. struct rtc_device *rtc;
  47. struct device *dev;
  48. unsigned long alarm_time;
  49. void __iomem *csr_base;
  50. struct clk *clk;
  51. unsigned int irq_wake;
  52. unsigned int irq_enabled;
  53. };
  54. static int xgene_rtc_read_time(struct device *dev, struct rtc_time *tm)
  55. {
  56. struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);
  57. rtc_time_to_tm(readl(pdata->csr_base + RTC_CCVR), tm);
  58. return 0;
  59. }
  60. static int xgene_rtc_set_mmss(struct device *dev, unsigned long secs)
  61. {
  62. struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);
  63. /*
  64. * NOTE: After the following write, the RTC_CCVR is only reflected
  65. * after the update cycle of 1 seconds.
  66. */
  67. writel((u32) secs, pdata->csr_base + RTC_CLR);
  68. readl(pdata->csr_base + RTC_CLR); /* Force a barrier */
  69. return 0;
  70. }
  71. static int xgene_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  72. {
  73. struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);
  74. rtc_time_to_tm(pdata->alarm_time, &alrm->time);
  75. alrm->enabled = readl(pdata->csr_base + RTC_CCR) & RTC_CCR_IE;
  76. return 0;
  77. }
  78. static int xgene_rtc_alarm_irq_enable(struct device *dev, u32 enabled)
  79. {
  80. struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);
  81. u32 ccr;
  82. ccr = readl(pdata->csr_base + RTC_CCR);
  83. if (enabled) {
  84. ccr &= ~RTC_CCR_MASK;
  85. ccr |= RTC_CCR_IE;
  86. } else {
  87. ccr &= ~RTC_CCR_IE;
  88. ccr |= RTC_CCR_MASK;
  89. }
  90. writel(ccr, pdata->csr_base + RTC_CCR);
  91. return 0;
  92. }
  93. static int xgene_rtc_alarm_irq_enabled(struct device *dev)
  94. {
  95. struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);
  96. return readl(pdata->csr_base + RTC_CCR) & RTC_CCR_IE ? 1 : 0;
  97. }
  98. static int xgene_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  99. {
  100. struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);
  101. unsigned long alarm_time;
  102. rtc_tm_to_time(&alrm->time, &alarm_time);
  103. pdata->alarm_time = alarm_time;
  104. writel((u32) pdata->alarm_time, pdata->csr_base + RTC_CMR);
  105. xgene_rtc_alarm_irq_enable(dev, alrm->enabled);
  106. return 0;
  107. }
  108. static const struct rtc_class_ops xgene_rtc_ops = {
  109. .read_time = xgene_rtc_read_time,
  110. .set_mmss = xgene_rtc_set_mmss,
  111. .read_alarm = xgene_rtc_read_alarm,
  112. .set_alarm = xgene_rtc_set_alarm,
  113. .alarm_irq_enable = xgene_rtc_alarm_irq_enable,
  114. };
  115. static irqreturn_t xgene_rtc_interrupt(int irq, void *id)
  116. {
  117. struct xgene_rtc_dev *pdata = (struct xgene_rtc_dev *) id;
  118. /* Check if interrupt asserted */
  119. if (!(readl(pdata->csr_base + RTC_STAT) & RTC_STAT_BIT))
  120. return IRQ_NONE;
  121. /* Clear interrupt */
  122. readl(pdata->csr_base + RTC_EOI);
  123. rtc_update_irq(pdata->rtc, 1, RTC_IRQF | RTC_AF);
  124. return IRQ_HANDLED;
  125. }
  126. static int xgene_rtc_probe(struct platform_device *pdev)
  127. {
  128. struct xgene_rtc_dev *pdata;
  129. struct resource *res;
  130. int ret;
  131. int irq;
  132. pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
  133. if (!pdata)
  134. return -ENOMEM;
  135. platform_set_drvdata(pdev, pdata);
  136. pdata->dev = &pdev->dev;
  137. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  138. pdata->csr_base = devm_ioremap_resource(&pdev->dev, res);
  139. if (IS_ERR(pdata->csr_base))
  140. return PTR_ERR(pdata->csr_base);
  141. pdata->rtc = devm_rtc_allocate_device(&pdev->dev);
  142. if (IS_ERR(pdata->rtc))
  143. return PTR_ERR(pdata->rtc);
  144. irq = platform_get_irq(pdev, 0);
  145. if (irq < 0) {
  146. dev_err(&pdev->dev, "No IRQ resource\n");
  147. return irq;
  148. }
  149. ret = devm_request_irq(&pdev->dev, irq, xgene_rtc_interrupt, 0,
  150. dev_name(&pdev->dev), pdata);
  151. if (ret) {
  152. dev_err(&pdev->dev, "Could not request IRQ\n");
  153. return ret;
  154. }
  155. pdata->clk = devm_clk_get(&pdev->dev, NULL);
  156. if (IS_ERR(pdata->clk)) {
  157. dev_err(&pdev->dev, "Couldn't get the clock for RTC\n");
  158. return -ENODEV;
  159. }
  160. ret = clk_prepare_enable(pdata->clk);
  161. if (ret)
  162. return ret;
  163. /* Turn on the clock and the crystal */
  164. writel(RTC_CCR_EN, pdata->csr_base + RTC_CCR);
  165. ret = device_init_wakeup(&pdev->dev, 1);
  166. if (ret) {
  167. clk_disable_unprepare(pdata->clk);
  168. return ret;
  169. }
  170. /* HW does not support update faster than 1 seconds */
  171. pdata->rtc->uie_unsupported = 1;
  172. pdata->rtc->ops = &xgene_rtc_ops;
  173. ret = rtc_register_device(pdata->rtc);
  174. if (ret) {
  175. clk_disable_unprepare(pdata->clk);
  176. return ret;
  177. }
  178. return 0;
  179. }
  180. static int xgene_rtc_remove(struct platform_device *pdev)
  181. {
  182. struct xgene_rtc_dev *pdata = platform_get_drvdata(pdev);
  183. xgene_rtc_alarm_irq_enable(&pdev->dev, 0);
  184. device_init_wakeup(&pdev->dev, 0);
  185. clk_disable_unprepare(pdata->clk);
  186. return 0;
  187. }
  188. static int __maybe_unused xgene_rtc_suspend(struct device *dev)
  189. {
  190. struct platform_device *pdev = to_platform_device(dev);
  191. struct xgene_rtc_dev *pdata = platform_get_drvdata(pdev);
  192. int irq;
  193. irq = platform_get_irq(pdev, 0);
  194. /*
  195. * If this RTC alarm will be used for waking the system up,
  196. * don't disable it of course. Else we just disable the alarm
  197. * and await suspension.
  198. */
  199. if (device_may_wakeup(&pdev->dev)) {
  200. if (!enable_irq_wake(irq))
  201. pdata->irq_wake = 1;
  202. } else {
  203. pdata->irq_enabled = xgene_rtc_alarm_irq_enabled(dev);
  204. xgene_rtc_alarm_irq_enable(dev, 0);
  205. clk_disable_unprepare(pdata->clk);
  206. }
  207. return 0;
  208. }
  209. static int __maybe_unused xgene_rtc_resume(struct device *dev)
  210. {
  211. struct platform_device *pdev = to_platform_device(dev);
  212. struct xgene_rtc_dev *pdata = platform_get_drvdata(pdev);
  213. int irq;
  214. int rc;
  215. irq = platform_get_irq(pdev, 0);
  216. if (device_may_wakeup(&pdev->dev)) {
  217. if (pdata->irq_wake) {
  218. disable_irq_wake(irq);
  219. pdata->irq_wake = 0;
  220. }
  221. } else {
  222. rc = clk_prepare_enable(pdata->clk);
  223. if (rc) {
  224. dev_err(dev, "Unable to enable clock error %d\n", rc);
  225. return rc;
  226. }
  227. xgene_rtc_alarm_irq_enable(dev, pdata->irq_enabled);
  228. }
  229. return 0;
  230. }
  231. static SIMPLE_DEV_PM_OPS(xgene_rtc_pm_ops, xgene_rtc_suspend, xgene_rtc_resume);
  232. #ifdef CONFIG_OF
  233. static const struct of_device_id xgene_rtc_of_match[] = {
  234. {.compatible = "apm,xgene-rtc" },
  235. { }
  236. };
  237. MODULE_DEVICE_TABLE(of, xgene_rtc_of_match);
  238. #endif
  239. static struct platform_driver xgene_rtc_driver = {
  240. .probe = xgene_rtc_probe,
  241. .remove = xgene_rtc_remove,
  242. .driver = {
  243. .name = "xgene-rtc",
  244. .pm = &xgene_rtc_pm_ops,
  245. .of_match_table = of_match_ptr(xgene_rtc_of_match),
  246. },
  247. };
  248. module_platform_driver(xgene_rtc_driver);
  249. MODULE_DESCRIPTION("APM X-Gene SoC RTC driver");
  250. MODULE_AUTHOR("Rameshwar Sahu <rsahu@apm.com>");
  251. MODULE_LICENSE("GPL");