rtc-sh.c 17 KB

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  1. /*
  2. * SuperH On-Chip RTC Support
  3. *
  4. * Copyright (C) 2006 - 2009 Paul Mundt
  5. * Copyright (C) 2006 Jamie Lenehan
  6. * Copyright (C) 2008 Angelo Castello
  7. *
  8. * Based on the old arch/sh/kernel/cpu/rtc.c by:
  9. *
  10. * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
  11. * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
  12. *
  13. * This file is subject to the terms and conditions of the GNU General Public
  14. * License. See the file "COPYING" in the main directory of this archive
  15. * for more details.
  16. */
  17. #include <linux/module.h>
  18. #include <linux/mod_devicetable.h>
  19. #include <linux/kernel.h>
  20. #include <linux/bcd.h>
  21. #include <linux/rtc.h>
  22. #include <linux/init.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/seq_file.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/spinlock.h>
  27. #include <linux/io.h>
  28. #include <linux/log2.h>
  29. #include <linux/clk.h>
  30. #include <linux/slab.h>
  31. #ifdef CONFIG_SUPERH
  32. #include <asm/rtc.h>
  33. #else
  34. /* Default values for RZ/A RTC */
  35. #define rtc_reg_size sizeof(u16)
  36. #define RTC_BIT_INVERTED 0 /* no chip bugs */
  37. #define RTC_CAP_4_DIGIT_YEAR (1 << 0)
  38. #define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR
  39. #endif
  40. #define DRV_NAME "sh-rtc"
  41. #define RTC_REG(r) ((r) * rtc_reg_size)
  42. #define R64CNT RTC_REG(0)
  43. #define RSECCNT RTC_REG(1) /* RTC sec */
  44. #define RMINCNT RTC_REG(2) /* RTC min */
  45. #define RHRCNT RTC_REG(3) /* RTC hour */
  46. #define RWKCNT RTC_REG(4) /* RTC week */
  47. #define RDAYCNT RTC_REG(5) /* RTC day */
  48. #define RMONCNT RTC_REG(6) /* RTC month */
  49. #define RYRCNT RTC_REG(7) /* RTC year */
  50. #define RSECAR RTC_REG(8) /* ALARM sec */
  51. #define RMINAR RTC_REG(9) /* ALARM min */
  52. #define RHRAR RTC_REG(10) /* ALARM hour */
  53. #define RWKAR RTC_REG(11) /* ALARM week */
  54. #define RDAYAR RTC_REG(12) /* ALARM day */
  55. #define RMONAR RTC_REG(13) /* ALARM month */
  56. #define RCR1 RTC_REG(14) /* Control */
  57. #define RCR2 RTC_REG(15) /* Control */
  58. /*
  59. * Note on RYRAR and RCR3: Up until this point most of the register
  60. * definitions are consistent across all of the available parts. However,
  61. * the placement of the optional RYRAR and RCR3 (the RYRAR control
  62. * register used to control RYRCNT/RYRAR compare) varies considerably
  63. * across various parts, occasionally being mapped in to a completely
  64. * unrelated address space. For proper RYRAR support a separate resource
  65. * would have to be handed off, but as this is purely optional in
  66. * practice, we simply opt not to support it, thereby keeping the code
  67. * quite a bit more simplified.
  68. */
  69. /* ALARM Bits - or with BCD encoded value */
  70. #define AR_ENB 0x80 /* Enable for alarm cmp */
  71. /* Period Bits */
  72. #define PF_HP 0x100 /* Enable Half Period to support 8,32,128Hz */
  73. #define PF_COUNT 0x200 /* Half periodic counter */
  74. #define PF_OXS 0x400 /* Periodic One x Second */
  75. #define PF_KOU 0x800 /* Kernel or User periodic request 1=kernel */
  76. #define PF_MASK 0xf00
  77. /* RCR1 Bits */
  78. #define RCR1_CF 0x80 /* Carry Flag */
  79. #define RCR1_CIE 0x10 /* Carry Interrupt Enable */
  80. #define RCR1_AIE 0x08 /* Alarm Interrupt Enable */
  81. #define RCR1_AF 0x01 /* Alarm Flag */
  82. /* RCR2 Bits */
  83. #define RCR2_PEF 0x80 /* PEriodic interrupt Flag */
  84. #define RCR2_PESMASK 0x70 /* Periodic interrupt Set */
  85. #define RCR2_RTCEN 0x08 /* ENable RTC */
  86. #define RCR2_ADJ 0x04 /* ADJustment (30-second) */
  87. #define RCR2_RESET 0x02 /* Reset bit */
  88. #define RCR2_START 0x01 /* Start bit */
  89. struct sh_rtc {
  90. void __iomem *regbase;
  91. unsigned long regsize;
  92. struct resource *res;
  93. int alarm_irq;
  94. int periodic_irq;
  95. int carry_irq;
  96. struct clk *clk;
  97. struct rtc_device *rtc_dev;
  98. spinlock_t lock;
  99. unsigned long capabilities; /* See asm/rtc.h for cap bits */
  100. unsigned short periodic_freq;
  101. };
  102. static int __sh_rtc_interrupt(struct sh_rtc *rtc)
  103. {
  104. unsigned int tmp, pending;
  105. tmp = readb(rtc->regbase + RCR1);
  106. pending = tmp & RCR1_CF;
  107. tmp &= ~RCR1_CF;
  108. writeb(tmp, rtc->regbase + RCR1);
  109. /* Users have requested One x Second IRQ */
  110. if (pending && rtc->periodic_freq & PF_OXS)
  111. rtc_update_irq(rtc->rtc_dev, 1, RTC_UF | RTC_IRQF);
  112. return pending;
  113. }
  114. static int __sh_rtc_alarm(struct sh_rtc *rtc)
  115. {
  116. unsigned int tmp, pending;
  117. tmp = readb(rtc->regbase + RCR1);
  118. pending = tmp & RCR1_AF;
  119. tmp &= ~(RCR1_AF | RCR1_AIE);
  120. writeb(tmp, rtc->regbase + RCR1);
  121. if (pending)
  122. rtc_update_irq(rtc->rtc_dev, 1, RTC_AF | RTC_IRQF);
  123. return pending;
  124. }
  125. static int __sh_rtc_periodic(struct sh_rtc *rtc)
  126. {
  127. unsigned int tmp, pending;
  128. tmp = readb(rtc->regbase + RCR2);
  129. pending = tmp & RCR2_PEF;
  130. tmp &= ~RCR2_PEF;
  131. writeb(tmp, rtc->regbase + RCR2);
  132. if (!pending)
  133. return 0;
  134. /* Half period enabled than one skipped and the next notified */
  135. if ((rtc->periodic_freq & PF_HP) && (rtc->periodic_freq & PF_COUNT))
  136. rtc->periodic_freq &= ~PF_COUNT;
  137. else {
  138. if (rtc->periodic_freq & PF_HP)
  139. rtc->periodic_freq |= PF_COUNT;
  140. rtc_update_irq(rtc->rtc_dev, 1, RTC_PF | RTC_IRQF);
  141. }
  142. return pending;
  143. }
  144. static irqreturn_t sh_rtc_interrupt(int irq, void *dev_id)
  145. {
  146. struct sh_rtc *rtc = dev_id;
  147. int ret;
  148. spin_lock(&rtc->lock);
  149. ret = __sh_rtc_interrupt(rtc);
  150. spin_unlock(&rtc->lock);
  151. return IRQ_RETVAL(ret);
  152. }
  153. static irqreturn_t sh_rtc_alarm(int irq, void *dev_id)
  154. {
  155. struct sh_rtc *rtc = dev_id;
  156. int ret;
  157. spin_lock(&rtc->lock);
  158. ret = __sh_rtc_alarm(rtc);
  159. spin_unlock(&rtc->lock);
  160. return IRQ_RETVAL(ret);
  161. }
  162. static irqreturn_t sh_rtc_periodic(int irq, void *dev_id)
  163. {
  164. struct sh_rtc *rtc = dev_id;
  165. int ret;
  166. spin_lock(&rtc->lock);
  167. ret = __sh_rtc_periodic(rtc);
  168. spin_unlock(&rtc->lock);
  169. return IRQ_RETVAL(ret);
  170. }
  171. static irqreturn_t sh_rtc_shared(int irq, void *dev_id)
  172. {
  173. struct sh_rtc *rtc = dev_id;
  174. int ret;
  175. spin_lock(&rtc->lock);
  176. ret = __sh_rtc_interrupt(rtc);
  177. ret |= __sh_rtc_alarm(rtc);
  178. ret |= __sh_rtc_periodic(rtc);
  179. spin_unlock(&rtc->lock);
  180. return IRQ_RETVAL(ret);
  181. }
  182. static inline void sh_rtc_setaie(struct device *dev, unsigned int enable)
  183. {
  184. struct sh_rtc *rtc = dev_get_drvdata(dev);
  185. unsigned int tmp;
  186. spin_lock_irq(&rtc->lock);
  187. tmp = readb(rtc->regbase + RCR1);
  188. if (enable)
  189. tmp |= RCR1_AIE;
  190. else
  191. tmp &= ~RCR1_AIE;
  192. writeb(tmp, rtc->regbase + RCR1);
  193. spin_unlock_irq(&rtc->lock);
  194. }
  195. static int sh_rtc_proc(struct device *dev, struct seq_file *seq)
  196. {
  197. struct sh_rtc *rtc = dev_get_drvdata(dev);
  198. unsigned int tmp;
  199. tmp = readb(rtc->regbase + RCR1);
  200. seq_printf(seq, "carry_IRQ\t: %s\n", (tmp & RCR1_CIE) ? "yes" : "no");
  201. tmp = readb(rtc->regbase + RCR2);
  202. seq_printf(seq, "periodic_IRQ\t: %s\n",
  203. (tmp & RCR2_PESMASK) ? "yes" : "no");
  204. return 0;
  205. }
  206. static inline void sh_rtc_setcie(struct device *dev, unsigned int enable)
  207. {
  208. struct sh_rtc *rtc = dev_get_drvdata(dev);
  209. unsigned int tmp;
  210. spin_lock_irq(&rtc->lock);
  211. tmp = readb(rtc->regbase + RCR1);
  212. if (!enable)
  213. tmp &= ~RCR1_CIE;
  214. else
  215. tmp |= RCR1_CIE;
  216. writeb(tmp, rtc->regbase + RCR1);
  217. spin_unlock_irq(&rtc->lock);
  218. }
  219. static int sh_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
  220. {
  221. sh_rtc_setaie(dev, enabled);
  222. return 0;
  223. }
  224. static int sh_rtc_read_time(struct device *dev, struct rtc_time *tm)
  225. {
  226. struct sh_rtc *rtc = dev_get_drvdata(dev);
  227. unsigned int sec128, sec2, yr, yr100, cf_bit;
  228. do {
  229. unsigned int tmp;
  230. spin_lock_irq(&rtc->lock);
  231. tmp = readb(rtc->regbase + RCR1);
  232. tmp &= ~RCR1_CF; /* Clear CF-bit */
  233. tmp |= RCR1_CIE;
  234. writeb(tmp, rtc->regbase + RCR1);
  235. sec128 = readb(rtc->regbase + R64CNT);
  236. tm->tm_sec = bcd2bin(readb(rtc->regbase + RSECCNT));
  237. tm->tm_min = bcd2bin(readb(rtc->regbase + RMINCNT));
  238. tm->tm_hour = bcd2bin(readb(rtc->regbase + RHRCNT));
  239. tm->tm_wday = bcd2bin(readb(rtc->regbase + RWKCNT));
  240. tm->tm_mday = bcd2bin(readb(rtc->regbase + RDAYCNT));
  241. tm->tm_mon = bcd2bin(readb(rtc->regbase + RMONCNT)) - 1;
  242. if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) {
  243. yr = readw(rtc->regbase + RYRCNT);
  244. yr100 = bcd2bin(yr >> 8);
  245. yr &= 0xff;
  246. } else {
  247. yr = readb(rtc->regbase + RYRCNT);
  248. yr100 = bcd2bin((yr == 0x99) ? 0x19 : 0x20);
  249. }
  250. tm->tm_year = (yr100 * 100 + bcd2bin(yr)) - 1900;
  251. sec2 = readb(rtc->regbase + R64CNT);
  252. cf_bit = readb(rtc->regbase + RCR1) & RCR1_CF;
  253. spin_unlock_irq(&rtc->lock);
  254. } while (cf_bit != 0 || ((sec128 ^ sec2) & RTC_BIT_INVERTED) != 0);
  255. #if RTC_BIT_INVERTED != 0
  256. if ((sec128 & RTC_BIT_INVERTED))
  257. tm->tm_sec--;
  258. #endif
  259. /* only keep the carry interrupt enabled if UIE is on */
  260. if (!(rtc->periodic_freq & PF_OXS))
  261. sh_rtc_setcie(dev, 0);
  262. dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
  263. "mday=%d, mon=%d, year=%d, wday=%d\n",
  264. __func__,
  265. tm->tm_sec, tm->tm_min, tm->tm_hour,
  266. tm->tm_mday, tm->tm_mon + 1, tm->tm_year, tm->tm_wday);
  267. return 0;
  268. }
  269. static int sh_rtc_set_time(struct device *dev, struct rtc_time *tm)
  270. {
  271. struct sh_rtc *rtc = dev_get_drvdata(dev);
  272. unsigned int tmp;
  273. int year;
  274. spin_lock_irq(&rtc->lock);
  275. /* Reset pre-scaler & stop RTC */
  276. tmp = readb(rtc->regbase + RCR2);
  277. tmp |= RCR2_RESET;
  278. tmp &= ~RCR2_START;
  279. writeb(tmp, rtc->regbase + RCR2);
  280. writeb(bin2bcd(tm->tm_sec), rtc->regbase + RSECCNT);
  281. writeb(bin2bcd(tm->tm_min), rtc->regbase + RMINCNT);
  282. writeb(bin2bcd(tm->tm_hour), rtc->regbase + RHRCNT);
  283. writeb(bin2bcd(tm->tm_wday), rtc->regbase + RWKCNT);
  284. writeb(bin2bcd(tm->tm_mday), rtc->regbase + RDAYCNT);
  285. writeb(bin2bcd(tm->tm_mon + 1), rtc->regbase + RMONCNT);
  286. if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) {
  287. year = (bin2bcd((tm->tm_year + 1900) / 100) << 8) |
  288. bin2bcd(tm->tm_year % 100);
  289. writew(year, rtc->regbase + RYRCNT);
  290. } else {
  291. year = tm->tm_year % 100;
  292. writeb(bin2bcd(year), rtc->regbase + RYRCNT);
  293. }
  294. /* Start RTC */
  295. tmp = readb(rtc->regbase + RCR2);
  296. tmp &= ~RCR2_RESET;
  297. tmp |= RCR2_RTCEN | RCR2_START;
  298. writeb(tmp, rtc->regbase + RCR2);
  299. spin_unlock_irq(&rtc->lock);
  300. return 0;
  301. }
  302. static inline int sh_rtc_read_alarm_value(struct sh_rtc *rtc, int reg_off)
  303. {
  304. unsigned int byte;
  305. int value = -1; /* return -1 for ignored values */
  306. byte = readb(rtc->regbase + reg_off);
  307. if (byte & AR_ENB) {
  308. byte &= ~AR_ENB; /* strip the enable bit */
  309. value = bcd2bin(byte);
  310. }
  311. return value;
  312. }
  313. static int sh_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
  314. {
  315. struct sh_rtc *rtc = dev_get_drvdata(dev);
  316. struct rtc_time *tm = &wkalrm->time;
  317. spin_lock_irq(&rtc->lock);
  318. tm->tm_sec = sh_rtc_read_alarm_value(rtc, RSECAR);
  319. tm->tm_min = sh_rtc_read_alarm_value(rtc, RMINAR);
  320. tm->tm_hour = sh_rtc_read_alarm_value(rtc, RHRAR);
  321. tm->tm_wday = sh_rtc_read_alarm_value(rtc, RWKAR);
  322. tm->tm_mday = sh_rtc_read_alarm_value(rtc, RDAYAR);
  323. tm->tm_mon = sh_rtc_read_alarm_value(rtc, RMONAR);
  324. if (tm->tm_mon > 0)
  325. tm->tm_mon -= 1; /* RTC is 1-12, tm_mon is 0-11 */
  326. wkalrm->enabled = (readb(rtc->regbase + RCR1) & RCR1_AIE) ? 1 : 0;
  327. spin_unlock_irq(&rtc->lock);
  328. return 0;
  329. }
  330. static inline void sh_rtc_write_alarm_value(struct sh_rtc *rtc,
  331. int value, int reg_off)
  332. {
  333. /* < 0 for a value that is ignored */
  334. if (value < 0)
  335. writeb(0, rtc->regbase + reg_off);
  336. else
  337. writeb(bin2bcd(value) | AR_ENB, rtc->regbase + reg_off);
  338. }
  339. static int sh_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
  340. {
  341. struct sh_rtc *rtc = dev_get_drvdata(dev);
  342. unsigned int rcr1;
  343. struct rtc_time *tm = &wkalrm->time;
  344. int mon;
  345. spin_lock_irq(&rtc->lock);
  346. /* disable alarm interrupt and clear the alarm flag */
  347. rcr1 = readb(rtc->regbase + RCR1);
  348. rcr1 &= ~(RCR1_AF | RCR1_AIE);
  349. writeb(rcr1, rtc->regbase + RCR1);
  350. /* set alarm time */
  351. sh_rtc_write_alarm_value(rtc, tm->tm_sec, RSECAR);
  352. sh_rtc_write_alarm_value(rtc, tm->tm_min, RMINAR);
  353. sh_rtc_write_alarm_value(rtc, tm->tm_hour, RHRAR);
  354. sh_rtc_write_alarm_value(rtc, tm->tm_wday, RWKAR);
  355. sh_rtc_write_alarm_value(rtc, tm->tm_mday, RDAYAR);
  356. mon = tm->tm_mon;
  357. if (mon >= 0)
  358. mon += 1;
  359. sh_rtc_write_alarm_value(rtc, mon, RMONAR);
  360. if (wkalrm->enabled) {
  361. rcr1 |= RCR1_AIE;
  362. writeb(rcr1, rtc->regbase + RCR1);
  363. }
  364. spin_unlock_irq(&rtc->lock);
  365. return 0;
  366. }
  367. static const struct rtc_class_ops sh_rtc_ops = {
  368. .read_time = sh_rtc_read_time,
  369. .set_time = sh_rtc_set_time,
  370. .read_alarm = sh_rtc_read_alarm,
  371. .set_alarm = sh_rtc_set_alarm,
  372. .proc = sh_rtc_proc,
  373. .alarm_irq_enable = sh_rtc_alarm_irq_enable,
  374. };
  375. static int __init sh_rtc_probe(struct platform_device *pdev)
  376. {
  377. struct sh_rtc *rtc;
  378. struct resource *res;
  379. struct rtc_time r;
  380. char clk_name[6];
  381. int clk_id, ret;
  382. rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
  383. if (unlikely(!rtc))
  384. return -ENOMEM;
  385. spin_lock_init(&rtc->lock);
  386. /* get periodic/carry/alarm irqs */
  387. ret = platform_get_irq(pdev, 0);
  388. if (unlikely(ret <= 0)) {
  389. dev_err(&pdev->dev, "No IRQ resource\n");
  390. return -ENOENT;
  391. }
  392. rtc->periodic_irq = ret;
  393. rtc->carry_irq = platform_get_irq(pdev, 1);
  394. rtc->alarm_irq = platform_get_irq(pdev, 2);
  395. res = platform_get_resource(pdev, IORESOURCE_IO, 0);
  396. if (!res)
  397. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  398. if (unlikely(res == NULL)) {
  399. dev_err(&pdev->dev, "No IO resource\n");
  400. return -ENOENT;
  401. }
  402. rtc->regsize = resource_size(res);
  403. rtc->res = devm_request_mem_region(&pdev->dev, res->start,
  404. rtc->regsize, pdev->name);
  405. if (unlikely(!rtc->res))
  406. return -EBUSY;
  407. rtc->regbase = devm_ioremap_nocache(&pdev->dev, rtc->res->start,
  408. rtc->regsize);
  409. if (unlikely(!rtc->regbase))
  410. return -EINVAL;
  411. if (!pdev->dev.of_node) {
  412. clk_id = pdev->id;
  413. /* With a single device, the clock id is still "rtc0" */
  414. if (clk_id < 0)
  415. clk_id = 0;
  416. snprintf(clk_name, sizeof(clk_name), "rtc%d", clk_id);
  417. } else
  418. snprintf(clk_name, sizeof(clk_name), "fck");
  419. rtc->clk = devm_clk_get(&pdev->dev, clk_name);
  420. if (IS_ERR(rtc->clk)) {
  421. /*
  422. * No error handling for rtc->clk intentionally, not all
  423. * platforms will have a unique clock for the RTC, and
  424. * the clk API can handle the struct clk pointer being
  425. * NULL.
  426. */
  427. rtc->clk = NULL;
  428. }
  429. clk_enable(rtc->clk);
  430. rtc->capabilities = RTC_DEF_CAPABILITIES;
  431. #ifdef CONFIG_SUPERH
  432. if (dev_get_platdata(&pdev->dev)) {
  433. struct sh_rtc_platform_info *pinfo =
  434. dev_get_platdata(&pdev->dev);
  435. /*
  436. * Some CPUs have special capabilities in addition to the
  437. * default set. Add those in here.
  438. */
  439. rtc->capabilities |= pinfo->capabilities;
  440. }
  441. #endif
  442. if (rtc->carry_irq <= 0) {
  443. /* register shared periodic/carry/alarm irq */
  444. ret = devm_request_irq(&pdev->dev, rtc->periodic_irq,
  445. sh_rtc_shared, 0, "sh-rtc", rtc);
  446. if (unlikely(ret)) {
  447. dev_err(&pdev->dev,
  448. "request IRQ failed with %d, IRQ %d\n", ret,
  449. rtc->periodic_irq);
  450. goto err_unmap;
  451. }
  452. } else {
  453. /* register periodic/carry/alarm irqs */
  454. ret = devm_request_irq(&pdev->dev, rtc->periodic_irq,
  455. sh_rtc_periodic, 0, "sh-rtc period", rtc);
  456. if (unlikely(ret)) {
  457. dev_err(&pdev->dev,
  458. "request period IRQ failed with %d, IRQ %d\n",
  459. ret, rtc->periodic_irq);
  460. goto err_unmap;
  461. }
  462. ret = devm_request_irq(&pdev->dev, rtc->carry_irq,
  463. sh_rtc_interrupt, 0, "sh-rtc carry", rtc);
  464. if (unlikely(ret)) {
  465. dev_err(&pdev->dev,
  466. "request carry IRQ failed with %d, IRQ %d\n",
  467. ret, rtc->carry_irq);
  468. goto err_unmap;
  469. }
  470. ret = devm_request_irq(&pdev->dev, rtc->alarm_irq,
  471. sh_rtc_alarm, 0, "sh-rtc alarm", rtc);
  472. if (unlikely(ret)) {
  473. dev_err(&pdev->dev,
  474. "request alarm IRQ failed with %d, IRQ %d\n",
  475. ret, rtc->alarm_irq);
  476. goto err_unmap;
  477. }
  478. }
  479. platform_set_drvdata(pdev, rtc);
  480. /* everything disabled by default */
  481. sh_rtc_setaie(&pdev->dev, 0);
  482. sh_rtc_setcie(&pdev->dev, 0);
  483. rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, "sh",
  484. &sh_rtc_ops, THIS_MODULE);
  485. if (IS_ERR(rtc->rtc_dev)) {
  486. ret = PTR_ERR(rtc->rtc_dev);
  487. goto err_unmap;
  488. }
  489. rtc->rtc_dev->max_user_freq = 256;
  490. /* reset rtc to epoch 0 if time is invalid */
  491. if (rtc_read_time(rtc->rtc_dev, &r) < 0) {
  492. rtc_time_to_tm(0, &r);
  493. rtc_set_time(rtc->rtc_dev, &r);
  494. }
  495. device_init_wakeup(&pdev->dev, 1);
  496. return 0;
  497. err_unmap:
  498. clk_disable(rtc->clk);
  499. return ret;
  500. }
  501. static int __exit sh_rtc_remove(struct platform_device *pdev)
  502. {
  503. struct sh_rtc *rtc = platform_get_drvdata(pdev);
  504. sh_rtc_setaie(&pdev->dev, 0);
  505. sh_rtc_setcie(&pdev->dev, 0);
  506. clk_disable(rtc->clk);
  507. return 0;
  508. }
  509. static void sh_rtc_set_irq_wake(struct device *dev, int enabled)
  510. {
  511. struct sh_rtc *rtc = dev_get_drvdata(dev);
  512. irq_set_irq_wake(rtc->periodic_irq, enabled);
  513. if (rtc->carry_irq > 0) {
  514. irq_set_irq_wake(rtc->carry_irq, enabled);
  515. irq_set_irq_wake(rtc->alarm_irq, enabled);
  516. }
  517. }
  518. static int __maybe_unused sh_rtc_suspend(struct device *dev)
  519. {
  520. if (device_may_wakeup(dev))
  521. sh_rtc_set_irq_wake(dev, 1);
  522. return 0;
  523. }
  524. static int __maybe_unused sh_rtc_resume(struct device *dev)
  525. {
  526. if (device_may_wakeup(dev))
  527. sh_rtc_set_irq_wake(dev, 0);
  528. return 0;
  529. }
  530. static SIMPLE_DEV_PM_OPS(sh_rtc_pm_ops, sh_rtc_suspend, sh_rtc_resume);
  531. static const struct of_device_id sh_rtc_of_match[] = {
  532. { .compatible = "renesas,sh-rtc", },
  533. { /* sentinel */ }
  534. };
  535. MODULE_DEVICE_TABLE(of, sh_rtc_of_match);
  536. static struct platform_driver sh_rtc_platform_driver = {
  537. .driver = {
  538. .name = DRV_NAME,
  539. .pm = &sh_rtc_pm_ops,
  540. .of_match_table = sh_rtc_of_match,
  541. },
  542. .remove = __exit_p(sh_rtc_remove),
  543. };
  544. module_platform_driver_probe(sh_rtc_platform_driver, sh_rtc_probe);
  545. MODULE_DESCRIPTION("SuperH on-chip RTC driver");
  546. MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>, "
  547. "Jamie Lenehan <lenehan@twibble.org>, "
  548. "Angelo Castello <angelo.castello@st.com>");
  549. MODULE_LICENSE("GPL");
  550. MODULE_ALIAS("platform:" DRV_NAME);