rtc-r7301.c 11 KB

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  1. /*
  2. * EPSON TOYOCOM RTC-7301SF/DG Driver
  3. *
  4. * Copyright (c) 2016 Akinobu Mita <akinobu.mita@gmail.com>
  5. *
  6. * Based on rtc-rp5c01.c
  7. *
  8. * Datasheet: http://www5.epsondevice.com/en/products/parallel/rtc7301sf.html
  9. */
  10. #include <linux/io.h>
  11. #include <linux/kernel.h>
  12. #include <linux/module.h>
  13. #include <linux/mod_devicetable.h>
  14. #include <linux/delay.h>
  15. #include <linux/regmap.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/rtc.h>
  18. #define DRV_NAME "rtc-r7301"
  19. #define RTC7301_1_SEC 0x0 /* Bank 0 and Band 1 */
  20. #define RTC7301_10_SEC 0x1 /* Bank 0 and Band 1 */
  21. #define RTC7301_AE BIT(3)
  22. #define RTC7301_1_MIN 0x2 /* Bank 0 and Band 1 */
  23. #define RTC7301_10_MIN 0x3 /* Bank 0 and Band 1 */
  24. #define RTC7301_1_HOUR 0x4 /* Bank 0 and Band 1 */
  25. #define RTC7301_10_HOUR 0x5 /* Bank 0 and Band 1 */
  26. #define RTC7301_DAY_OF_WEEK 0x6 /* Bank 0 and Band 1 */
  27. #define RTC7301_1_DAY 0x7 /* Bank 0 and Band 1 */
  28. #define RTC7301_10_DAY 0x8 /* Bank 0 and Band 1 */
  29. #define RTC7301_1_MONTH 0x9 /* Bank 0 */
  30. #define RTC7301_10_MONTH 0xa /* Bank 0 */
  31. #define RTC7301_1_YEAR 0xb /* Bank 0 */
  32. #define RTC7301_10_YEAR 0xc /* Bank 0 */
  33. #define RTC7301_100_YEAR 0xd /* Bank 0 */
  34. #define RTC7301_1000_YEAR 0xe /* Bank 0 */
  35. #define RTC7301_ALARM_CONTROL 0xe /* Bank 1 */
  36. #define RTC7301_ALARM_CONTROL_AIE BIT(0)
  37. #define RTC7301_ALARM_CONTROL_AF BIT(1)
  38. #define RTC7301_TIMER_CONTROL 0xe /* Bank 2 */
  39. #define RTC7301_TIMER_CONTROL_TIE BIT(0)
  40. #define RTC7301_TIMER_CONTROL_TF BIT(1)
  41. #define RTC7301_CONTROL 0xf /* All banks */
  42. #define RTC7301_CONTROL_BUSY BIT(0)
  43. #define RTC7301_CONTROL_STOP BIT(1)
  44. #define RTC7301_CONTROL_BANK_SEL_0 BIT(2)
  45. #define RTC7301_CONTROL_BANK_SEL_1 BIT(3)
  46. struct rtc7301_priv {
  47. struct regmap *regmap;
  48. int irq;
  49. spinlock_t lock;
  50. u8 bank;
  51. };
  52. static const struct regmap_config rtc7301_regmap_config = {
  53. .reg_bits = 32,
  54. .val_bits = 8,
  55. .reg_stride = 4,
  56. };
  57. static u8 rtc7301_read(struct rtc7301_priv *priv, unsigned int reg)
  58. {
  59. int reg_stride = regmap_get_reg_stride(priv->regmap);
  60. unsigned int val;
  61. regmap_read(priv->regmap, reg_stride * reg, &val);
  62. return val & 0xf;
  63. }
  64. static void rtc7301_write(struct rtc7301_priv *priv, u8 val, unsigned int reg)
  65. {
  66. int reg_stride = regmap_get_reg_stride(priv->regmap);
  67. regmap_write(priv->regmap, reg_stride * reg, val);
  68. }
  69. static void rtc7301_update_bits(struct rtc7301_priv *priv, unsigned int reg,
  70. u8 mask, u8 val)
  71. {
  72. int reg_stride = regmap_get_reg_stride(priv->regmap);
  73. regmap_update_bits(priv->regmap, reg_stride * reg, mask, val);
  74. }
  75. static int rtc7301_wait_while_busy(struct rtc7301_priv *priv)
  76. {
  77. int retries = 100;
  78. while (retries-- > 0) {
  79. u8 val;
  80. val = rtc7301_read(priv, RTC7301_CONTROL);
  81. if (!(val & RTC7301_CONTROL_BUSY))
  82. return 0;
  83. udelay(300);
  84. }
  85. return -ETIMEDOUT;
  86. }
  87. static void rtc7301_stop(struct rtc7301_priv *priv)
  88. {
  89. rtc7301_update_bits(priv, RTC7301_CONTROL, RTC7301_CONTROL_STOP,
  90. RTC7301_CONTROL_STOP);
  91. }
  92. static void rtc7301_start(struct rtc7301_priv *priv)
  93. {
  94. rtc7301_update_bits(priv, RTC7301_CONTROL, RTC7301_CONTROL_STOP, 0);
  95. }
  96. static void rtc7301_select_bank(struct rtc7301_priv *priv, u8 bank)
  97. {
  98. u8 val = 0;
  99. if (bank == priv->bank)
  100. return;
  101. if (bank & BIT(0))
  102. val |= RTC7301_CONTROL_BANK_SEL_0;
  103. if (bank & BIT(1))
  104. val |= RTC7301_CONTROL_BANK_SEL_1;
  105. rtc7301_update_bits(priv, RTC7301_CONTROL,
  106. RTC7301_CONTROL_BANK_SEL_0 |
  107. RTC7301_CONTROL_BANK_SEL_1, val);
  108. priv->bank = bank;
  109. }
  110. static void rtc7301_get_time(struct rtc7301_priv *priv, struct rtc_time *tm,
  111. bool alarm)
  112. {
  113. int year;
  114. tm->tm_sec = rtc7301_read(priv, RTC7301_1_SEC);
  115. tm->tm_sec += (rtc7301_read(priv, RTC7301_10_SEC) & ~RTC7301_AE) * 10;
  116. tm->tm_min = rtc7301_read(priv, RTC7301_1_MIN);
  117. tm->tm_min += (rtc7301_read(priv, RTC7301_10_MIN) & ~RTC7301_AE) * 10;
  118. tm->tm_hour = rtc7301_read(priv, RTC7301_1_HOUR);
  119. tm->tm_hour += (rtc7301_read(priv, RTC7301_10_HOUR) & ~RTC7301_AE) * 10;
  120. tm->tm_mday = rtc7301_read(priv, RTC7301_1_DAY);
  121. tm->tm_mday += (rtc7301_read(priv, RTC7301_10_DAY) & ~RTC7301_AE) * 10;
  122. if (alarm) {
  123. tm->tm_wday = -1;
  124. tm->tm_mon = -1;
  125. tm->tm_year = -1;
  126. tm->tm_yday = -1;
  127. tm->tm_isdst = -1;
  128. return;
  129. }
  130. tm->tm_wday = (rtc7301_read(priv, RTC7301_DAY_OF_WEEK) & ~RTC7301_AE);
  131. tm->tm_mon = rtc7301_read(priv, RTC7301_10_MONTH) * 10 +
  132. rtc7301_read(priv, RTC7301_1_MONTH) - 1;
  133. year = rtc7301_read(priv, RTC7301_1000_YEAR) * 1000 +
  134. rtc7301_read(priv, RTC7301_100_YEAR) * 100 +
  135. rtc7301_read(priv, RTC7301_10_YEAR) * 10 +
  136. rtc7301_read(priv, RTC7301_1_YEAR);
  137. tm->tm_year = year - 1900;
  138. }
  139. static void rtc7301_write_time(struct rtc7301_priv *priv, struct rtc_time *tm,
  140. bool alarm)
  141. {
  142. int year;
  143. rtc7301_write(priv, tm->tm_sec % 10, RTC7301_1_SEC);
  144. rtc7301_write(priv, tm->tm_sec / 10, RTC7301_10_SEC);
  145. rtc7301_write(priv, tm->tm_min % 10, RTC7301_1_MIN);
  146. rtc7301_write(priv, tm->tm_min / 10, RTC7301_10_MIN);
  147. rtc7301_write(priv, tm->tm_hour % 10, RTC7301_1_HOUR);
  148. rtc7301_write(priv, tm->tm_hour / 10, RTC7301_10_HOUR);
  149. rtc7301_write(priv, tm->tm_mday % 10, RTC7301_1_DAY);
  150. rtc7301_write(priv, tm->tm_mday / 10, RTC7301_10_DAY);
  151. /* Don't care for alarm register */
  152. rtc7301_write(priv, alarm ? RTC7301_AE : tm->tm_wday,
  153. RTC7301_DAY_OF_WEEK);
  154. if (alarm)
  155. return;
  156. rtc7301_write(priv, (tm->tm_mon + 1) % 10, RTC7301_1_MONTH);
  157. rtc7301_write(priv, (tm->tm_mon + 1) / 10, RTC7301_10_MONTH);
  158. year = tm->tm_year + 1900;
  159. rtc7301_write(priv, year % 10, RTC7301_1_YEAR);
  160. rtc7301_write(priv, (year / 10) % 10, RTC7301_10_YEAR);
  161. rtc7301_write(priv, (year / 100) % 10, RTC7301_100_YEAR);
  162. rtc7301_write(priv, year / 1000, RTC7301_1000_YEAR);
  163. }
  164. static void rtc7301_alarm_irq(struct rtc7301_priv *priv, unsigned int enabled)
  165. {
  166. rtc7301_update_bits(priv, RTC7301_ALARM_CONTROL,
  167. RTC7301_ALARM_CONTROL_AF |
  168. RTC7301_ALARM_CONTROL_AIE,
  169. enabled ? RTC7301_ALARM_CONTROL_AIE : 0);
  170. }
  171. static int rtc7301_read_time(struct device *dev, struct rtc_time *tm)
  172. {
  173. struct rtc7301_priv *priv = dev_get_drvdata(dev);
  174. unsigned long flags;
  175. int err;
  176. spin_lock_irqsave(&priv->lock, flags);
  177. rtc7301_select_bank(priv, 0);
  178. err = rtc7301_wait_while_busy(priv);
  179. if (!err)
  180. rtc7301_get_time(priv, tm, false);
  181. spin_unlock_irqrestore(&priv->lock, flags);
  182. return err;
  183. }
  184. static int rtc7301_set_time(struct device *dev, struct rtc_time *tm)
  185. {
  186. struct rtc7301_priv *priv = dev_get_drvdata(dev);
  187. unsigned long flags;
  188. spin_lock_irqsave(&priv->lock, flags);
  189. rtc7301_stop(priv);
  190. udelay(300);
  191. rtc7301_select_bank(priv, 0);
  192. rtc7301_write_time(priv, tm, false);
  193. rtc7301_start(priv);
  194. spin_unlock_irqrestore(&priv->lock, flags);
  195. return 0;
  196. }
  197. static int rtc7301_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
  198. {
  199. struct rtc7301_priv *priv = dev_get_drvdata(dev);
  200. unsigned long flags;
  201. u8 alrm_ctrl;
  202. if (priv->irq <= 0)
  203. return -EINVAL;
  204. spin_lock_irqsave(&priv->lock, flags);
  205. rtc7301_select_bank(priv, 1);
  206. rtc7301_get_time(priv, &alarm->time, true);
  207. alrm_ctrl = rtc7301_read(priv, RTC7301_ALARM_CONTROL);
  208. alarm->enabled = !!(alrm_ctrl & RTC7301_ALARM_CONTROL_AIE);
  209. alarm->pending = !!(alrm_ctrl & RTC7301_ALARM_CONTROL_AF);
  210. spin_unlock_irqrestore(&priv->lock, flags);
  211. return 0;
  212. }
  213. static int rtc7301_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
  214. {
  215. struct rtc7301_priv *priv = dev_get_drvdata(dev);
  216. unsigned long flags;
  217. if (priv->irq <= 0)
  218. return -EINVAL;
  219. spin_lock_irqsave(&priv->lock, flags);
  220. rtc7301_select_bank(priv, 1);
  221. rtc7301_write_time(priv, &alarm->time, true);
  222. rtc7301_alarm_irq(priv, alarm->enabled);
  223. spin_unlock_irqrestore(&priv->lock, flags);
  224. return 0;
  225. }
  226. static int rtc7301_alarm_irq_enable(struct device *dev, unsigned int enabled)
  227. {
  228. struct rtc7301_priv *priv = dev_get_drvdata(dev);
  229. unsigned long flags;
  230. if (priv->irq <= 0)
  231. return -EINVAL;
  232. spin_lock_irqsave(&priv->lock, flags);
  233. rtc7301_select_bank(priv, 1);
  234. rtc7301_alarm_irq(priv, enabled);
  235. spin_unlock_irqrestore(&priv->lock, flags);
  236. return 0;
  237. }
  238. static const struct rtc_class_ops rtc7301_rtc_ops = {
  239. .read_time = rtc7301_read_time,
  240. .set_time = rtc7301_set_time,
  241. .read_alarm = rtc7301_read_alarm,
  242. .set_alarm = rtc7301_set_alarm,
  243. .alarm_irq_enable = rtc7301_alarm_irq_enable,
  244. };
  245. static irqreturn_t rtc7301_irq_handler(int irq, void *dev_id)
  246. {
  247. struct rtc_device *rtc = dev_id;
  248. struct rtc7301_priv *priv = dev_get_drvdata(rtc->dev.parent);
  249. unsigned long flags;
  250. irqreturn_t ret = IRQ_NONE;
  251. u8 alrm_ctrl;
  252. spin_lock_irqsave(&priv->lock, flags);
  253. rtc7301_select_bank(priv, 1);
  254. alrm_ctrl = rtc7301_read(priv, RTC7301_ALARM_CONTROL);
  255. if (alrm_ctrl & RTC7301_ALARM_CONTROL_AF) {
  256. ret = IRQ_HANDLED;
  257. rtc7301_alarm_irq(priv, false);
  258. rtc_update_irq(rtc, 1, RTC_IRQF | RTC_AF);
  259. }
  260. spin_unlock_irqrestore(&priv->lock, flags);
  261. return ret;
  262. }
  263. static void rtc7301_init(struct rtc7301_priv *priv)
  264. {
  265. unsigned long flags;
  266. spin_lock_irqsave(&priv->lock, flags);
  267. rtc7301_select_bank(priv, 2);
  268. rtc7301_write(priv, 0, RTC7301_TIMER_CONTROL);
  269. spin_unlock_irqrestore(&priv->lock, flags);
  270. }
  271. static int __init rtc7301_rtc_probe(struct platform_device *dev)
  272. {
  273. struct resource *res;
  274. void __iomem *regs;
  275. struct rtc7301_priv *priv;
  276. struct rtc_device *rtc;
  277. int ret;
  278. res = platform_get_resource(dev, IORESOURCE_MEM, 0);
  279. if (!res)
  280. return -ENODEV;
  281. priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
  282. if (!priv)
  283. return -ENOMEM;
  284. regs = devm_ioremap_resource(&dev->dev, res);
  285. if (IS_ERR(regs))
  286. return PTR_ERR(regs);
  287. priv->regmap = devm_regmap_init_mmio(&dev->dev, regs,
  288. &rtc7301_regmap_config);
  289. if (IS_ERR(priv->regmap))
  290. return PTR_ERR(priv->regmap);
  291. priv->irq = platform_get_irq(dev, 0);
  292. spin_lock_init(&priv->lock);
  293. priv->bank = -1;
  294. rtc7301_init(priv);
  295. platform_set_drvdata(dev, priv);
  296. rtc = devm_rtc_device_register(&dev->dev, DRV_NAME, &rtc7301_rtc_ops,
  297. THIS_MODULE);
  298. if (IS_ERR(rtc))
  299. return PTR_ERR(rtc);
  300. if (priv->irq > 0) {
  301. ret = devm_request_irq(&dev->dev, priv->irq,
  302. rtc7301_irq_handler, IRQF_SHARED,
  303. dev_name(&dev->dev), rtc);
  304. if (ret) {
  305. priv->irq = 0;
  306. dev_err(&dev->dev, "unable to request IRQ\n");
  307. } else {
  308. device_set_wakeup_capable(&dev->dev, true);
  309. }
  310. }
  311. return 0;
  312. }
  313. #ifdef CONFIG_PM_SLEEP
  314. static int rtc7301_suspend(struct device *dev)
  315. {
  316. struct rtc7301_priv *priv = dev_get_drvdata(dev);
  317. if (device_may_wakeup(dev))
  318. enable_irq_wake(priv->irq);
  319. return 0;
  320. }
  321. static int rtc7301_resume(struct device *dev)
  322. {
  323. struct rtc7301_priv *priv = dev_get_drvdata(dev);
  324. if (device_may_wakeup(dev))
  325. disable_irq_wake(priv->irq);
  326. return 0;
  327. }
  328. #endif
  329. static SIMPLE_DEV_PM_OPS(rtc7301_pm_ops, rtc7301_suspend, rtc7301_resume);
  330. static const struct of_device_id rtc7301_dt_match[] = {
  331. { .compatible = "epson,rtc7301sf" },
  332. { .compatible = "epson,rtc7301dg" },
  333. {}
  334. };
  335. MODULE_DEVICE_TABLE(of, rtc7301_dt_match);
  336. static struct platform_driver rtc7301_rtc_driver = {
  337. .driver = {
  338. .name = DRV_NAME,
  339. .of_match_table = rtc7301_dt_match,
  340. .pm = &rtc7301_pm_ops,
  341. },
  342. };
  343. module_platform_driver_probe(rtc7301_rtc_driver, rtc7301_rtc_probe);
  344. MODULE_AUTHOR("Akinobu Mita <akinobu.mita@gmail.com>");
  345. MODULE_LICENSE("GPL");
  346. MODULE_DESCRIPTION("EPSON TOYOCOM RTC-7301SF/DG Driver");
  347. MODULE_ALIAS("platform:rtc-r7301");