rtc-mt7622.c 10 KB

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  1. /*
  2. * Driver for MediaTek SoC based RTC
  3. *
  4. * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License as
  8. * published by the Free Software Foundation; either version 2 of
  9. * the License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. */
  16. #include <linux/clk.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/module.h>
  19. #include <linux/of_address.h>
  20. #include <linux/of_device.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/rtc.h>
  23. #define MTK_RTC_DEV KBUILD_MODNAME
  24. #define MTK_RTC_PWRCHK1 0x4
  25. #define RTC_PWRCHK1_MAGIC 0xc6
  26. #define MTK_RTC_PWRCHK2 0x8
  27. #define RTC_PWRCHK2_MAGIC 0x9a
  28. #define MTK_RTC_KEY 0xc
  29. #define RTC_KEY_MAGIC 0x59
  30. #define MTK_RTC_PROT1 0x10
  31. #define RTC_PROT1_MAGIC 0xa3
  32. #define MTK_RTC_PROT2 0x14
  33. #define RTC_PROT2_MAGIC 0x57
  34. #define MTK_RTC_PROT3 0x18
  35. #define RTC_PROT3_MAGIC 0x67
  36. #define MTK_RTC_PROT4 0x1c
  37. #define RTC_PROT4_MAGIC 0xd2
  38. #define MTK_RTC_CTL 0x20
  39. #define RTC_RC_STOP BIT(0)
  40. #define MTK_RTC_DEBNCE 0x2c
  41. #define RTC_DEBNCE_MASK GENMASK(2, 0)
  42. #define MTK_RTC_INT 0x30
  43. #define RTC_INT_AL_STA BIT(4)
  44. /*
  45. * Ranges from 0x40 to 0x78 provide RTC time setup for year, month,
  46. * day of month, day of week, hour, minute and second.
  47. */
  48. #define MTK_RTC_TREG(_t, _f) (0x40 + (0x4 * (_f)) + ((_t) * 0x20))
  49. #define MTK_RTC_AL_CTL 0x7c
  50. #define RTC_AL_EN BIT(0)
  51. #define RTC_AL_ALL GENMASK(7, 0)
  52. /*
  53. * The offset is used in the translation for the year between in struct
  54. * rtc_time and in hardware register MTK_RTC_TREG(x,MTK_YEA)
  55. */
  56. #define MTK_RTC_TM_YR_OFFSET 100
  57. /*
  58. * The lowest value for the valid tm_year. RTC hardware would take incorrectly
  59. * tm_year 100 as not a leap year and thus it is also required being excluded
  60. * from the valid options.
  61. */
  62. #define MTK_RTC_TM_YR_L (MTK_RTC_TM_YR_OFFSET + 1)
  63. /*
  64. * The most year the RTC can hold is 99 and the next to 99 in year register
  65. * would be wraparound to 0, for MT7622.
  66. */
  67. #define MTK_RTC_HW_YR_LIMIT 99
  68. /* The highest value for the valid tm_year */
  69. #define MTK_RTC_TM_YR_H (MTK_RTC_TM_YR_OFFSET + MTK_RTC_HW_YR_LIMIT)
  70. /* Simple macro helps to check whether the hardware supports the tm_year */
  71. #define MTK_RTC_TM_YR_VALID(_y) ((_y) >= MTK_RTC_TM_YR_L && \
  72. (_y) <= MTK_RTC_TM_YR_H)
  73. /* Types of the function the RTC provides are time counter and alarm. */
  74. enum {
  75. MTK_TC,
  76. MTK_AL,
  77. };
  78. /* Indexes are used for the pointer to relevant registers in MTK_RTC_TREG */
  79. enum {
  80. MTK_YEA,
  81. MTK_MON,
  82. MTK_DOM,
  83. MTK_DOW,
  84. MTK_HOU,
  85. MTK_MIN,
  86. MTK_SEC
  87. };
  88. struct mtk_rtc {
  89. struct rtc_device *rtc;
  90. void __iomem *base;
  91. int irq;
  92. struct clk *clk;
  93. };
  94. static void mtk_w32(struct mtk_rtc *rtc, u32 reg, u32 val)
  95. {
  96. writel_relaxed(val, rtc->base + reg);
  97. }
  98. static u32 mtk_r32(struct mtk_rtc *rtc, u32 reg)
  99. {
  100. return readl_relaxed(rtc->base + reg);
  101. }
  102. static void mtk_rmw(struct mtk_rtc *rtc, u32 reg, u32 mask, u32 set)
  103. {
  104. u32 val;
  105. val = mtk_r32(rtc, reg);
  106. val &= ~mask;
  107. val |= set;
  108. mtk_w32(rtc, reg, val);
  109. }
  110. static void mtk_set(struct mtk_rtc *rtc, u32 reg, u32 val)
  111. {
  112. mtk_rmw(rtc, reg, 0, val);
  113. }
  114. static void mtk_clr(struct mtk_rtc *rtc, u32 reg, u32 val)
  115. {
  116. mtk_rmw(rtc, reg, val, 0);
  117. }
  118. static void mtk_rtc_hw_init(struct mtk_rtc *hw)
  119. {
  120. /* The setup of the init sequence is for allowing RTC got to work */
  121. mtk_w32(hw, MTK_RTC_PWRCHK1, RTC_PWRCHK1_MAGIC);
  122. mtk_w32(hw, MTK_RTC_PWRCHK2, RTC_PWRCHK2_MAGIC);
  123. mtk_w32(hw, MTK_RTC_KEY, RTC_KEY_MAGIC);
  124. mtk_w32(hw, MTK_RTC_PROT1, RTC_PROT1_MAGIC);
  125. mtk_w32(hw, MTK_RTC_PROT2, RTC_PROT2_MAGIC);
  126. mtk_w32(hw, MTK_RTC_PROT3, RTC_PROT3_MAGIC);
  127. mtk_w32(hw, MTK_RTC_PROT4, RTC_PROT4_MAGIC);
  128. mtk_rmw(hw, MTK_RTC_DEBNCE, RTC_DEBNCE_MASK, 0);
  129. mtk_clr(hw, MTK_RTC_CTL, RTC_RC_STOP);
  130. }
  131. static void mtk_rtc_get_alarm_or_time(struct mtk_rtc *hw, struct rtc_time *tm,
  132. int time_alarm)
  133. {
  134. u32 year, mon, mday, wday, hour, min, sec;
  135. /*
  136. * Read again until the field of the second is not changed which
  137. * ensures all fields in the consistent state. Note that MTK_SEC must
  138. * be read first. In this way, it guarantees the others remain not
  139. * changed when the results for two MTK_SEC consecutive reads are same.
  140. */
  141. do {
  142. sec = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_SEC));
  143. min = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_MIN));
  144. hour = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_HOU));
  145. wday = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_DOW));
  146. mday = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_DOM));
  147. mon = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_MON));
  148. year = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_YEA));
  149. } while (sec != mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_SEC)));
  150. tm->tm_sec = sec;
  151. tm->tm_min = min;
  152. tm->tm_hour = hour;
  153. tm->tm_wday = wday;
  154. tm->tm_mday = mday;
  155. tm->tm_mon = mon - 1;
  156. /* Rebase to the absolute year which userspace queries */
  157. tm->tm_year = year + MTK_RTC_TM_YR_OFFSET;
  158. }
  159. static void mtk_rtc_set_alarm_or_time(struct mtk_rtc *hw, struct rtc_time *tm,
  160. int time_alarm)
  161. {
  162. u32 year;
  163. /* Rebase to the relative year which RTC hardware requires */
  164. year = tm->tm_year - MTK_RTC_TM_YR_OFFSET;
  165. mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_YEA), year);
  166. mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_MON), tm->tm_mon + 1);
  167. mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_DOW), tm->tm_wday);
  168. mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_DOM), tm->tm_mday);
  169. mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_HOU), tm->tm_hour);
  170. mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_MIN), tm->tm_min);
  171. mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_SEC), tm->tm_sec);
  172. }
  173. static irqreturn_t mtk_rtc_alarmirq(int irq, void *id)
  174. {
  175. struct mtk_rtc *hw = (struct mtk_rtc *)id;
  176. u32 irq_sta;
  177. irq_sta = mtk_r32(hw, MTK_RTC_INT);
  178. if (irq_sta & RTC_INT_AL_STA) {
  179. /* Stop alarm also implicitly disables the alarm interrupt */
  180. mtk_w32(hw, MTK_RTC_AL_CTL, 0);
  181. rtc_update_irq(hw->rtc, 1, RTC_IRQF | RTC_AF);
  182. /* Ack alarm interrupt status */
  183. mtk_w32(hw, MTK_RTC_INT, RTC_INT_AL_STA);
  184. return IRQ_HANDLED;
  185. }
  186. return IRQ_NONE;
  187. }
  188. static int mtk_rtc_gettime(struct device *dev, struct rtc_time *tm)
  189. {
  190. struct mtk_rtc *hw = dev_get_drvdata(dev);
  191. mtk_rtc_get_alarm_or_time(hw, tm, MTK_TC);
  192. return 0;
  193. }
  194. static int mtk_rtc_settime(struct device *dev, struct rtc_time *tm)
  195. {
  196. struct mtk_rtc *hw = dev_get_drvdata(dev);
  197. if (!MTK_RTC_TM_YR_VALID(tm->tm_year))
  198. return -EINVAL;
  199. /* Stop time counter before setting a new one*/
  200. mtk_set(hw, MTK_RTC_CTL, RTC_RC_STOP);
  201. mtk_rtc_set_alarm_or_time(hw, tm, MTK_TC);
  202. /* Restart the time counter */
  203. mtk_clr(hw, MTK_RTC_CTL, RTC_RC_STOP);
  204. return 0;
  205. }
  206. static int mtk_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
  207. {
  208. struct mtk_rtc *hw = dev_get_drvdata(dev);
  209. struct rtc_time *alrm_tm = &wkalrm->time;
  210. mtk_rtc_get_alarm_or_time(hw, alrm_tm, MTK_AL);
  211. wkalrm->enabled = !!(mtk_r32(hw, MTK_RTC_AL_CTL) & RTC_AL_EN);
  212. wkalrm->pending = !!(mtk_r32(hw, MTK_RTC_INT) & RTC_INT_AL_STA);
  213. return 0;
  214. }
  215. static int mtk_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
  216. {
  217. struct mtk_rtc *hw = dev_get_drvdata(dev);
  218. struct rtc_time *alrm_tm = &wkalrm->time;
  219. if (!MTK_RTC_TM_YR_VALID(alrm_tm->tm_year))
  220. return -EINVAL;
  221. /*
  222. * Stop the alarm also implicitly including disables interrupt before
  223. * setting a new one.
  224. */
  225. mtk_clr(hw, MTK_RTC_AL_CTL, RTC_AL_EN);
  226. /*
  227. * Avoid contention between mtk_rtc_setalarm and IRQ handler so that
  228. * disabling the interrupt and awaiting for pending IRQ handler to
  229. * complete.
  230. */
  231. synchronize_irq(hw->irq);
  232. mtk_rtc_set_alarm_or_time(hw, alrm_tm, MTK_AL);
  233. /* Restart the alarm with the new setup */
  234. mtk_w32(hw, MTK_RTC_AL_CTL, RTC_AL_ALL);
  235. return 0;
  236. }
  237. static const struct rtc_class_ops mtk_rtc_ops = {
  238. .read_time = mtk_rtc_gettime,
  239. .set_time = mtk_rtc_settime,
  240. .read_alarm = mtk_rtc_getalarm,
  241. .set_alarm = mtk_rtc_setalarm,
  242. };
  243. static const struct of_device_id mtk_rtc_match[] = {
  244. { .compatible = "mediatek,mt7622-rtc" },
  245. { .compatible = "mediatek,soc-rtc" },
  246. {},
  247. };
  248. MODULE_DEVICE_TABLE(of, mtk_rtc_match);
  249. static int mtk_rtc_probe(struct platform_device *pdev)
  250. {
  251. struct mtk_rtc *hw;
  252. struct resource *res;
  253. int ret;
  254. hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
  255. if (!hw)
  256. return -ENOMEM;
  257. platform_set_drvdata(pdev, hw);
  258. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  259. hw->base = devm_ioremap_resource(&pdev->dev, res);
  260. if (IS_ERR(hw->base))
  261. return PTR_ERR(hw->base);
  262. hw->clk = devm_clk_get(&pdev->dev, "rtc");
  263. if (IS_ERR(hw->clk)) {
  264. dev_err(&pdev->dev, "No clock\n");
  265. return PTR_ERR(hw->clk);
  266. }
  267. ret = clk_prepare_enable(hw->clk);
  268. if (ret)
  269. return ret;
  270. hw->irq = platform_get_irq(pdev, 0);
  271. if (hw->irq < 0) {
  272. dev_err(&pdev->dev, "No IRQ resource\n");
  273. ret = hw->irq;
  274. goto err;
  275. }
  276. ret = devm_request_irq(&pdev->dev, hw->irq, mtk_rtc_alarmirq,
  277. 0, dev_name(&pdev->dev), hw);
  278. if (ret) {
  279. dev_err(&pdev->dev, "Can't request IRQ\n");
  280. goto err;
  281. }
  282. mtk_rtc_hw_init(hw);
  283. device_init_wakeup(&pdev->dev, true);
  284. hw->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
  285. &mtk_rtc_ops, THIS_MODULE);
  286. if (IS_ERR(hw->rtc)) {
  287. ret = PTR_ERR(hw->rtc);
  288. dev_err(&pdev->dev, "Unable to register device\n");
  289. goto err;
  290. }
  291. return 0;
  292. err:
  293. clk_disable_unprepare(hw->clk);
  294. return ret;
  295. }
  296. static int mtk_rtc_remove(struct platform_device *pdev)
  297. {
  298. struct mtk_rtc *hw = platform_get_drvdata(pdev);
  299. clk_disable_unprepare(hw->clk);
  300. return 0;
  301. }
  302. #ifdef CONFIG_PM_SLEEP
  303. static int mtk_rtc_suspend(struct device *dev)
  304. {
  305. struct mtk_rtc *hw = dev_get_drvdata(dev);
  306. if (device_may_wakeup(dev))
  307. enable_irq_wake(hw->irq);
  308. return 0;
  309. }
  310. static int mtk_rtc_resume(struct device *dev)
  311. {
  312. struct mtk_rtc *hw = dev_get_drvdata(dev);
  313. if (device_may_wakeup(dev))
  314. disable_irq_wake(hw->irq);
  315. return 0;
  316. }
  317. static SIMPLE_DEV_PM_OPS(mtk_rtc_pm_ops, mtk_rtc_suspend, mtk_rtc_resume);
  318. #define MTK_RTC_PM_OPS (&mtk_rtc_pm_ops)
  319. #else /* CONFIG_PM */
  320. #define MTK_RTC_PM_OPS NULL
  321. #endif /* CONFIG_PM */
  322. static struct platform_driver mtk_rtc_driver = {
  323. .probe = mtk_rtc_probe,
  324. .remove = mtk_rtc_remove,
  325. .driver = {
  326. .name = MTK_RTC_DEV,
  327. .of_match_table = mtk_rtc_match,
  328. .pm = MTK_RTC_PM_OPS,
  329. },
  330. };
  331. module_platform_driver(mtk_rtc_driver);
  332. MODULE_DESCRIPTION("MediaTek SoC based RTC Driver");
  333. MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
  334. MODULE_LICENSE("GPL");