rtc-max77686.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. //
  3. // RTC driver for Maxim MAX77686 and MAX77802
  4. //
  5. // Copyright (C) 2012 Samsung Electronics Co.Ltd
  6. //
  7. // based on rtc-max8997.c
  8. #include <linux/i2c.h>
  9. #include <linux/slab.h>
  10. #include <linux/rtc.h>
  11. #include <linux/delay.h>
  12. #include <linux/mutex.h>
  13. #include <linux/module.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/mfd/max77686-private.h>
  16. #include <linux/irqdomain.h>
  17. #include <linux/regmap.h>
  18. #define MAX77686_I2C_ADDR_RTC (0x0C >> 1)
  19. #define MAX77620_I2C_ADDR_RTC 0x68
  20. #define MAX77686_INVALID_I2C_ADDR (-1)
  21. /* Define non existing register */
  22. #define MAX77686_INVALID_REG (-1)
  23. /* RTC Control Register */
  24. #define BCD_EN_SHIFT 0
  25. #define BCD_EN_MASK BIT(BCD_EN_SHIFT)
  26. #define MODEL24_SHIFT 1
  27. #define MODEL24_MASK BIT(MODEL24_SHIFT)
  28. /* RTC Update Register1 */
  29. #define RTC_UDR_SHIFT 0
  30. #define RTC_UDR_MASK BIT(RTC_UDR_SHIFT)
  31. #define RTC_RBUDR_SHIFT 4
  32. #define RTC_RBUDR_MASK BIT(RTC_RBUDR_SHIFT)
  33. /* RTC Hour register */
  34. #define HOUR_PM_SHIFT 6
  35. #define HOUR_PM_MASK BIT(HOUR_PM_SHIFT)
  36. /* RTC Alarm Enable */
  37. #define ALARM_ENABLE_SHIFT 7
  38. #define ALARM_ENABLE_MASK BIT(ALARM_ENABLE_SHIFT)
  39. #define REG_RTC_NONE 0xdeadbeef
  40. /*
  41. * MAX77802 has separate register (RTCAE1) for alarm enable instead
  42. * using 1 bit from registers RTC{SEC,MIN,HOUR,DAY,MONTH,YEAR,DATE}
  43. * as in done in MAX77686.
  44. */
  45. #define MAX77802_ALARM_ENABLE_VALUE 0x77
  46. enum {
  47. RTC_SEC = 0,
  48. RTC_MIN,
  49. RTC_HOUR,
  50. RTC_WEEKDAY,
  51. RTC_MONTH,
  52. RTC_YEAR,
  53. RTC_DATE,
  54. RTC_NR_TIME
  55. };
  56. struct max77686_rtc_driver_data {
  57. /* Minimum usecs needed for a RTC update */
  58. unsigned long delay;
  59. /* Mask used to read RTC registers value */
  60. u8 mask;
  61. /* Registers offset to I2C addresses map */
  62. const unsigned int *map;
  63. /* Has a separate alarm enable register? */
  64. bool alarm_enable_reg;
  65. /* I2C address for RTC block */
  66. int rtc_i2c_addr;
  67. /* RTC interrupt via platform resource */
  68. bool rtc_irq_from_platform;
  69. /* Pending alarm status register */
  70. int alarm_pending_status_reg;
  71. /* RTC IRQ CHIP for regmap */
  72. const struct regmap_irq_chip *rtc_irq_chip;
  73. };
  74. struct max77686_rtc_info {
  75. struct device *dev;
  76. struct i2c_client *rtc;
  77. struct rtc_device *rtc_dev;
  78. struct mutex lock;
  79. struct regmap *regmap;
  80. struct regmap *rtc_regmap;
  81. const struct max77686_rtc_driver_data *drv_data;
  82. struct regmap_irq_chip_data *rtc_irq_data;
  83. int rtc_irq;
  84. int virq;
  85. int rtc_24hr_mode;
  86. };
  87. enum MAX77686_RTC_OP {
  88. MAX77686_RTC_WRITE,
  89. MAX77686_RTC_READ,
  90. };
  91. /* These are not registers but just offsets that are mapped to addresses */
  92. enum max77686_rtc_reg_offset {
  93. REG_RTC_CONTROLM = 0,
  94. REG_RTC_CONTROL,
  95. REG_RTC_UPDATE0,
  96. REG_WTSR_SMPL_CNTL,
  97. REG_RTC_SEC,
  98. REG_RTC_MIN,
  99. REG_RTC_HOUR,
  100. REG_RTC_WEEKDAY,
  101. REG_RTC_MONTH,
  102. REG_RTC_YEAR,
  103. REG_RTC_DATE,
  104. REG_ALARM1_SEC,
  105. REG_ALARM1_MIN,
  106. REG_ALARM1_HOUR,
  107. REG_ALARM1_WEEKDAY,
  108. REG_ALARM1_MONTH,
  109. REG_ALARM1_YEAR,
  110. REG_ALARM1_DATE,
  111. REG_ALARM2_SEC,
  112. REG_ALARM2_MIN,
  113. REG_ALARM2_HOUR,
  114. REG_ALARM2_WEEKDAY,
  115. REG_ALARM2_MONTH,
  116. REG_ALARM2_YEAR,
  117. REG_ALARM2_DATE,
  118. REG_RTC_AE1,
  119. REG_RTC_END,
  120. };
  121. /* Maps RTC registers offset to the MAX77686 register addresses */
  122. static const unsigned int max77686_map[REG_RTC_END] = {
  123. [REG_RTC_CONTROLM] = MAX77686_RTC_CONTROLM,
  124. [REG_RTC_CONTROL] = MAX77686_RTC_CONTROL,
  125. [REG_RTC_UPDATE0] = MAX77686_RTC_UPDATE0,
  126. [REG_WTSR_SMPL_CNTL] = MAX77686_WTSR_SMPL_CNTL,
  127. [REG_RTC_SEC] = MAX77686_RTC_SEC,
  128. [REG_RTC_MIN] = MAX77686_RTC_MIN,
  129. [REG_RTC_HOUR] = MAX77686_RTC_HOUR,
  130. [REG_RTC_WEEKDAY] = MAX77686_RTC_WEEKDAY,
  131. [REG_RTC_MONTH] = MAX77686_RTC_MONTH,
  132. [REG_RTC_YEAR] = MAX77686_RTC_YEAR,
  133. [REG_RTC_DATE] = MAX77686_RTC_DATE,
  134. [REG_ALARM1_SEC] = MAX77686_ALARM1_SEC,
  135. [REG_ALARM1_MIN] = MAX77686_ALARM1_MIN,
  136. [REG_ALARM1_HOUR] = MAX77686_ALARM1_HOUR,
  137. [REG_ALARM1_WEEKDAY] = MAX77686_ALARM1_WEEKDAY,
  138. [REG_ALARM1_MONTH] = MAX77686_ALARM1_MONTH,
  139. [REG_ALARM1_YEAR] = MAX77686_ALARM1_YEAR,
  140. [REG_ALARM1_DATE] = MAX77686_ALARM1_DATE,
  141. [REG_ALARM2_SEC] = MAX77686_ALARM2_SEC,
  142. [REG_ALARM2_MIN] = MAX77686_ALARM2_MIN,
  143. [REG_ALARM2_HOUR] = MAX77686_ALARM2_HOUR,
  144. [REG_ALARM2_WEEKDAY] = MAX77686_ALARM2_WEEKDAY,
  145. [REG_ALARM2_MONTH] = MAX77686_ALARM2_MONTH,
  146. [REG_ALARM2_YEAR] = MAX77686_ALARM2_YEAR,
  147. [REG_ALARM2_DATE] = MAX77686_ALARM2_DATE,
  148. [REG_RTC_AE1] = REG_RTC_NONE,
  149. };
  150. static const struct regmap_irq max77686_rtc_irqs[] = {
  151. /* RTC interrupts */
  152. REGMAP_IRQ_REG(0, 0, MAX77686_RTCINT_RTC60S_MSK),
  153. REGMAP_IRQ_REG(1, 0, MAX77686_RTCINT_RTCA1_MSK),
  154. REGMAP_IRQ_REG(2, 0, MAX77686_RTCINT_RTCA2_MSK),
  155. REGMAP_IRQ_REG(3, 0, MAX77686_RTCINT_SMPL_MSK),
  156. REGMAP_IRQ_REG(4, 0, MAX77686_RTCINT_RTC1S_MSK),
  157. REGMAP_IRQ_REG(5, 0, MAX77686_RTCINT_WTSR_MSK),
  158. };
  159. static const struct regmap_irq_chip max77686_rtc_irq_chip = {
  160. .name = "max77686-rtc",
  161. .status_base = MAX77686_RTC_INT,
  162. .mask_base = MAX77686_RTC_INTM,
  163. .num_regs = 1,
  164. .irqs = max77686_rtc_irqs,
  165. .num_irqs = ARRAY_SIZE(max77686_rtc_irqs),
  166. };
  167. static const struct max77686_rtc_driver_data max77686_drv_data = {
  168. .delay = 16000,
  169. .mask = 0x7f,
  170. .map = max77686_map,
  171. .alarm_enable_reg = false,
  172. .rtc_irq_from_platform = false,
  173. .alarm_pending_status_reg = MAX77686_REG_STATUS2,
  174. .rtc_i2c_addr = MAX77686_I2C_ADDR_RTC,
  175. .rtc_irq_chip = &max77686_rtc_irq_chip,
  176. };
  177. static const struct max77686_rtc_driver_data max77620_drv_data = {
  178. .delay = 16000,
  179. .mask = 0x7f,
  180. .map = max77686_map,
  181. .alarm_enable_reg = false,
  182. .rtc_irq_from_platform = true,
  183. .alarm_pending_status_reg = MAX77686_INVALID_REG,
  184. .rtc_i2c_addr = MAX77620_I2C_ADDR_RTC,
  185. .rtc_irq_chip = &max77686_rtc_irq_chip,
  186. };
  187. static const unsigned int max77802_map[REG_RTC_END] = {
  188. [REG_RTC_CONTROLM] = MAX77802_RTC_CONTROLM,
  189. [REG_RTC_CONTROL] = MAX77802_RTC_CONTROL,
  190. [REG_RTC_UPDATE0] = MAX77802_RTC_UPDATE0,
  191. [REG_WTSR_SMPL_CNTL] = MAX77802_WTSR_SMPL_CNTL,
  192. [REG_RTC_SEC] = MAX77802_RTC_SEC,
  193. [REG_RTC_MIN] = MAX77802_RTC_MIN,
  194. [REG_RTC_HOUR] = MAX77802_RTC_HOUR,
  195. [REG_RTC_WEEKDAY] = MAX77802_RTC_WEEKDAY,
  196. [REG_RTC_MONTH] = MAX77802_RTC_MONTH,
  197. [REG_RTC_YEAR] = MAX77802_RTC_YEAR,
  198. [REG_RTC_DATE] = MAX77802_RTC_DATE,
  199. [REG_ALARM1_SEC] = MAX77802_ALARM1_SEC,
  200. [REG_ALARM1_MIN] = MAX77802_ALARM1_MIN,
  201. [REG_ALARM1_HOUR] = MAX77802_ALARM1_HOUR,
  202. [REG_ALARM1_WEEKDAY] = MAX77802_ALARM1_WEEKDAY,
  203. [REG_ALARM1_MONTH] = MAX77802_ALARM1_MONTH,
  204. [REG_ALARM1_YEAR] = MAX77802_ALARM1_YEAR,
  205. [REG_ALARM1_DATE] = MAX77802_ALARM1_DATE,
  206. [REG_ALARM2_SEC] = MAX77802_ALARM2_SEC,
  207. [REG_ALARM2_MIN] = MAX77802_ALARM2_MIN,
  208. [REG_ALARM2_HOUR] = MAX77802_ALARM2_HOUR,
  209. [REG_ALARM2_WEEKDAY] = MAX77802_ALARM2_WEEKDAY,
  210. [REG_ALARM2_MONTH] = MAX77802_ALARM2_MONTH,
  211. [REG_ALARM2_YEAR] = MAX77802_ALARM2_YEAR,
  212. [REG_ALARM2_DATE] = MAX77802_ALARM2_DATE,
  213. [REG_RTC_AE1] = MAX77802_RTC_AE1,
  214. };
  215. static const struct regmap_irq_chip max77802_rtc_irq_chip = {
  216. .name = "max77802-rtc",
  217. .status_base = MAX77802_RTC_INT,
  218. .mask_base = MAX77802_RTC_INTM,
  219. .num_regs = 1,
  220. .irqs = max77686_rtc_irqs, /* same masks as 77686 */
  221. .num_irqs = ARRAY_SIZE(max77686_rtc_irqs),
  222. };
  223. static const struct max77686_rtc_driver_data max77802_drv_data = {
  224. .delay = 200,
  225. .mask = 0xff,
  226. .map = max77802_map,
  227. .alarm_enable_reg = true,
  228. .rtc_irq_from_platform = false,
  229. .alarm_pending_status_reg = MAX77686_REG_STATUS2,
  230. .rtc_i2c_addr = MAX77686_INVALID_I2C_ADDR,
  231. .rtc_irq_chip = &max77802_rtc_irq_chip,
  232. };
  233. static void max77686_rtc_data_to_tm(u8 *data, struct rtc_time *tm,
  234. struct max77686_rtc_info *info)
  235. {
  236. u8 mask = info->drv_data->mask;
  237. tm->tm_sec = data[RTC_SEC] & mask;
  238. tm->tm_min = data[RTC_MIN] & mask;
  239. if (info->rtc_24hr_mode) {
  240. tm->tm_hour = data[RTC_HOUR] & 0x1f;
  241. } else {
  242. tm->tm_hour = data[RTC_HOUR] & 0x0f;
  243. if (data[RTC_HOUR] & HOUR_PM_MASK)
  244. tm->tm_hour += 12;
  245. }
  246. /* Only a single bit is set in data[], so fls() would be equivalent */
  247. tm->tm_wday = ffs(data[RTC_WEEKDAY] & mask) - 1;
  248. tm->tm_mday = data[RTC_DATE] & 0x1f;
  249. tm->tm_mon = (data[RTC_MONTH] & 0x0f) - 1;
  250. tm->tm_year = data[RTC_YEAR] & mask;
  251. tm->tm_yday = 0;
  252. tm->tm_isdst = 0;
  253. /*
  254. * MAX77686 uses 1 bit from sec/min/hour/etc RTC registers and the
  255. * year values are just 0..99 so add 100 to support up to 2099.
  256. */
  257. if (!info->drv_data->alarm_enable_reg)
  258. tm->tm_year += 100;
  259. }
  260. static int max77686_rtc_tm_to_data(struct rtc_time *tm, u8 *data,
  261. struct max77686_rtc_info *info)
  262. {
  263. data[RTC_SEC] = tm->tm_sec;
  264. data[RTC_MIN] = tm->tm_min;
  265. data[RTC_HOUR] = tm->tm_hour;
  266. data[RTC_WEEKDAY] = 1 << tm->tm_wday;
  267. data[RTC_DATE] = tm->tm_mday;
  268. data[RTC_MONTH] = tm->tm_mon + 1;
  269. if (info->drv_data->alarm_enable_reg) {
  270. data[RTC_YEAR] = tm->tm_year;
  271. return 0;
  272. }
  273. data[RTC_YEAR] = tm->tm_year > 100 ? (tm->tm_year - 100) : 0;
  274. if (tm->tm_year < 100) {
  275. dev_err(info->dev, "RTC cannot handle the year %d.\n",
  276. 1900 + tm->tm_year);
  277. return -EINVAL;
  278. }
  279. return 0;
  280. }
  281. static int max77686_rtc_update(struct max77686_rtc_info *info,
  282. enum MAX77686_RTC_OP op)
  283. {
  284. int ret;
  285. unsigned int data;
  286. unsigned long delay = info->drv_data->delay;
  287. if (op == MAX77686_RTC_WRITE)
  288. data = 1 << RTC_UDR_SHIFT;
  289. else
  290. data = 1 << RTC_RBUDR_SHIFT;
  291. ret = regmap_update_bits(info->rtc_regmap,
  292. info->drv_data->map[REG_RTC_UPDATE0],
  293. data, data);
  294. if (ret < 0)
  295. dev_err(info->dev, "Fail to write update reg(ret=%d, data=0x%x)\n",
  296. ret, data);
  297. else {
  298. /* Minimum delay required before RTC update. */
  299. usleep_range(delay, delay * 2);
  300. }
  301. return ret;
  302. }
  303. static int max77686_rtc_read_time(struct device *dev, struct rtc_time *tm)
  304. {
  305. struct max77686_rtc_info *info = dev_get_drvdata(dev);
  306. u8 data[RTC_NR_TIME];
  307. int ret;
  308. mutex_lock(&info->lock);
  309. ret = max77686_rtc_update(info, MAX77686_RTC_READ);
  310. if (ret < 0)
  311. goto out;
  312. ret = regmap_bulk_read(info->rtc_regmap,
  313. info->drv_data->map[REG_RTC_SEC],
  314. data, ARRAY_SIZE(data));
  315. if (ret < 0) {
  316. dev_err(info->dev, "Fail to read time reg(%d)\n", ret);
  317. goto out;
  318. }
  319. max77686_rtc_data_to_tm(data, tm, info);
  320. out:
  321. mutex_unlock(&info->lock);
  322. return ret;
  323. }
  324. static int max77686_rtc_set_time(struct device *dev, struct rtc_time *tm)
  325. {
  326. struct max77686_rtc_info *info = dev_get_drvdata(dev);
  327. u8 data[RTC_NR_TIME];
  328. int ret;
  329. ret = max77686_rtc_tm_to_data(tm, data, info);
  330. if (ret < 0)
  331. return ret;
  332. mutex_lock(&info->lock);
  333. ret = regmap_bulk_write(info->rtc_regmap,
  334. info->drv_data->map[REG_RTC_SEC],
  335. data, ARRAY_SIZE(data));
  336. if (ret < 0) {
  337. dev_err(info->dev, "Fail to write time reg(%d)\n", ret);
  338. goto out;
  339. }
  340. ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
  341. out:
  342. mutex_unlock(&info->lock);
  343. return ret;
  344. }
  345. static int max77686_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  346. {
  347. struct max77686_rtc_info *info = dev_get_drvdata(dev);
  348. u8 data[RTC_NR_TIME];
  349. unsigned int val;
  350. const unsigned int *map = info->drv_data->map;
  351. int i, ret;
  352. mutex_lock(&info->lock);
  353. ret = max77686_rtc_update(info, MAX77686_RTC_READ);
  354. if (ret < 0)
  355. goto out;
  356. ret = regmap_bulk_read(info->rtc_regmap, map[REG_ALARM1_SEC],
  357. data, ARRAY_SIZE(data));
  358. if (ret < 0) {
  359. dev_err(info->dev, "Fail to read alarm reg(%d)\n", ret);
  360. goto out;
  361. }
  362. max77686_rtc_data_to_tm(data, &alrm->time, info);
  363. alrm->enabled = 0;
  364. if (info->drv_data->alarm_enable_reg) {
  365. if (map[REG_RTC_AE1] == REG_RTC_NONE) {
  366. ret = -EINVAL;
  367. dev_err(info->dev,
  368. "alarm enable register not set(%d)\n", ret);
  369. goto out;
  370. }
  371. ret = regmap_read(info->rtc_regmap, map[REG_RTC_AE1], &val);
  372. if (ret < 0) {
  373. dev_err(info->dev,
  374. "fail to read alarm enable(%d)\n", ret);
  375. goto out;
  376. }
  377. if (val)
  378. alrm->enabled = 1;
  379. } else {
  380. for (i = 0; i < ARRAY_SIZE(data); i++) {
  381. if (data[i] & ALARM_ENABLE_MASK) {
  382. alrm->enabled = 1;
  383. break;
  384. }
  385. }
  386. }
  387. alrm->pending = 0;
  388. if (info->drv_data->alarm_pending_status_reg == MAX77686_INVALID_REG)
  389. goto out;
  390. ret = regmap_read(info->regmap,
  391. info->drv_data->alarm_pending_status_reg, &val);
  392. if (ret < 0) {
  393. dev_err(info->dev,
  394. "Fail to read alarm pending status reg(%d)\n", ret);
  395. goto out;
  396. }
  397. if (val & (1 << 4)) /* RTCA1 */
  398. alrm->pending = 1;
  399. out:
  400. mutex_unlock(&info->lock);
  401. return ret;
  402. }
  403. static int max77686_rtc_stop_alarm(struct max77686_rtc_info *info)
  404. {
  405. u8 data[RTC_NR_TIME];
  406. int ret, i;
  407. struct rtc_time tm;
  408. const unsigned int *map = info->drv_data->map;
  409. if (!mutex_is_locked(&info->lock))
  410. dev_warn(info->dev, "%s: should have mutex locked\n", __func__);
  411. ret = max77686_rtc_update(info, MAX77686_RTC_READ);
  412. if (ret < 0)
  413. goto out;
  414. if (info->drv_data->alarm_enable_reg) {
  415. if (map[REG_RTC_AE1] == REG_RTC_NONE) {
  416. ret = -EINVAL;
  417. dev_err(info->dev,
  418. "alarm enable register not set(%d)\n", ret);
  419. goto out;
  420. }
  421. ret = regmap_write(info->rtc_regmap, map[REG_RTC_AE1], 0);
  422. } else {
  423. ret = regmap_bulk_read(info->rtc_regmap, map[REG_ALARM1_SEC],
  424. data, ARRAY_SIZE(data));
  425. if (ret < 0) {
  426. dev_err(info->dev, "Fail to read alarm reg(%d)\n", ret);
  427. goto out;
  428. }
  429. max77686_rtc_data_to_tm(data, &tm, info);
  430. for (i = 0; i < ARRAY_SIZE(data); i++)
  431. data[i] &= ~ALARM_ENABLE_MASK;
  432. ret = regmap_bulk_write(info->rtc_regmap, map[REG_ALARM1_SEC],
  433. data, ARRAY_SIZE(data));
  434. }
  435. if (ret < 0) {
  436. dev_err(info->dev, "Fail to write alarm reg(%d)\n", ret);
  437. goto out;
  438. }
  439. ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
  440. out:
  441. return ret;
  442. }
  443. static int max77686_rtc_start_alarm(struct max77686_rtc_info *info)
  444. {
  445. u8 data[RTC_NR_TIME];
  446. int ret;
  447. struct rtc_time tm;
  448. const unsigned int *map = info->drv_data->map;
  449. if (!mutex_is_locked(&info->lock))
  450. dev_warn(info->dev, "%s: should have mutex locked\n", __func__);
  451. ret = max77686_rtc_update(info, MAX77686_RTC_READ);
  452. if (ret < 0)
  453. goto out;
  454. if (info->drv_data->alarm_enable_reg) {
  455. ret = regmap_write(info->rtc_regmap, map[REG_RTC_AE1],
  456. MAX77802_ALARM_ENABLE_VALUE);
  457. } else {
  458. ret = regmap_bulk_read(info->rtc_regmap, map[REG_ALARM1_SEC],
  459. data, ARRAY_SIZE(data));
  460. if (ret < 0) {
  461. dev_err(info->dev, "Fail to read alarm reg(%d)\n", ret);
  462. goto out;
  463. }
  464. max77686_rtc_data_to_tm(data, &tm, info);
  465. data[RTC_SEC] |= (1 << ALARM_ENABLE_SHIFT);
  466. data[RTC_MIN] |= (1 << ALARM_ENABLE_SHIFT);
  467. data[RTC_HOUR] |= (1 << ALARM_ENABLE_SHIFT);
  468. data[RTC_WEEKDAY] &= ~ALARM_ENABLE_MASK;
  469. if (data[RTC_MONTH] & 0xf)
  470. data[RTC_MONTH] |= (1 << ALARM_ENABLE_SHIFT);
  471. if (data[RTC_YEAR] & info->drv_data->mask)
  472. data[RTC_YEAR] |= (1 << ALARM_ENABLE_SHIFT);
  473. if (data[RTC_DATE] & 0x1f)
  474. data[RTC_DATE] |= (1 << ALARM_ENABLE_SHIFT);
  475. ret = regmap_bulk_write(info->rtc_regmap, map[REG_ALARM1_SEC],
  476. data, ARRAY_SIZE(data));
  477. }
  478. if (ret < 0) {
  479. dev_err(info->dev, "Fail to write alarm reg(%d)\n", ret);
  480. goto out;
  481. }
  482. ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
  483. out:
  484. return ret;
  485. }
  486. static int max77686_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  487. {
  488. struct max77686_rtc_info *info = dev_get_drvdata(dev);
  489. u8 data[RTC_NR_TIME];
  490. int ret;
  491. ret = max77686_rtc_tm_to_data(&alrm->time, data, info);
  492. if (ret < 0)
  493. return ret;
  494. mutex_lock(&info->lock);
  495. ret = max77686_rtc_stop_alarm(info);
  496. if (ret < 0)
  497. goto out;
  498. ret = regmap_bulk_write(info->rtc_regmap,
  499. info->drv_data->map[REG_ALARM1_SEC],
  500. data, ARRAY_SIZE(data));
  501. if (ret < 0) {
  502. dev_err(info->dev, "Fail to write alarm reg(%d)\n", ret);
  503. goto out;
  504. }
  505. ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
  506. if (ret < 0)
  507. goto out;
  508. if (alrm->enabled)
  509. ret = max77686_rtc_start_alarm(info);
  510. out:
  511. mutex_unlock(&info->lock);
  512. return ret;
  513. }
  514. static int max77686_rtc_alarm_irq_enable(struct device *dev,
  515. unsigned int enabled)
  516. {
  517. struct max77686_rtc_info *info = dev_get_drvdata(dev);
  518. int ret;
  519. mutex_lock(&info->lock);
  520. if (enabled)
  521. ret = max77686_rtc_start_alarm(info);
  522. else
  523. ret = max77686_rtc_stop_alarm(info);
  524. mutex_unlock(&info->lock);
  525. return ret;
  526. }
  527. static irqreturn_t max77686_rtc_alarm_irq(int irq, void *data)
  528. {
  529. struct max77686_rtc_info *info = data;
  530. dev_dbg(info->dev, "RTC alarm IRQ: %d\n", irq);
  531. rtc_update_irq(info->rtc_dev, 1, RTC_IRQF | RTC_AF);
  532. return IRQ_HANDLED;
  533. }
  534. static const struct rtc_class_ops max77686_rtc_ops = {
  535. .read_time = max77686_rtc_read_time,
  536. .set_time = max77686_rtc_set_time,
  537. .read_alarm = max77686_rtc_read_alarm,
  538. .set_alarm = max77686_rtc_set_alarm,
  539. .alarm_irq_enable = max77686_rtc_alarm_irq_enable,
  540. };
  541. static int max77686_rtc_init_reg(struct max77686_rtc_info *info)
  542. {
  543. u8 data[2];
  544. int ret;
  545. /* Set RTC control register : Binary mode, 24hour mdoe */
  546. data[0] = (1 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
  547. data[1] = (0 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
  548. info->rtc_24hr_mode = 1;
  549. ret = regmap_bulk_write(info->rtc_regmap,
  550. info->drv_data->map[REG_RTC_CONTROLM],
  551. data, ARRAY_SIZE(data));
  552. if (ret < 0) {
  553. dev_err(info->dev, "Fail to write controlm reg(%d)\n", ret);
  554. return ret;
  555. }
  556. ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
  557. return ret;
  558. }
  559. static const struct regmap_config max77686_rtc_regmap_config = {
  560. .reg_bits = 8,
  561. .val_bits = 8,
  562. };
  563. static int max77686_init_rtc_regmap(struct max77686_rtc_info *info)
  564. {
  565. struct device *parent = info->dev->parent;
  566. struct i2c_client *parent_i2c = to_i2c_client(parent);
  567. int ret;
  568. if (info->drv_data->rtc_irq_from_platform) {
  569. struct platform_device *pdev = to_platform_device(info->dev);
  570. info->rtc_irq = platform_get_irq(pdev, 0);
  571. if (info->rtc_irq < 0) {
  572. dev_err(info->dev, "Failed to get rtc interrupts: %d\n",
  573. info->rtc_irq);
  574. return info->rtc_irq;
  575. }
  576. } else {
  577. info->rtc_irq = parent_i2c->irq;
  578. }
  579. info->regmap = dev_get_regmap(parent, NULL);
  580. if (!info->regmap) {
  581. dev_err(info->dev, "Failed to get rtc regmap\n");
  582. return -ENODEV;
  583. }
  584. if (info->drv_data->rtc_i2c_addr == MAX77686_INVALID_I2C_ADDR) {
  585. info->rtc_regmap = info->regmap;
  586. goto add_rtc_irq;
  587. }
  588. info->rtc = i2c_new_dummy(parent_i2c->adapter,
  589. info->drv_data->rtc_i2c_addr);
  590. if (!info->rtc) {
  591. dev_err(info->dev, "Failed to allocate I2C device for RTC\n");
  592. return -ENODEV;
  593. }
  594. info->rtc_regmap = devm_regmap_init_i2c(info->rtc,
  595. &max77686_rtc_regmap_config);
  596. if (IS_ERR(info->rtc_regmap)) {
  597. ret = PTR_ERR(info->rtc_regmap);
  598. dev_err(info->dev, "Failed to allocate RTC regmap: %d\n", ret);
  599. goto err_unregister_i2c;
  600. }
  601. add_rtc_irq:
  602. ret = regmap_add_irq_chip(info->rtc_regmap, info->rtc_irq,
  603. IRQF_TRIGGER_FALLING | IRQF_ONESHOT |
  604. IRQF_SHARED, 0, info->drv_data->rtc_irq_chip,
  605. &info->rtc_irq_data);
  606. if (ret < 0) {
  607. dev_err(info->dev, "Failed to add RTC irq chip: %d\n", ret);
  608. goto err_unregister_i2c;
  609. }
  610. return 0;
  611. err_unregister_i2c:
  612. if (info->rtc)
  613. i2c_unregister_device(info->rtc);
  614. return ret;
  615. }
  616. static int max77686_rtc_probe(struct platform_device *pdev)
  617. {
  618. struct max77686_rtc_info *info;
  619. const struct platform_device_id *id = platform_get_device_id(pdev);
  620. int ret;
  621. info = devm_kzalloc(&pdev->dev, sizeof(struct max77686_rtc_info),
  622. GFP_KERNEL);
  623. if (!info)
  624. return -ENOMEM;
  625. mutex_init(&info->lock);
  626. info->dev = &pdev->dev;
  627. info->drv_data = (const struct max77686_rtc_driver_data *)
  628. id->driver_data;
  629. ret = max77686_init_rtc_regmap(info);
  630. if (ret < 0)
  631. return ret;
  632. platform_set_drvdata(pdev, info);
  633. ret = max77686_rtc_init_reg(info);
  634. if (ret < 0) {
  635. dev_err(&pdev->dev, "Failed to initialize RTC reg:%d\n", ret);
  636. goto err_rtc;
  637. }
  638. device_init_wakeup(&pdev->dev, 1);
  639. info->rtc_dev = devm_rtc_device_register(&pdev->dev, id->name,
  640. &max77686_rtc_ops, THIS_MODULE);
  641. if (IS_ERR(info->rtc_dev)) {
  642. ret = PTR_ERR(info->rtc_dev);
  643. dev_err(&pdev->dev, "Failed to register RTC device: %d\n", ret);
  644. if (ret == 0)
  645. ret = -EINVAL;
  646. goto err_rtc;
  647. }
  648. info->virq = regmap_irq_get_virq(info->rtc_irq_data,
  649. MAX77686_RTCIRQ_RTCA1);
  650. if (info->virq <= 0) {
  651. ret = -ENXIO;
  652. goto err_rtc;
  653. }
  654. ret = request_threaded_irq(info->virq, NULL, max77686_rtc_alarm_irq, 0,
  655. "rtc-alarm1", info);
  656. if (ret < 0) {
  657. dev_err(&pdev->dev, "Failed to request alarm IRQ: %d: %d\n",
  658. info->virq, ret);
  659. goto err_rtc;
  660. }
  661. return 0;
  662. err_rtc:
  663. regmap_del_irq_chip(info->rtc_irq, info->rtc_irq_data);
  664. if (info->rtc)
  665. i2c_unregister_device(info->rtc);
  666. return ret;
  667. }
  668. static int max77686_rtc_remove(struct platform_device *pdev)
  669. {
  670. struct max77686_rtc_info *info = platform_get_drvdata(pdev);
  671. free_irq(info->virq, info);
  672. regmap_del_irq_chip(info->rtc_irq, info->rtc_irq_data);
  673. if (info->rtc)
  674. i2c_unregister_device(info->rtc);
  675. return 0;
  676. }
  677. #ifdef CONFIG_PM_SLEEP
  678. static int max77686_rtc_suspend(struct device *dev)
  679. {
  680. if (device_may_wakeup(dev)) {
  681. struct max77686_rtc_info *info = dev_get_drvdata(dev);
  682. return enable_irq_wake(info->virq);
  683. }
  684. return 0;
  685. }
  686. static int max77686_rtc_resume(struct device *dev)
  687. {
  688. if (device_may_wakeup(dev)) {
  689. struct max77686_rtc_info *info = dev_get_drvdata(dev);
  690. return disable_irq_wake(info->virq);
  691. }
  692. return 0;
  693. }
  694. #endif
  695. static SIMPLE_DEV_PM_OPS(max77686_rtc_pm_ops,
  696. max77686_rtc_suspend, max77686_rtc_resume);
  697. static const struct platform_device_id rtc_id[] = {
  698. { "max77686-rtc", .driver_data = (kernel_ulong_t)&max77686_drv_data, },
  699. { "max77802-rtc", .driver_data = (kernel_ulong_t)&max77802_drv_data, },
  700. { "max77620-rtc", .driver_data = (kernel_ulong_t)&max77620_drv_data, },
  701. {},
  702. };
  703. MODULE_DEVICE_TABLE(platform, rtc_id);
  704. static struct platform_driver max77686_rtc_driver = {
  705. .driver = {
  706. .name = "max77686-rtc",
  707. .pm = &max77686_rtc_pm_ops,
  708. },
  709. .probe = max77686_rtc_probe,
  710. .remove = max77686_rtc_remove,
  711. .id_table = rtc_id,
  712. };
  713. module_platform_driver(max77686_rtc_driver);
  714. MODULE_DESCRIPTION("Maxim MAX77686 RTC driver");
  715. MODULE_AUTHOR("Chiwoong Byun <woong.byun@samsung.com>");
  716. MODULE_LICENSE("GPL");